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1 EV-LN Page No. Schematic Page Title lock iagram Power Supply & RST LN (Part) opper Mode Interface Fiber - SFP Interface STRP,GPIO,I & FXLOS LN (Part) hennai EV-LN TITLE LN oard EV-LN-REV- ate: Tuesday, June, Sheet of
2 EV-LN lock iagram Pin MII onnector (Female) Pin MII onnector (Male) RMII Mode Switch Port Power Supply Module I EEPROM/ Header Microchip LN Reset Switch Straps Jumpers rystal Port Port Fiber Trasnceiver- (SFP) Port / Ethernet Magnetics & RJ / Ethernet Magnetics & RJ Fiber Trasnceiver- (SFP) Port hennai EV-LN lock iagram LN oard EV-LN-REV- ate: Friday, June, Sheet of
3 POWER SUPPLY J PJ-H V_EXT SW Switch, SPT, Slide P/N:MSQE V_SW F /.R V R uf V TP RE EN_.uF. V REGULTOR, ( V fixed when Rb=) U VIN ENLE _mp VOUT TRIM GN OKR-T/-W- R.K % (Ra) VOUT_V R % (Rb) R E % uf.uf TP ORNGE V.uF "V Present" V R K GRN V V V SW sw_pb_p Reset Switch R.K /W % R /W %.uf U MR# GN V RESET# RESET TPS SOT_ Threshold =.V elay = ms NSN_NMOS Q R K G S R.K % RST# V U LVG R.K RE "Reset" Reset Generator hennai EV-LN Power Supply & RESET LN oard EV-LN-REV- ate: Friday, June, Sheet of
4 V VTXRX Power Supply Filtering F F /.R.uF /.R.uF.uF VTXRX.uF V F /.R LMEGSN.uF VTXRX VTXRX V V VR TP SMT F /.R LMEGSN VTX VTX.uF.uF.uF.uF V.uF.uF.uF.uF.uF Low ESR uf VTX VTX.uF VR pf.uf.uf Note: OSVSS need to connect to hip gnd. pf pf Y.MHz ppm V R.K % OSI OSO RST# TP IRQ WHITE TEST/FXLOSEN I_SL I_S GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO REG_EN RIS U POWER OSV OSI OSO OSVSS REG_EN RIS RST# IRQ VTXRX VTXRX TEST/FXLOSEN TESTMOE VIS V ISL/EESL/TK IS/EES/TMS OS OTHER SIGNLS VIO_ VIO_ VIO_ VIO_ VIO_ I GPIO/LE/TO/LEPOL/MNGT GPIO/LE/TI/LEPOL GPIO/LE/LEPOL/EPSIZE GPIO/LE/LEPOL/EEEEN GPIO/LE/LEPOL/EN GPIO/LE/LEPOL/PHY GPIO GPIO INT PORT INT PORT LN_QFN VR_ VR_ VR_ VTX VTX FXSEN/FXS/FXLOS TXN TXP RXN RXP TXN TXP RXN RXP FXSEN/FXS/FXLOS Reserved GN FXS/FXLOS TXN TXP RXN RXP TXN TXP RXN RXP FXS/FXLOS hennai EV-LN LN (Part) LN oard EV-LN-REV- ate: Friday, June, Sheet of
5 PORT TXP R R TXN R R VTXRX F FX_SFP-TXP FX_SFP-TXN OP-TXP R. /W % OP-TXN R. /W % R. /W % R. /W % R T Pulse JNL T+ TXT T- XMIT LINK/T LE_THOE GRN RJ & R LE_NOE efault assembly RXP RXN R R R R FX_SFP-RXP FX_SFP-RXN OP-RXP OP-RXN pf V % pf V % pf V % pf V %.uf V % R+ RXT R- N HS GN GN GN RV MTG pf kv YEL MTG & LE (Green) = LINK/T LE (Yellow) = SPEE Note: apacitors through are optional for EMI purposes and are not populated on the EV evaluation board. These capacitors are required for operation in an EMI constrained environment. R RES LE_THOE SPEE R LE_NOE PORT TXP R R TXN R R VTXRX F FX_SFP-TXP FX_SFP-TXN OP-TXP R. /W % OP-TXN R. /W % R. /W % R. /W % R T Pulse JNL T+ TXT T- XMIT LINK/T LE_THOE GRN RJ & R LE_NOE RXP RXN R R R R FX_SFP-RXP FX_SFP-RXN Note: F and F to be zero ohms OP-RXP OP-RXN pf V % pf V % pf V % pf V %.uf V % R+ RXT R- N HS GN GN GN RV MTG pf kv YEL MTG & LE (Green) = LINK/T LE (Yellow) = SPEE Note: apacitors through are optional for EMI purposes and are not populated on the EV evaluation board. These capacitors are required for operation in an EMI constrained environment. R RES LE_THOE SPEE R LE_NOE hennai EV-LN opper Mode Interface LN oard EV-LN-REV- ate: Friday, June, Sheet of
6 FX_SFP-RXN R R V R. R. Note:Place capacitors, and resistors close to FOT.uF ssemble at,,, Fiber Port :SFP Interface FX_SFP-RXN R R V R. R. Note:Place capacitors, and resistors close to FOT.uF ssemble at,,, Fiber Port :SFP Interface FX_SFP-RXP.uF FX_SFP-RXP.uF FX_SFP-TXP FX_SFP-TXN R R.uF R.uF SFP_T- SFP_T+ SFP_R+ SFP_R- SFP_VT SFP_VR + uf V L.uF uh + uf V V.uF FX_SFP-TXP FX_SFP-TXN R R.uF.uF R SFP_T- SFP_T+ SFP_R+ SFP_R- SFP_VT SFP_VR + uf V L.uF uh + uf V V.uF L uh L uh Note:Place resistors close to SI SFP_VT J FTLFP VeeR R+ R- VeeR VeeT T- T+ VeeT VccT VccR VeeT T- T+ VeeT VeeT TXFault TX isable MO-EF() MO-EF () MO-EF () Rate Select LOS VeeR VeeR + uf V.uF Note:Place resistors close to SI SFP_VT J FTLFP VeeR R+ R- VeeR VccT VccR VeeT TXFault TX isable MO-EF() MO-EF () MO-EF () Rate Select LOS VeeR VeeR + uf V.uF R.K R.K R.K R.K R.K R.K R.K R.K FXS/FXLOS FXS/FXLOS Note: Fiber mode related components are Not Populated on EV (efault) hennai EV-LN Fiber-SFP Interface LN oard EV-LN-REV- ate: Friday, June, Sheet of
7 V GPIO V GPIO GPIO [:] & LE_POL_Strap V V V V GPIO GPIO GPIO GPIO I EEPROM V V R R R.K J R J LE_NOE LE_NOE LE_THOE LE_THOE R R.K R.K J R K J LE_NOE LE_NOE LE_THOE LE_THOE R K R.K R.K J R J LE_NOE LE_NOE LE_THOE LE_THOE R R.K R.K U WP F-I/P V GN S SL.uF K K Note: U: I IP Socket. ifferent sizes can be mounted I EEPROM Lower size elow K(K X ) I EEPROM Higher size bove K(K X ) [efault-kit] I_S I_SL J J J J J J GPIO GPIO GPIO GPIO GPIO GPIO FX_Los_Strap_ & V LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE Port LEs SPEE GRN FULL UPLEX / ollision GRN LINK/T GRN LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE Port LEs SPEE GRN FULL UPLEX / ollision GRN LINK/T GRN GPIO R V K J V R R Ref.Voltage Function Poupulate V bove V selects FX-LOS for ports and Poupulate Poupulate V (efault) Poupulate (efault) (efault) Level of. V selects FX-LOS for port and FX-S/copper twisted pair for port further determined by FXS Level of V Selects FX-S / copper twisted pair for ports and further determined by FXS and FXS. TEST/FXLOSEN R K R K Strap Name Logic onnector LE Polarity Strap GPIO R K LE/GPIO/MNGT J,J (&) J,J (&) (efault) The LE is set as active high. The LE is set as active low, J FX_Mode_Strap_ & V LE/GPIO LE/GPIO/EPSIZE LE/GPIO/EEEEN LE/GPIO/EN LE/GPIO/PHY J,J (&) J,J (&) (efault) J,J (&) J,J (&) (efault) J,J (&) J,J (&) (efault) J,J (&) J,J (&) (efault) J,J (&) (efault) J,J (&) The LE is set as active high. The LE is set as active low, The LE is set as active high. EEPROM Size=K bits ( x ) through K bits (K x ) The LE is set as active low, EEPROM Size=K bits (K x ) through K bits (K x ) or Mbits (K x ) (LN only) The LE is set as active high. EEE isable The LE is set as active low, EEE Enable The LE is set as active high. isable The LE is set as active low, Enable The LE is set as active high. PHY=,, The LE is set as active low, PHY =,, GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO = LE/TO/LEPOL/MNGT GPIO = LE/TI/LEPOL GPIO = LE/LEPOL/EPSIZE GPIO = LE/LEPOL/EEEEN GPIO = LE/LEPOL/EN GPIO = LE/LEPOL/PHY J HEER FXS/FXLOS FXS/FXLOS R R R R K K K K V PORT PORT PORT MOE opper (efault) Fiber opper (efault) Fiber Poupulate EV-LN STRP,GPIO,I & FXLOS LN oard EV-LN-REV- ate: Monday, June, Sheet of R R R R R R R R hennai
8 P_REF_LK_MOE_RES P_MIO P_M P_OUT_MOE_RES P_OUT_MOE_RES P_OUTV R M_TXLK M_RXLK P_INV P_IN P_IN RS V J +V[] MIO M RX RX RX RX RX_V RX_LK RX_ER TX_ER TX_LK TX_EN TX TX TX TX OL RS +V[] MP - -- uf.uf M +V[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] +V[] MII_R MII Male for External M oard PORT V uf P_OUT_MOE_RES P_OUT_MOE_RES P_REF_LK_MOE_RES P_IN P_IN Place near to I R R R R R P_SPEE R efault - Open Note: The P_SPEE & P_UPLEX pins are typically connected to the speed & duplex indication of the external PHY efault - Open Emulated Link Partner efault dvertised bility for Port J (P_UPLEX) - J (P_SPEE) P_SPEE P_OUT_MOE P_OUT_MOE P_OUTV P_REF_LK_MOE P_INV J K - P_UPLEX P_M P_MIO uplex Strap_ V Speed Strap_ U P_SPEE P_OUT/P_MOE P_OUT/P_MOE P_OUTV P_REFLK/P_MOE P_INV P_IN P_IN P_UPLEX P_M P_MIO P_UPLEX R LN_QFN VERTISE LINK PRTNER ILITY (its,,,) SE-T full-duplex () SE-X full-duplex () (efault) SE-T half-duplex () SE-X half-duplex () K J V P_REF_LK_MOE_RES P_OUT_MOE_RES P_OUT_MOE_RES P_MOE (SW) R R R P_MOE (SW) SW K K Port Mode strap Mapping P_MOE (SW) x Short - Short - x Short - Short - Short - Short - Short - Short - x Short - Short - x Short - Short - Short - Short - Short - Short - JSQN SW JSQN SW K JSQN V V V MOE RMII M clock in RMII M clock out ma RMII M clock out ma (efault) RMII PHY clock in P_MOE P_MOE P_MOE RMII PHY clock out ma RMII PHY clock out ma.uf RMII RX lock onfigurations Note: For Switches to short -, Knob Position should be at - and vice versa. For RMII P_MIO P_M P_IN P_IN P_INV PHY_RXLK P_REF_LK_MOE_RES R PHY_TXLK P_OUTV P_OUT_MOE_RES P_OUT_MOE_RES P_INV RS RS J hassis hassis FEMLE MII ONN MP - - M_TXLK PHY_TXLK Switch Settings SW (-) efault SW (-) SW (-) efault SW (-) SW JSQN SW JSQN M_RXLK efault Short - PHY_RXLK efault Short - escription TX lock used as a Reference lock RX lock used as a Reference lock Reference clock used as a TX clock Reference clock used as a RX clock Mode RMII M RMII M RMII PHY RMII PHY TP TP I_SL I_S P_MIO P_M ardvark - I onnector.k K HEER X J R R Pullup for MIO(common for all PHY) signal V V R K P_INV MII Female for External PHY oard PORT Note:. For Switches to short -, Knob Position should be at - and vice versa.. External PHY considered LN hennai EV-LN LN-Part LN oard EV-LN-REV- ate: Monday, June, Sheet of
EVB-LAN9353 LAN9353 (Config 9 and 10)
EV-LN LN (onfig and ) Page No. Schematic Page Title lock iagram Power Supply & RST LN(Part) opper Mode Interface Fiber- SFP Interface STRP,GPIO,I & FXLOS Strap LN(Part) MII Interface hennai EV-LN TITLE
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