EVB-LAN9353 LAN9353 (Config 9 and 10)

Transcription

1 EV-LN LN (onfig and ) Page No. Schematic Page Title lock iagram Power Supply & RST LN(Part) opper Mode Interface Fiber- SFP Interface STRP,GPIO,I & FXLOS Strap LN(Part) MII Interface hennai EV-LN TITLE oard Name: LN Name: EV-LN-REV- ate: Monday, June, Sheet of

2 EV-LN lock iagram (onfig ) EV-LN lock iagram (onfig ) Pin MII onnector (Female) Pin MII onnector (Male) Pin MII onnector (Male) Pin MII onnector (Female) Pin MII onnector (Female) Pin MII onnector (Male) MII/RMII/TMII RMII RMII Mode Port Power Supply Module Mode Port Port Power Supply Module I EEPROM/ Header Microchip LN Reset I EEPROM/ Header Microchip LN Reset Straps Jumpers Port Port rystal Straps Jumpers Port rystal Fiber Trasnceiver- (SFP) Port / Ethernet Magnetics & RJ / Ethernet Magnetics & RJ Fiber Trasnceiver- (SFP) Port / Ethernet Magnetics & RJ Fiber Trasnceiver- (SFP) Port hennai EV-LN lock iagram oard Name: LN Name: EV-LN-REV- ate: Friday, June, Sheet of

3 POWER SUPPLY J PJ-H V_EXT SW F V_SW /.R, SPT, Slide P/N:MSQE V TP RE R uf V EN_.V REGULTOR, ( V fixed when Rb=e) U VIN VOUT ENLE TRIM _mp GN.uF OKR-T/-W- VOUT_V R R E.K % % (Ra) (Rb) R E % uf.uf TP ORNGE V.uF V R K "V Present" GRN V V V SW sw_pb_p R.K /W % R /W %.uf U MR# GN V RESET# RESET TPS SOT_ Threshold =.V elay = ms R NSN_NMOS K G Q S R.K % RST# V U LVG R.K RE "Reset" Reset Generator TP LK TP LK hennai EV-LN Power Supply & RST oard Name: LN Name: EV-LN-REV- ate: Friday, June, Sheet of

4 V VTXRX Power Supply Filtering F F /.R.uF /.R.uF.uF VTXRX.uF V F /.R LMEGSN.uF VTXRX VTXRX V V VR TP SMT F /.R VTX VTX.uF.uF.uF.uF V.uF.uF Low ESR uf VTX VTX.uF.uF.uF.uF VR pf.uf.uf Note: OSVSS need to connect to hip gnd. pf pf Y.MHz ppm V R.K % TP WHITE OSI OSO IRQ TEST/FXLOSEN I_SL I_S GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO RST# REG_EN RIS U POWER OSV OSI OSO OSVSS REG_EN RIS RST# IRQ VTXRX VTXRX TEST/FXLOSEN TESTMOE VIS V ISL/EESL/TK IS/EES/TMS VIO_ VIO_ VIO_ VIO_ VIO_ OS OTHER SIGNLS I LN INT PORT INT PORT GPIO/LE/TO/LEPOL/MNGT GPIO/LE/TI/LEPOL/P_INTPHY GPIO/LE/LEPOL/EPSIZE GPIO/LE/LEPOL/EEEEN GPIO/LE/LEPOL/EN GPIO/LE/LEPOL/PHY GPIO GPIO VR_ VR_ VR_ VTX VTX FXSEN/FXS/FXLOS TXN TXP RXN RXP TXN TXP RXN RXP FXSEN/FXS/FXLOS GN FXS/FXLOS TXN TXP RXN RXP TXN TXP RXN RXP FXS/FXLOS hennai EV-LN LN(Part) oard Name: LN Name: EV-LN-REV- ate: Friday, June, Sheet of

5 VTXRX LE_THOE LINK/T R E LE_NOE PORT TXP R R TXN R R F FX_SFP-TXP FX_SFP-TXN E R. /W % OP-TXP OP-TXN R. /W % R. /W % R. /W % R T Pulse JNL XMIT T TXT T- GRN RJ & efault assembly RXP RXN R R R R FX_SFP-RXP FX_SFP-RXN OP-RXP OP-RXN R RXT R- N HS GN GN GN RV pf kv YEL & LE (Green) = LINK/T LE (Yellow) = SPEE MTG MTG pf V % pf V % pf V % pf V %.uf V % Note: apacitors through are optional for EMI purposes and are not populated on the LN/ evaluation board. These capacitors are required for operation in an EMI constrained environment. R RES LE_THOE SPEE R E LE_NOE PORT TXP R R TXN R R VTXRX F FX_SFP-TXP FX_SFP-TXN E R. /W % OP-TXP OP-TXN R. /W % R. /W % R. /W % R T Pulse JNL XMIT T TXT T- LE_THOE LINK/T GRN R RJ & E LE_NOE RXP RXN R FX_SFP-RXP R R FX_SFP-RXN R Note: F and F to be zero ohms OP-RXP OP-RXN pf V % pf V % pf V % pf V %.uf V % R RXT R- N HS GN GN GN RV MTG pf kv YEL MTG & LE (Green) = LINK/T LE (Yellow) = SPEE Note: apacitors through are optional for EMI purposes and are not populated on the LN/ evaluation board. These capacitors are required for operation in an EMI constrained environment. R RES LE_THOE SPEE R E LE_NOE hennai EV-LN opper Mode Interface oard Name: LN Name: EV-LN-REV- ate: Friday, June, Sheet of

6 FX_SFP-RXN R R V R. R. Note:Place capacitors, and resistors close to FOT.uF ssemble E at,,, Fiber Port :SFP Interface FX_SFP-RXN R R V R. R. Note:Place capacitors, and resistors close to FOT.uF ssemble E at,,, Fiber Port :SFP Interface FX_SFP-RXP.uF FX_SFP-RXP.uF FX_SFP-TXP FX_SFP-TXN R R.uF.uF R SFP_T- SFP_T SFP_R SFP_R- SFP_VT SFP_VR uf V L.uF uh V uf V.uF FX_SFP-TXP FX_SFP-TXN R R.uF R.uF SFP_T- SFP_T SFP_R SFP_R- SFP_VT SFP_VR uf V L.uF uh V uf V.uF L uh L uh Note:Place resistors close to SI SFP_VT J FTLFP VeeR R R- VeeR VeeT T- T VeeT VccT VccR VeeT T- T VeeT VeeT TXFault TX isable MO-EF() MO-EF () MO-EF () Rate Select LOS VeeR VeeR uf V.uF Note:Place resistors close to SI SFP_VT J FTLFP VeeR R R- VeeR VccT VccR VeeT TXFault TX isable MO-EF() MO-EF () MO-EF () Rate Select LOS VeeR VeeR uf V.uF R.K R.K R.K R.K R.K R.K R.K R.K FXS/FXLOS FXS/FXLOS Note: Fiber mode related components are Not Populated on EV (efault) hennai EV-LN Fiber-SFP Interface oard Name: LN Name: EV-LN-REV- ate: Friday, June, Sheet of

7 V GPIO V GPIO GPIO [:] & LE_POL_Strap V V V V GPIO GPIO GPIO GPIO I EEPROM V V R R R.K J R E LE_NOE LE_NOE LE_THOE LE_THOE J J R E R.K J R.K J J R K J LE_NOE LE_NOE LE_THOE LE_THOE R K R.K J R.K J R E J LE_NOE LE_NOE LE_THOE LE_THOE I_S Note: U: I IP Socket. ifferent sizes can be mounted I EEPROM Lower size elow K(K X ) I EEPROM Higher size bove K(K X ) [efault-kit] I_SL J R E R.K J R.K U WP F-I/P V GN S SL.uF K K GPIO LE_NOE LE_THOE LE_NOE LE_THOE GPIO LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE GPIO Port LEs SPEE GRN FULL UPLEX / ollision GRN LINK/T GRN GPIO LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE LE_NOE LE_THOE GPIO Port LEs SPEE GRN FULL UPLEX / ollision GRN LINK/T GRN GPIO V I_SL I_S ardvark - I onnector J HEER X PORT PORT PORT MOE opper (efault) Fiber opper (efault) Fiber Poupulate R R R R FX_Mode_Strap_ & V R K FXS/FXLOS R K V R K FXS/FXLOS R K Strap Name LE/GPIO/MNGT LE/GPIO LE/GPIO/EPSIZE LE/GPIO/EEEEN LE/GPIO/EN LE/GPIO/PHY Logic onnector J,J (&) J,J (&) (efault) J,J (&) J,J (&) (efault) J,J (&) J,J (&) (efault) J,J (&) J,J (&) (efault) J,J (&) J,J (&) (efault) J,J (&) (efault) J,J (&) LE Polarity Strap The LE is set as active high. The LE is set as active low, The LE is set as active high. The LE is set as active low, The LE is set as active high. EEPROM Size=K bits ( x ) through K bits (K x ) The LE is set as active low, EEPROM Size=K bits (K x ) through K bits (K x ) or Mbits (K x ) (LN only) The LE is set as active high. EEE isable The LE is set as active low, EEE Enable The LE is set as active high. isable The LE is set as active low, Enable The LE is set as active high. PHY=,, The LE is set as active low, PHY =,, GPIO R GPIO R GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO K K J J V J HEER R R Ref.Voltage Function Poupulate V bove V selects FX-LOS for ports and Poupulate Poupulate V (efault) Poupulate (efault) (efault) Level of. V selects FX-LOS for port and FX-S/copper twisted pair for port further determined by FXS Level of V Selects FX-S / copper twisted pair for ports and further determined by FXS and FXS. FX_Los_Strap_ & V R K TEST/FXLOSEN R K hennai EV-LN STRP,GPIO,I & FXLOS oard Name: LN Name: EV-LN-REV- ate: Monday, June, Sheet of

8 V V SW P_OUT/REF_LK_MOE R.K P_OUT_MOE P_OUT_MOE R.K R.K Port (RMII) MOE STRP Mapping P_INTPHY : P_MOE P_MOE P_MOE Port Mode J and J SW SW SW x RMII M clock in Short - Short - Short - open (RMII pin remap mode) x x x x Short - Short - Short - Short - Short - Short - Short - Short - Short - Short - Short - open Short - Short - Short - Short - Short - open Short - Short - open Short - Short - open RMII M clock out ma RMII M clock out ma RMII PHY clock in RMII PHY clock out ma RMII PHY clock out ma Internal PHY JSQN SW P_MOE P_MOE P_MOE Note: For es to short -, Knob Position should be at - and vice versa. Note: ONFIG or ONFIG must be configured before P/P mode configurations onfig : Port and Port : External (RMII) and Port : Internal JSQN SW JSQN V V P_REFLK_MOE/P_INLK P_OUT_MOE/P_OUT_MOE P_OUT_MOE/P_OUT R.K R.K R.K SW JSQN SW JSQN SW JSQN V V P_MOE P_MOE & P_MOE P_MOE onfig Port : External (MII/RMII/TMII) Port and Port : Internal Port MOE STRP Mapping P_INTPHY : P_MOE P_MOE P_MOE P_MOE J and J SW SW SW SW x x Short - Short - Short - N N x Short - Short - Short - Short - N Short - Short - Short - Short - Short - Short - Short - Short - Short - Short - x x Short - Short - Short - Short - N x Short - Short - Short - Short - Short - x Short - Short - Short - Short - Short - x x Short - Short - Short - Short - N x Short - Short - Short - Short - Short - x o P_REFLK_MOE/P_INLK P_OUT_MOE/P_OUT P_OUT_MOE/P_OUT_MOE P_OUT_MOE P_OUT_MOE P_OUT/REF_LK_MOE MOE MII M MII PHY Turbo MII PHY ma Turbo MII PHY ma RMII M clock in RMII M clock out ma RMII M clock out ma RMII PHY clock in RMII PHY clock out ma RMII PHY clock out ma hennai EV-LN Strap oard Name: LN Name: EV-LN-REV- ate: Monday, June, Sheet of

9 Jumper settings for ONFIG or ONFIG SW - - SW - - SW SW SW SW SW SW Mode Note: For es to short -, Knob Position should be at - and vice versa. P_UPLEX R.K P_OUTER_SPEE R.K - - J V efault (-) J - - V efault (-) RMII MII/RMII/TMII (efault) onfiguration ONFIG ONFIG SW P_INLK JSQN P_REFLK_MOE SW P_IN JSQN P_IN SW P_IN JSQN P_IN SW P_INER JSQN P_INV SW P_OUT JSQN P_OUT_MOE SW P_OUT JSQN P_OUT_MOE SW P_RS JSQN P_M_UPLEX SW P_OL JSQN P_MIO_SPEE P_M_UPLEX/P_RS R.K P_MIO_SPEE/P_OL R.K Jumpers onfig(rmii) = - Short (- - open) onfig = - Short (- - open) (efault) LN U P_REFLK/P_MOE[P_OUTLK/P_REFLK/P_MOE] R P_OUT/REF_LK_MOE P_REFLK_MOE/P_INLK R P_IN/P_IN R P_REFLK/P_MOE[P_INLK] R P_IN P_IN/P_IN R P_IN[P_IN] P_IN R P_IN P_INV/P_INER P_IN[P_IN] P_IN P_INV P_INV[P_INER] P_INV P_OUT_MOE/P_OUT R R P_OUT_MOE P_OUT_MOE/P_OUT_MOE R P_OUT/P_MOE[P_OUT] P_OUT/P_MOE R P_OUT_MOE P_OUTV P_OUT/P_MOE[P_OUT/P_MOE] P_OUT/P_MOE P_OUTV J P_OUTV[RESERVE] P_OUTV P_M_UPLEX/P_RS P_UPLEX P_MIO_SPEE/P_OL P_UPLEX/P_M[P_RS] P_UPLEX P_OUTER_SPEE P_SPEE/P_MIO[P_OL] P_SPEE[P_OUTER/P_SPEE] V efault -Open J J V efault -Open ONFIG[ONFIG] ONFIG = RMII ONFIG = MII/RMII(efault) P_M P_MIO P_M P_MIO P_MIO_SPEE P_M_UPLEX P_IN P_IN P_INV P_REFLK_MOE P_OUTV P_OUT_MOE P_OUT_MOE P_INER P_INLK P_INV P_IN P_IN P_IN P_IN P_OL P_RS P_MIO P_M P_OUT P_OUT P_OUT_MOE P_OUT_MOE P_OUTV P_OUT/REF_LK_MOE P_OUTER_SPEE P_REFLK_MOE/P_INLK P_OUT_MOE/P_OUT P_OUT_MOE/P_OUT_MOE P_OUT_MOE P_OUT_MOE P_OUT/REF_LK_MOE Emulated Link Partner efault dvertised bility for Port Emulated Link Partner efault dvertised bility for Port J (P_UPLEX) - J (P_SPEE) uplex Strap_ Speed Strap_ VERTISE LINK PRTNER ILITY (its,,,) SE-T full-duplex () SE-X full-duplex () (efault) SE-T half-duplex () SE-X half-duplex () J (P_UPLEX) - J (P_SPEE) uplex Strap_ Speed Strap_ VERTISE LINK PRTNER ILITY (its,,,) SE-T full-duplex () SE-X full-duplex () SE-T half-duplex () SE-X half-duplex () hennai EV-LN LN(Part) oard Name: LN Name: EV-LN-REV- ate: Monday, June, Sheet of

10 V MII Male for External M oard MP - -- uf MII_R.uF MII Female for External PHY oard FEMLE MII ONN MP - - V uf.uf Port - RMII RX lock onfigurations SW M_RXLK M_TXLK efault Short - P_MIO P_M P_OUT P_OUT P_OUT_MOE P_OUT_MOE P_OUTV P_OUT/REF_LK_MOE P_OUTER_SPEE P_INER P_INLK P_INV P_IN P_IN P_IN P_IN P_OL P_RS PORT R R E E M_TXLK M_RXLK J V[] MIO M RX RX RX RX RX_V RX_LK RX_ER TX_ER TX_LK TX_EN TX TX TX TX OL RS V[] V[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] OMMON[] V[] P_MIO P_M P_IN P_IN P_IN P_IN P_INV P_INLK R E PHY_RXLK P_INER P_OUTER_SPEE R E TXER P_OUT/REF_LK_MOE R E PHY_TXLK P_OUTV P_OUT_MOE P_OUT_MOE P_OUT P_OUT P_OL P_RS hassis hassis J Settings SW (-) efault SW (-) SW (-) efault SW (-) JSQN SW PHY_RXLK PHY_TXLK efault (-) JSQN escription TX lock used as a Reference lock RX lock used as a Reference lock Reference clock used as a TX clock Reference clock used as a RX clock Mode RMII M RMII M RMII PHY RMII PHY Note:. For es to short -, Knob Position should be at - and vice versa.. External PHY considered LN PORT P_MIO_SPEE P_M_UPLEX P_OUT_MOE P_OUT_MOE P_OUTV P_REFLK_MOE P_INV P_IN P_IN P_INV For RMII R P_RS P_RS V E M_TXLK M_RXLK MII Male for External M oard MP - -- uf MII_R.uF J V[] V[] MIO OMMON[] M OMMON[] RX OMMON[] RX OMMON[] RX OMMON[] RX OMMON[] RX_V OMMON[] RX_LK OMMON[] RX_ER OMMON[] TX_ER OMMON[] TX_LK OMMON[] TX_EN OMMON[] TX OMMON[] TX OMMON[] TX OMMON[] TX OMMON[] OL OMMON[] RS OMMON[] V[] V[] P_REFLK_MOE MII Female for External PHY oard FEMLE MII ONN MP - - P_MIO_SPEE P_M_UPLEX P_IN P_IN P_INV R E PHY_RXLK P_OUTV P_OUT_MOE P_OUT_MOE P_RS PHY_TXLK hassis hassis J V uf.uf Port - RMII RX lock onfigurations Settings SW (-) efault SW (-) SW (-) efault SW (-) SW M_RXLK M_TXLK efault Short - JSQN SW PHY_RXLK PHY_TXLK efault (-) JSQN escription TX lock used as a Reference lock RX lock used as a Reference lock Reference clock used as a TX clock Reference clock used as a RX clock Mode RMII M RMII M RMII PHY RMII PHY Note:. For es to short -, Knob Position should be at - and vice versa.. External PHY considered LN J = efault open Short for RMII mode J P_INV P_RS Short option for RXV & RS for RMII mode TP Pullup for MIO(common for all PHY) signal TP P_MIO_SPEE P_M_UPLEX.K R K R V TP TP Pullup for MIO(common for all PHY) signal J = efault open P_MIO.K R J P_M K R V V V R K R K P_OUTV P_OUTV R.K TXER hennai EV-LN MII Interface oard Name: LN Name: EV-LN-REV- ate: Monday, June, Sheet of