X1 Initial Draft 02/29/12. Release for Production 03/22/12. U502 section updated J11 replaced by AX1. U11 - Y5 to Y8 made NC 06/05/12

Transcription

1 TLE OF ONTENTS Notes & lock iagram PKLNVLK (LQFP) PKLNVLK- SOKET PWR PERIPHERLS TWRPI MOULES ELEVTOR ONNETOR Revisions Rev ESRIPTION PPROVE TE X Initial raft /9/ X Pins reassignment, nd TWRPI GP removed // X X. khz oscillator added for K, pin reassignment for TWR PI's, & Elevator. dding a x HR for SW/ JTG on K User LEs resistors changed to ohms. ohms resistors were populated on Primary Elev :,,,,,. PT9 & PT connected to & pins on Primary Elev with ohm resistors // // X Replacing the x HRs on User LE's and infrared interface with a ip Switch. Replacing TVS diodes to improve the differential nets routing // Release for Production // X U section updated J replaced by - U replaced with PKLZVLK(TMP-WF-) // lberto arrillo/ // U replaced with Sub assembly - U K power supply and it s pull up, JTG supply changed to VOUT_K from U VT changed to VOUT_K from For URT signals a buffer added (U) For the signals between K to K, bi directional level translator(u- -9) added. OM optimisation done. NSP foot print used for U and U unused pins tied to GN Release Eduardo and listair's f/b implemented: * U - removed * U- Signals swapped betn and Y * U -XTl and EXTL pins made N * U - Reset is connected to VOUT_K // // // // U - Y to Y made N // J,J replaced by -9- J - efault Jumper option added // Release // lberto arrillo/ Production Release // lberto arrillo/ Microcontroller Solutions Group William annon rive West ustin, TX -9 This document contains information proprietary to Freescale Semiconductor and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale Semiconductor. IP lassification: FP: _ PUI: _ esigner: rawing Title: <esigner> XTWR-KLN rawn by: K.S helvi TLE OF ONTENTS pproved: Size ocument Number Rev lberto arrillo SH- PF: SPF- Friday, ugust, ate: Sheet of 9

2 . Unless Otherwise Specified: ll resistors are in ohms ll capacitors are in uf ll voltages are. Interrupted lines coded with the same letter or letter combinations are electrically connected.. evice type number is for reference only. The number varies with the manufacturer.. Special signal usage: _ enotes - ctive-low Signal <> or [] enotes - Vectored Signals Power & Ground Nets NET VOLTGE ESRIPTION PV_US V Primary input power. Filtered from US connector. Input to US power switch. PV_TRG_US V Output of US power switch controlled by the VTRG_EN signal from the JM MU. Provides input to regulator. PV_REG.V Output of regulator U or from the Elevator connector PV.V Output of regulator U.v or.v MU & Interface circuit input power V.V V power for MU and analog circuits. Filtered from MU_PWR.. Interpret diagram in accordance with merican National Standards Institute specifications, current revision, with the exception of logic block symbology. VREFH.V Upper reference voltage for on the MU. Filtered from V. V Lower reference voltage for on the MU. Filtered from VSS. VSS V VSS power for MU and analog circuits. Filtered from GN. GN V igital Ground. IP lassification: FP: PUI: rawing Title: XTWR-KLN NOTES Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9

3 G K - LQFP MU_PWR V VREFH V V V V VREFH 9 VSS VSS U NP R9 R.K.K {,9} PTE/I_SL {,,9} PTE/I_S {,9} PTE/_OUT/_SE {,,9} PTE/FTM_H {,9} PTE/URT_TX/RT_LKOUT/MP_OUT {,,9} PTE/SPI_MOSI {,,9} PTE/SPI_SK {,,9} PTE/SPI_MISO {,,9} PTE/SPI_PS_ {,,9} PTE/ GPIO {,,,9} PTE/_P/_SE {,,,9} PTE/_M/_SE {,,9} PTE/_P/_SE/URT_TX {,,9} PTE/_M/_SE/URT_RX PV_K_US_L J PTE/URT_TX/RT_LKOUT/MP_OUT/I_S PTE/SPI_MOSI/URT_RX/SPI_MISO/I_SL PTE/SPI_SK PTE/SPI_MISO/SPI_MOSI PTE/SPI_PS PTE PTE/_P/_SE/FTM_H/URT_TX PTE/_M/_SE/FTM_H/URT_RX PTE/_P/_SE/FTM_H/URT_TX PTE/_M/_SE/FTM_H/URT_RX PTE/FTM_H/I_SL PTE/FTM_H/I_S PTE/_OUT/_SE/MP_IN/FTM_H/FTM_LKIN PTE/FTM_H PTE9/MP_IN/_SE/FTM_H/FTM_LKIN PT/TSI_H/FTM_H/SW_LK PT/TSI_H/URT_RX/FTM_H PT/TSI_H/URT_TX/FTM_H PT/TSI_H/I_SL/FTM_H/SW_IO 9 PT/TSI_H/I_S/FTM_H/NMI PT/US_LKIN/FTM_H PT/FTM_H PT/FTM_H PT/SPI_PS/URT_TX PT/SPI_SK/URT_RX PT/SPI_MOSI/SPI_MISO PT/SPI_MISO/SPI_MOSI PT/EXTL/URT_RX/FTM_LKIN PT9/XTL/URT_TX/FTM_LKIN/LPTMR_LT PT/RESET PTE9/_SE {,} SW_LK_TGTMU {,,} PT/TSI_H/URT_RX {,,,9} PT/TSI_H/URT_TX {,,,9} SW_IO_TGTMU {,,,} PT {,} PT/FTM_H {,,9} PT/FTM_H {,9} PT/FTM_H {,9} URT_TX_TGTMU {,,9} URT_RX_TGTMU {,,9} PT {,} PT {,} EXTL_K_LK_MHZ {,} XTL_K_LK_MHZ {,} RST_TGTMU_ {,,9} HR X TH MU_PWR J TP.UF HR X TH PV_VREGIN_K VOUT_V K_US_N K_US_P.UF PF PF VREGIN VOUT 9 US_M US_P PT/LLWU_P/_SE/TSI_H/I_SL/FTM_H PT/_SE9/TSI_H/I_S/FTM_H PT/_SE/TSI_H/I_SL/FTM_H PT/_SE/TSI_H/I_S/FTM_H PT/EXTRG_IN PT9 9 PT/SPI_PS PT/SPI_SK PT/TSI_H9/SPI_MOSI/URT_RX/FTM_LKIN/SPI_MISO PT/TSI_H/SPI_MISO/URT_TX/FTM_LKIN/SPI_MOSI PT/TSI_H/FTM_H PT9/TSI_H/FTM_H PT/_SE/TSI_H {,,9} PT/_SE9/TSI_H {,,9} PT/_SE/TSI_H {,,9} PT/_SE/TSI_H {,,9} PT/EXTRG_IN {,} PT9 {,,,9} PT/SPI_PS {,,,9} PT/SPI_SK {,,9} PT/TSI_H9/URT_RX {,,} PT/TSI_H {,,} PT/TSI_H {,} PT9/TSI_H {,} K JTG / SW ONNETOR J SW_IO_TGTMU SW_LK_TGTMU.UF 9 RST_TGTMU_ GN HR X PT/_SE/TSI_H/EXTRG_IN/MP_OUT PT/LLWU_P/RT_LKIN/_SE/TSI_H/I_SL/FTM_H PT/_SE/TSI_H/I_S/FTM_H PT/LLWU_P/URT_RX/FTM_H/LKOUT PT/LLWU_P/SPI_PS/URT_TX/FTM_H PT/LLWU_P9/SPI_SK/LPTMR_LT/MP_OUT PT/LLWU_P/MP_IN/SPI_MOSI/EXTRG_IN/SPI_MISO PT/MP_IN/SPI_MISO/SPI_MOSI pin ( PT) has no connexion PT/MP_IN/I_SL/FTM_H reference at the spreadsheet PT9/MP_IN/I_S/FTM_H PT/I_SL PT/I_S 9 PT/FTM_LKIN PT/FTM_LKIN PT PT R PT/_SE/TSI_H {,,9} PT/LLWU_P/RT_LKIN/_SE {} PT/_SE/TSI_H/I_S {,,9} PT/LLWU_P/URT_RX/FTM_H/LKOUT {,,9}.K PT/LLWU_P/URT_TX/FTM_H {,,9} PT/LLWU_P9/SPI_SK/MP_OUT {,,9} PT/LLWU_P/EXTRG_IN/SPI_MISO {,,9} PT/MP_IN {,9} PT/K_US_I {,9} PT9/MP_IN/I_S/FTM_H {,9} PT/FTM_LKIN {,,9} PT/FTM_LKIN {,} PT {,} PT {,} R.K PT/I_SL {,} PT/I_S {,} VSS VSS VSS PT/SPI_PS/FTM_H PT/_SE/SPI_SK/FTM_H PT/SPI_MOSI/URT_RX/FTM_H/SPI_MISO PT/SPI_MISO/URT_TX/FTM_H/SPI_MOSI PT/LLWU_P/SPI_PS/URT_RX/FTM_H PT/_SE/SPI_SK/URT_TX/FTM_H PT/LLWU_P/_SE/SPI_MOSI/URT_RX/SPI_MISO 9 PT/SPI_MISO/URT_TX/SPI_MOSI PT/SPI_PS/FTM_H {,9} PT/_SE/SPI_SK/FTM_H {,9} PT/SPI_MOSI/URT_RX/FTM_H/SPI_MISO {,9} PT/SPI_MISO/URT_TX/FTM_H/SPI_MOSI {,9} PT/LLWU_P/SPI_PS/URT_RX/FTM_H {,9} PT/_SE/SPI_SK/URT_TX/FTM_H {,,9} PT/LLWU_P/_SE/SPI_MOSI/URT_RX/SPI_MISO {,,9} PT/TWRPI_GPIO/_IRQ {,} 9 9 PKLZVLK K US Interface (Host, evice, OTG) efault: - (Enable US Power) efault: - (Enable US Flag) J PF EXTL_K_LK_MHZ {,} MIRO US V S S PT/SPI_SK K_US_EN J HR X TH L OHM PV_K_US R PV_US.K UF U EN FLG EN FLG IN OUT GN OUT MI-YM K_US_FLG_ PV_K_US_L TP NP UF HR X TH R.K R.K PTE/FTM_H PT 9 PF X.MHZ R.M NP EXTL_RES_K R XTL_K_LK_MHZ {,} R NP Y VIO V.UF GN PT/LLWU_P/RT_LKIN/_SE GN OUT.KHZ. khz Osc - K_US_N R K_US_N {} + K_US_P R K_US_P {} K_US_SHL I S S J U U U NP R NP R PT/K_US_I OHM L K_ELEV_US_N {9} K_ELEV_US_P {9} IP lassification: FP: PUI: rawing Title: XTWR-KLN PKLNVKL (LQFP) Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9

4 K - SU SSEMLY V MU_PWR VREFH V V V V VREFH 9 VSS VSS U {,9} PTE/URT_TX/RT_LKOUT/MP_OUT {,,9} PTE/SPI_MOSI {,,9} PTE/SPI_SK {,,9} PTE/SPI_MISO {,,9} PTE/SPI_PS_ {,,9} PTE/ GPIO {,,,9} PTE/_P/_SE {,,,9} PTE/_M/_SE {,,9} PTE/_P/_SE/URT_TX {,,9} PTE/_M/_SE/URT_RX {,9} PTE/I_SL {,,9} PTE/I_S {,9} PTE/_OUT/_SE {,,9} PTE/FTM_H PTE/URT_TX/RT_LKOUT/MP_OUT/I_S PTE/SPI_MOSI/URT_RX/SPI_MISO/I_SL PTE/SPI_SK PTE/SPI_MISO/SPI_MOSI PTE/SPI_PS PTE PTE/_P/_SE/FTM_H/URT_TX PTE/_M/_SE/FTM_H/URT_RX PTE/_P/_SE/FTM_H/URT_TX PTE/_M/_SE/FTM_H/URT_RX PTE/FTM_H/I_SL PTE/FTM_H/I_S PTE/_OUT/_SE/MP_IN/FTM_H/FTM_LKIN PTE/FTM_H PTE9/MP_IN/_SE/FTM_H/FTM_LKIN PT/TSI_H/FTM_H/SW_LK PT/TSI_H/URT_RX/FTM_H PT/TSI_H/URT_TX/FTM_H PT/TSI_H/I_SL/FTM_H/SW_IO 9 PT/TSI_H/I_S/FTM_H/NMI PT/US_LKIN/FTM_H PT/FTM_H PT/FTM_H PT/SPI_PS/URT_TX PT/SPI_SK/URT_RX PT/SPI_MOSI/SPI_MISO PT/SPI_MISO/SPI_MOSI PT/EXTL/URT_RX/FTM_LKIN PT9/XTL/URT_TX/FTM_LKIN/LPTMR_LT PT/RESET PTE9/_SE {,} SW_LK_TGTMU {,,} PT/TSI_H/URT_RX {,,,9} PT/TSI_H/URT_TX {,,,9} SW_IO_TGTMU {,,,} PT {,} PT/FTM_H {,,9} PT/FTM_H {,9} PT/FTM_H {,9} URT_TX_TGTMU {,,9} URT_RX_TGTMU {,,9} PT {,} PT {,} EXTL_K_LK_MHZ {} XTL_K_LK_MHZ {} RST_TGTMU_ {,,9} {} K_US_N {} K_US_P VOUT_V PV_VREGIN_K 9 VREGIN VOUT US_M US_P PT/LLWU_P/_SE/TSI_H/I_SL/FTM_H PT/_SE9/TSI_H/I_S/FTM_H PT/_SE/TSI_H/I_SL/FTM_H PT/_SE/TSI_H/I_S/FTM_H PT/EXTRG_IN PT9 9 PT/SPI_PS PT/SPI_SK PT/TSI_H9/SPI_MOSI/URT_RX/FTM_LKIN/SPI_MISO PT/TSI_H/SPI_MISO/URT_TX/FTM_LKIN/SPI_MOSI PT/TSI_H/FTM_H PT9/TSI_H/FTM_H PT/_SE/TSI_H {,,9} PT/_SE9/TSI_H {,,9} PT/_SE/TSI_H {,,9} PT/_SE/TSI_H {,,9} PT/EXTRG_IN {,} PT9 {,,,9} PT/SPI_PS {,,,9} PT/SPI_SK {,,9} PT/TSI_H9/URT_RX {,,} PT/TSI_H {,,} PT/TSI_H {,} PT9/TSI_H {,} PT/_SE/TSI_H/EXTRG_IN/MP_OUT PT/LLWU_P/RT_LKIN/_SE/TSI_H/I_SL/FTM_H PT/_SE/TSI_H/I_S/FTM_H PT/LLWU_P/URT_RX/FTM_H/LKOUT PT/LLWU_P/SPI_PS/URT_TX/FTM_H PT/LLWU_P9/SPI_SK/LPTMR_LT/MP_OUT PT/LLWU_P/MP_IN/SPI_MOSI/EXTRG_IN/SPI_MISO PT/MP_IN/SPI_MISO/SPI_MOSI PT/MP_IN/I_SL/FTM_H PT9/MP_IN/I_S/FTM_H PT/I_SL PT/I_S 9 PT/FTM_LKIN PT/FTM_LKIN PT/_SE/TSI_H {,,9} PT/LLWU_P/RT_LKIN/_SE {} PT/_SE/TSI_H/I_S {,,9} PT/LLWU_P/URT_RX/FTM_H/LKOUT {,,9} PT/LLWU_P/URT_TX/FTM_H {,,9} PT/LLWU_P9/SPI_SK/MP_OUT {,,9} PT/LLWU_P/EXTRG_IN/SPI_MISO {,,9} PT/MP_IN {,9} PT/K_US_I {,9} PT9/MP_IN/I_S/FTM_H {,9} PT/I_SL {,} PT/I_S {,} PT/FTM_LKIN {,,9} PT/FTM_LKIN {,} PT PT PT {,} PT {,} VSS VSS VSS PT/SPI_PS/FTM_H PT/_SE/SPI_SK/FTM_H PT/SPI_MOSI/URT_RX/FTM_H/SPI_MISO PT/SPI_MISO/URT_TX/FTM_H/SPI_MOSI PT/LLWU_P/SPI_PS/URT_RX/FTM_H PT/_SE/SPI_SK/URT_TX/FTM_H PT/LLWU_P/_SE/SPI_MOSI/URT_RX/SPI_MISO 9 PT/SPI_MISO/URT_TX/SPI_MOSI PT/SPI_PS/FTM_H {,9} PT/_SE/SPI_SK/FTM_H {,9} PT/SPI_MOSI/URT_RX/FTM_H/SPI_MISO {,9} PT/SPI_MISO/URT_TX/FTM_H/SPI_MOSI {,9} PT/LLWU_P/SPI_PS/URT_RX/FTM_H {,9} PT/_SE/SPI_SK/URT_TX/FTM_H {,,9} PT/LLWU_P/_SE/SPI_MOSI/URT_RX/SPI_MISO {,,9} PT/TWRPI_GPIO/_IRQ {,} 9 9 PKLZVLK + SKT_QFP IP lassification: FP: PUI: rawing Title: XTWR-KLN PKLNVKL SU SSEMLY Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9

5 OR POWER SELETOR (Shunting -: =.V) (Shunting - : =.V) efault shunt - PV_TRG_US TP NP PV_REG J TP NP {9} VUS_ELEV HR TH X J VREG IN SELETOR VREG_INPUT MI9-.WS U UF T VIN OUTPUT GN U T IN OUT UF GN MI9-. PV 9 UF HR_X UF.UF R PU_PO_LE YEL/GRN POWER ON PWR_MU J efault: - V (Enable V) TP9 TP MU_PWR L NP L L OHM@MHZ MU_PWR_J V_HR TP VREFH HR X TH OHM@MHZ.UF.UF.UF.UF PF.UF J9 HR X TH OHM@MHZ L.UF.UF OHM@MHZ L.UF.UF efault shunt - OHM@MHZ VSS GN LOOP TEST PS GN LOOP TEST LOOPS TP TP TP TP TP TP TP TP IP lassification: FP: PUI: rawing Title: XTWR-KLN POWER SETION Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9

6 {,} PT LES LE GREEN R LE PUSH UTTON {,} PT/EXTRG_IN R LE efault: all Off LE RE IRJ SW PTE/_P/_SE/URT_TX {,,9} PTE/_M/_SE/URT_RX {,,9} SW P switch PT {,} SW IP- SW PT/LLWU_P/URT_RX/FTM_H/LKOUT {,,,9} INFRRE R9.K IR_SEN R MP_IN P switch IR-/TR R IRR Q PT-/TR.K.UF Intensity will be different between =.V and.v. POTENTIOMETER {,} PT/I_SL ELEROMETER efault: - (Enable LK) J HR X TH _SLK.UF R NP PV_REG R V_OPT.UF.uF R K.UF POT_K J HR X TH PTE9/_SE {,} efault: - (Enable POTENTIOMETER) {,} PT/I_S J HR X TH _S U9 SL S VIO V INT PT/LLWU_P9/SPI_SK/MP_OUT {,,9} efault: - (Enable T) R.KS_ R NP.K YP_ S YP GN GN GN INT INT N N N N N 9 INT J HR X TH J HR X TH efault: No Shunt - : Enable ELEROMETER PT/LLWU_P/EXTRG_IN/SPI_MISO {,,,9} efault: No Shunt - : Enable ELEROMETER 9.UF MMQ TOUH ELETROES WITH LEs {,,} PT/TSI_H {,,} PT/TSI_H9/URT_RX {,,,9} PTE/_P/_SE {,,,9} PT/TSI_H/URT_RX {,,,} SW_IO_TGTMU {,,,9} PT9 {,,9} PT/SPI_SK {,,9} PT/_SE/TSI_H/I_S {,,9} PT/LLWU_P/URT_TX/FTM_H GPIO HR J 9 9 PTE/_M/_SE {,,,9} PTE/FTM_H {,,9} PT/TSI_H/URT_TX {,,,9} PT/SPI_PS {,,,9} PT/LLWU_P/URT_RX/FTM_H/LKOUT {,,,9} PT/LLWU_P/EXTRG_IN/SPI_MISO {,,,9} R HR X TH J9 ELE LEOR R.K LE_OR + ELETROE R ELE R.K LEYR LE_YEL + ELETROE {,,9} PT/FTM_LKIN {,} PT HR_X PT/FTM_LKIN {,} PT {,} {,,9} PT/FTM_H {,} PT J HR X TH LE_OR LE_YEL efault: - (Enable LE) IP lassification: FP: PUI: rawing Title: XTWR-KLN PERIPHERLS Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9

7 GENERL PURPOSE TWRPI Note: The TWRPI connectors are powered by which may be.v or.v. Not all TWRPI boards will work at.v. heck that the TWRPI board will work at.v before using it when this board is set for.v. J {,,9} PT/_SE/TSI_H {,,9} PT/_SE/TSI_H {,,9} PT/_SE9/TSI_H {,,9} PT/_SE/SPI_SK/URT_TX/FTM_H TWRPI- R.K TWRPI-I PV_TRG_US J 9 9 V TWRPI- TWRPI- TWRPI-I RESET_ R9.K {,,9} PTE/SPI_MISO {,,9} PTE/SPI_PS_ {,} PT/TWRPI_GPIO/_IRQ {,,,9} PT/TSI_H/URT_RX {,,,9} PT9 I_SL SPI_MISO SPI_S_ TWRPI_GPIO/IRQ URT_RX TWRPI_GPIO URT_TS TWRPI_GPIO 9 9 ON_X ON X PLUG SHR SMT MIL TR H U I_S SPI_MOSI SPI_LK TWRPI_GPIO TWRPI_GPIO URT_TX URT_RTS PTE/I_S {,,9} PTE/SPI_MOSI {,,9} PTE/SPI_SK {,,9} PTE/ GPIO {,,9} PT/SPI_PS {,,,9} PT/TSI_H/URT_TX {,,,,9} VSS ON_X VSS ON X PLUG SHR SMT MIL TR H U {,,,9} RST_TGTMU_ {,,9} PT/LLWU_P/_SE/SPI_MOSI/URT_RX/SPI_MISO TOUH P TWRPI PT/_SE9/TSI_H {,,} PT/TSI_H9/URT_RX {,,} PT/TSI_H {,} PT/TSI_H {,,9} PT/_SE/TSI_H {,,9} PT/_SE/TSI_H {,,,} SW_IO_TGTMU {,,,9} PTE/_P/_SE R.K PV_TRG_US J V Touch TWRPI Touch TWRPI Touch TWRPI Touch TWRPI Touch TWRPI 9 Touch TWRPI Touch TWRPI Touch TWRPI Touch TWRPI 9 Touch TWRPI Touch TWRPI Touch TWRPI TOUH TWRPI-I TOUH TWRPI-I 9 R.K PT9/TSI_H {,} PT/_SE/TSI_H PT/_SE/TSI_H SW_LK_TGTMU {,,} PT/TSI_H/URT_TX {,,,,9} PTE/_M/_SE {,,,9} RST_TGTMU_ {,,,9} ON_X VSS IP lassification: FP: PUI: rawing Title: XTWR-KLN TWRPI MOULES Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9

8 G L OHM TP PV_US UF VOUT_K.UF.UF VOUT_K U V V VSS K - QFN JTG_TLK/SW_LK/EZP_LK/TSI_H/PT/URT_TS/URT_OL/FTM_H JTG_TI/EZP_I/TSI_H/PT/URT_RX/FTM_H JTG_TO/TRE_SWO/EZP_O/TSI_H/PT/URT_TX/FTM_H JTG_TMS/SW_IO/TSI_H/PT/URT_RTS/FTM_H NMI/EZP_S/TSI_H/PT/FTM_H K US-SERIL INTERFE JTG ONNETOR JTG_TLK_SI JTG_TI_SI JTG_TO_SI JTG_TMS_SI SW_EN_SI_ VOUT_K.UF GN VOUT_K R.K J 9 HR X JTG_TMS_SI JTG_TLK_SI JTG_TO_SI JTG_TI_SI K_RESET_ RESET_ VOUT_K R YEL/GRN VOUT_K R K NP.UF RESET SW P switch MU_PWR ONN US MINI- x US-SHL J S I + - VUS S US_VUS U U UF U US_N US_P.UF R R PV_US.UF US_K_N US_K_P PF.UF VOUT_K TP NP PF PV_US 9 VT VREGIN VOUT US_M US_P EXTL XTL EXTL/PT/FTM_FLT/FTM_LKIN XTL/PT9/FTM_FLT/FTM_LKIN/LPTMR_LT _SE9/TSI_H/PT/I_S/FTM_H/FTM_Q_PH _SE/TSI_H/PT/I_SL/FTM_H/FTM_Q_PH EXTL_LK_MHZ XTL_LK_MHZ SI_SW_OE_ RESET_ R9 R.M.MHZ EXTL_RES X VOUT_K R9.K VOUT_K V V U TXS OE GN VOUT_K J HR X TH R.K NP RST_TGTMU_,,9 S S R K 9 RESET V V U OE L OHM R K K_RESET_ 9.UF VSS _SE/TSI_H/PT/SPI_PS/URT_RTS/FTM_H/IS_TX _SE/MP_IN/TSI_H/PT/SPI_PS/URT_TS/FTM_H/IS_TX_FS MP_IN/PT/SPI_PS/URT_RX/FTM_H/LKOUT/IS_TX_LK PT/SPI_PS/URT_TX/FTM_H/MP_OUT PT/SPI_SK/LPTMR_LT/IS_RX/MP_OUT MP_IN/PT/SPI_SOUT/P_EXTRG/IS_RX_LK/IS_MLK MP_IN/PT/SPI_SIN/US_SOF_OUT/IS_RX_FS URT_RX_K URT_TX_K SI_SPI_SK SI_SPI_SOUT SI_SPI_SIN SI_SW_OE_ SI_SPI_SOUT SW_EN_SI_ 9 SW_IO_UF VOUT_K U V OE Y OE Y.UF SI_SPI_SIN TX GN SW_IO_TGTMU {,,,} EP VOUT_K R SW_EN_SI_ SI_SPI_SK OE Y SW_LK_UF LE GREEN VOUT_K R OE GN Y K-K - VXLTR PT/SPI_PS/URT_RTS/FTM_H/EWM_IN 9 _SE/PT/SPI_PS/URT_TS/URT_OL/FTM_H/EWM_OUT _SEb/PT/SPI_PS/URT_RX/FTM_H/FTM_FLT PT/MT_IRO/URT_TX/FTM_H/FTM_FLT LE_SI POWER_EN VTRG_FULT_ LV PKXVFM POWER_EN R.K NP R K PWR switch to enable v from US connector.k R VTRG_EN PV_US.UF NP PF U VIN SLEW ENLE TIVE HIGH VOUT FULT GN MI-.YM TO USE TXS! ERIVE in TSE PV_TRG_US TP NP MSSPL VOUT_K R.K PV_ELEV UF VTRG_FULT_ SW_LK_UF URT_TX_K URT_RX_K VOUT_K U V V IR GN SNLVT VOUT_K U IR V V GN SNLVT SW_LK_TGTMU {,,} URT_TX_K_EN URT_RX_K_EN HR TH X J URT_TX_ELEV_EN URT_TX_TGTMU {,,9} URT_RX_K_EN PV_REG U IR V V {,,9} URT_TX_ELEV URT_TX_ELEV_EN GN SNLVT HR TH X J URT_RX_ELEV_EN URT_RX_TGTMU {,,9} URT_TX_K_EN PV_REG U IR V V {,,9} URT_RX_ELEV_EN URT_RX_ELEV GN SNLVT {9} ELE_PS_SENSE R K Q MMTL IP lassification: FP: PUI: rawing Title: XTWR-KLN SW K Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9

9 ELEVTOR ONNETOR PV_ELEV PV_ELEV {,9} ELE_PS_SENSE {,,} PTE/SPI_SK {,,} PTE/SPI_PS_ {,,,9} PTE/SPI_MOSI {,,} PTE/SPI_MISO {,} PT/MP_IN {,} PTE/URT_TX/RT_LKOUT/MP_OUT {,,} PT/SPI_SK {,,} PT/_SE/TSI_H {,,} PT/_SE9/TSI_H {,,} PT/_SE/TSI_H {,,} PT/_SE/TSI_H {,,} PT/FTM_H {,,} PTE/ GPIO {,,} PT/LLWU_P/_SE/SPI_MOSI/URT_RX/SPI_MISO {,,} PT/_SE/SPI_SK/URT_TX/FTM_H {,,9} PT/LLWU_P/SPI_PS/URT_RX/FTM_H {,} PT/SPI_MISO/URT_TX/FTM_H/SPI_MOSI {,} PT/SPI_MOSI/URT_RX/FTM_H/SPI_MISO {,} PT/SPI_PS/FTM_H {,,9} PT/LLWU_P/SPI_PS/URT_RX/FTM_H {,} PT/_SE/SPI_SK/FTM_H {,,} PT/FTM_LKIN {,,} PT/LLWU_P/EXTRG_IN/SPI_MISO {,,} PT/LLWU_P9/SPI_SK/MP_OUT PV_ELEV PV_ELEV PV_REG PV_REG J {,9} ELE_PS_SENSE V_ V_ GN_ GN_9.V_.V_ ELE_PS_SENSE_.V_ GN_ GN_ R SH_LK/SPI_LK GN_ GN_ I_SL_ELEV R PT/_SE/TSI_H {,,} SH_LK/SPI_LK I_SL I_S_ELEV PTE/I_S {,,} R SH_/SPI_S_ 9 SH_/SPI_S I_S R PT9/ URT_TS R PT9/MP_IN/I_S/FTM_H {,} SH_M/SPI_MOSI SH_/SPI_S GPIO9/URT_TS 9 R PT_ELEV_GPIO R PT/SPI_PS {,,,} R9 SH_/SPI_MISO SH_M/SPI_MOSI GPIO/SH_ PT9_ELEV_GPIO R SH_/SPI_MISO GPIO/S_WP_ET PT9 {,,,} ETH_OL_ ETH_RS ETH_RXER_ ETH_M_ ETH_TXLK_ ETH_MIO_ ETH_TXEN_ ETH_RXLK_ ETH_TXER ETH_RXV_ ETH_TX ETH_RX 9 ETH_TX ETH_RX 9 ETH_TX_ ETH_RX_ R PT_ELEV_GPIO ETH_TX_ ETH_RX_ R GPIO/SH_ GPIO/URT_RTS IS_MLK PT_ELEV_GPIO GPIO/SH_ IS_OUT_SK R GPIO IS_OUT_WS LKIN IS_IN LKOUT IS_OUT R PT_ELEV_N GN_ GN_ N R PTE/_P/_SE {,,,} R PT_ELEV_N N N N R PTE/_M/_SE {,,,} R PT_ELEV_N 9 N N 9 N R9 PTE/_P/_SE/URT_TX {,,} R PT_ELEV_N N N N R N PTE/_M/_SE/URT_RX {,,} N GN_ GN OUT_ELEV R PTE/_OUT/_SE {,} TMR R PT/FTM_H {,} R NP TMR TMR TMR R PT/FTM_H {,} R PTE_ELEV_GPIO TMR TMR GPIO_ELEV R GPIO PTE/FTM_H {,,} GPIO.V_.V_ PT_ELEV_PWM R PT/LLWU_P/URT_TX/FTM_H {,,} R PT_ELEV_PWM PWM PWM PT_ELEV_PWM R PT/LLWU_P/URT_RX/FTM_H/LKOUT {,,,9} R PT_ELEV_PWM 9 PWM PWM 9 PT_ELEV_PWM R PT/_SE/TSI_H/I_S {,,} R9 PT_ELEV_PWM PWM PWM PTE_ELEV_PWM R PWM PTE/I_SL {,} PWM PT_ELEV_URT_RX R N_RX PT/TSI_H/URT_RX {,,,} URT_RX PT_ELEV_URT_TX N_TX PT/TSI_H/URT_TX {,,,} URT_TX R PT_ELEV_URT_RX URT_RX_ELEV {,,} PT_ELEV_SPI_MISO WIRE URT_RX R9 R PT_ELEV_URT_TX URT_TX_ELEV {,,} PT_ELEV_SPI_MOSI SPI_MISO/IO URT_TX R R VSS_ELEV R9 PT_ELEV_SPIO_S SPI_MOSI/IO VSS R V_ELEV R PT_ELEV_SPI_S SPI_S V R VREFH V R PT_ELEV_SPI_LK SPI_S N_RX R 9 SPI_LK N_TX R 9 GN_ GN_ I_SL GPIO VSS R PT_ELEV_GPIO I_S GPIO GPIO/SPI_HOL/IO GPIO/SPI_WP/IO RSRV_ GPIO RSRV_ K_ELEV_US_N {} US_M IRQ_H K_ELEV_US_P {} US_P IRQ_G PT/K_US_I {,} US_I R NP IRQ_F VUS_ELEV {} US_VUS R 9 IRQ_E IS_IN_SK IRQ_ IS_IN_WS 9 R PT_ELEV_IRQ_ IRQ_ IS_IN R PT_ELEV_IRQ_ IRQ_ IS_OUT RST_IN_ IRQ_ RST_TGTMU_ {,,} RSTIN R NP RST_OUT_ R EI_LE/EI_S PTE/SPI_MOSI {,,,9} RSTOUT PT_ELEV_LKOUT R NP EI_S PT/LLWU_P/URT_RX/FTM_H/LKOUT {,,,9} LKOUT GN_ GN_ EI_ EI_ EI_ EI_ 9 EI_ EI_ 9 EI_ EI_ EI_9 EI_ EI_R/W EI_9 EI_OE EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ 9 EI_ EI_ 9 EI_ EI_ EI_ EI_ GN_ GN_.V_.V_ PV_REG J V_ V_ GN_ GN_.V_.V_ ELE_PS_SENSE_.V_ GN_ GN_ GN_9 GN_ SPI_LK I_SL 9 SPI_S I_S SPI_S GPIO SPI_MOSI ULPI_STOP SPI_MISO ULPI_LK ETH_OL_ GPIO ETH_RXER_ ETH_M_ ETH_TXLK_ ETH_MIO_ ETH_TXEN_ ETH_RXLK_ GPIO ETH_RXV_ GPIO9/SH_ GPIO/SH_ 9 GPIO/SH_ GPIO/SH_ ETH_TX_ ETH_RX_ ETH_TX_ ETH_RX_ ULPI_NEXT/US_HS_M ULPI_T/IS_MLK ULPI_IR/US_HS_P ULPI_T/IS_OUT_SK UPLI_T/US_HS_VUS ULPI_T/IS_OUT_WS ULPI_T/US_HS_I ULPI_T/IS_IN ULPI_T ULPI_T/IS_OUT GN_ GN_ L_HSYN/L_P N 9 L_VSYN/L_P N N N9 N N GN_ GN_9 L_LK/L_P GPIO9/URT_ TMR TMR9 TMR TMR GPIO GPIO/URT_.V_9.V_ PWM PWM 9 PWM PWM PWM PWM9 PWM PWM N_RX URT_RX/TSI N_TX URT_TX/TSI L_ONTRST URT_RTS/TSI L_OE/L_P URT_TS/TSI L_/L_P URT_RX/TSI L_/L_P URT_TX/TSI L_/L_P URT_RTS/N_RX 9 L_/L_P URT_TS/N_TX GN_ GN_ GPIO L_/L_P GPIO L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P IRQ_P/SPI_S L_9/L_P9 IRQ_O/SPI_S L_/L_P IRQ_N L_/L_P 9 IRQ_M IS_IN_SK IRQ_L IS_IN_WS IRQ_K IS_IN IRQ_J IS_OUT IRQ_I L_/L_P L_/L_P/S_RX_+ L_/L_P/S_GN L_9/L_P9/S_RX_- L_/L_P/S_GN GN_ GN_ EI_/L_P/S_GN EI_E /L_P/S_TX_+ EI_/L_P/S_GN EI_E /L_P9/S_TX_- 9 EI_/L_P/S_RX_+ EI_E /L_P/S_GN EI_/L_P/S_RX_- EI_E /L_P/S_GN EI_/L_P/S_GN EI_TSIZE/L_P/S_TX_+ EI_/L_P/S_GN EI_TSIZE/L_P/S_TX_- EI_/L_P/S_RX_+ EI_TS/L_P/S_GN EI_/L_P9/S_RX_- EI_TST/L_P/S_GN EI_/L_P/S_GN EI_T/L_P/S_TX_+ EI_9/L_P/S_GN EI_S/L_P/S_TX_- EI_/L_P/S_RX_+ EI_S/L_P/S_GN EI_/L_P/S_RX_- EI_S/L_P9/S_GN 9 L_/L_P/S_GN EI_S/L_P/S_TX_+ L_/L_P/S_REFLK+ GPIO/L_P/S_TX_- L_/L_P/S_REFLK- L_/L_P/S_GN GN_ GN_.V_.V_ PI EXPRESS TOWER SYSTEM SEONRY PV_REG PI EXPRESS TOWER SYSTEM PRIMRY PV_ELEV PV_REG +.UF +.UF IP lassification: FP: PUI: rawing Title: XTWR-KLN ELEVTORS Size ocument Number Rev SH- PF: SPF- Friday, ugust, ate: Sheet of 9 9