DEVKIT-MPC5748G. Table Of Contents: Caution:

Transcription

1 Table Of ontents: Power - Main input, V and.v regulator Power - MU Power Power - MU ecoupling Reset and JTG locks MU GPIO MU GPIO omms - N and LIN omms - OpenS omms - US Host Interface (device footprints only) omms - Ethernet (RMII Mode) omms - FlexRay User - Switches, LE's and Potentiometer User - GPIO onnectors aution: Sheet Sheet Sheet Sheet Sheet Sheet Sheet Sheet 9 Sheet Sheet Sheet Sheet Sheet Sheet These schematics are provided for reference purposes only. s such, NP does not make any warranty, implied or otherwise, as to the suitability of circuit design or component selection (type or value) used in these schematics for hardware design using the NP alypso family of Microprocessors. ustomers using any part of these schematics as a basis for hardware design, do so at their own risk and Freescale does not assume any liability for such a hardware design. User notes are given throughtout the schematics. Specific P LYOUT notes are detailed in ITLIS EVKIT-MPG Revision Information Rev ate esigner omments Sep atalin Neacsu Initial release Sep atalin Neacsu Further changes. ecreased component size where possible. 9 Sep atalin Neacsu hanged ethernet page. hanged caps around Q Rearranged GPIOs on page. dded more LEs on page ifferent test points used in design: TPVx - Through Hole Pad small TPHx - Through Hile Pad Large (for standard." header). Notes: lso used on IO Matrix (IOMx) - ll components and board processes are to be ROHS compliant - ll small capacitors are unless otherwise stated TP - Surface Mount Wire Loop - ll resistors are %.w unless otherwise stated. ll zero ohm links are - ll connectors and headers are denoted Px and are.mm pitch unless otherwise stated - ll jumpers are denoted Jx. Jumpers are mm pitch - Jumper default positions are shown in the schematics. For way jumpers, default is always posn -. Pin jumpers generally have the "source" on pin. - ll switches are denoted SWx - ll test points (SMT wire loop style) are denoted TPx - Test point Vias (just through hole pads) are denoted TPVx Signals (ports) have not been routed via busses as this makes it harder to determine where each signal goes. Oct atalin Neacsu hanged U, US connectors, ETH onnector, OM optimization Oct atalin Neacsu hanged PN of U and Oct atalin Neacsu Small visual updates Oct atalin Neacsu dd separation resistors for US interface, U Oct atalin Neacsu hanged V converter, minor OM optimization 9 Oct atalin Neacsu hanged V converter, minor OM optimization, better cost Oct atalin Neacsu Updated IO connections per Jesus Sanchez's request dded TP on page per Ruiz Ricardo's request Oct atalin Neacsu hanged Power Supply page dded one user led Oct atalin Neacsu hanged PN for P and P Oct atalin Neacsu hanged Power Supply page to allow supply selection Nov atalin Neacsu OM Optimization Nov atalin Neacsu PN change for L ec atalin Neacsu dded Open S block Implemented other feedback Jan atalin Neacsu Implemented OpenS feedback Jan atalin Neacsu hanged some Is to their NP equivalent 9 Jan atalin Neacsu P, Y add connections. JTG connector pins Jan atalin Neacsu Protoype Release Jun Jun Qiao Update with Flexray, OpenS, Ethernet, LE, uttons, GPIO. Jun Jun Qiao Update with OpenS, GPIO connectors. Jun Jun Qiao Pilot Release esigner: Neacsu rawn Neacsu pproved: Pesses Philip IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG Index and Title Page Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

2 Power Input and Voltage Regulators V Power Supply Input P ON PWR SH SH + - uf V V_IN PMEGER V Switching Regulator Input Voltage V, Output V at m VIN S U R.K % F OUT P9-SG- R.9K % L uh SRUP V_SW uf V V_SR TP SILK = V_SR R S GREEN SILK = V_OK oard supply selection Select between US and external V - -> external V - -> US/URT connector V_SW Power ontrol V_SR J HR_ V_TGT_OUT Jumpers can be fitted to facilitate power measurements V_SR LYOUT NOTE: Graphical silk: Layout note: follow I datasheet recommandations for P layout and thermal dissipation R MU_V [] V_SR R MU_V [].V Switching Regulator Input Voltage V, Output.V at m V_SR V_SR PER_HV R.K % R.9K % V_SR V_SR TP SILK = V_SR R R uf V V_SR PMEGER VIN S U9 F OUT P9-SG- L.uH SRUP uf V R S GREEN SILK = V_OK Test and reference points TP SILK = TP9 SILK = Layout note: follow I datasheet recommandations for P layout and thermal dissipation Test Points, Top Side esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG Power Input, V,.V Reg Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

3 alypso MU Power onnections Power Supply ontraints: efault onfiguration: - If V_HV_ is driven from.v, V_HV_FL must also be supplied from.v - If V_HV_ is driven from V, the V_HV_FL pin must be disconnected from.v - on't attempt to over drive an analogue pad to V when the digital V_HV_x supply is set to.v. This will trigger the ES protection on that pad. For example if V_HV_ is set to.v and the analogue supplies are set to V, you cannot drive V into a pad in the V_HV_ domain - LL MU supply voltages are set to.v (,, V_HV_, V_HV_, V_HV_, Vallast) - V_HV_FL = External.V supplied (jumper fitted) The analogue pins can only be driven to the same voltage as the V_HV_x domain they are situated in (ie max.v) so makes sense for the analogue supply and reference to be.v [] MU_V [] MU_V _P v v SILK = V R R SILK = V _P SILK = V R R SILK = V TPV _P R TPV REF_P SILK = V R R SILK = V TPH SILK = REF HV_P SILK = V R SILK = V TPV R HV_P TPV SILK = V R9 HVFL_P TPV SILK = V R R SILK = V _P R Q MJT pf.uf Individual MU supply control TPV SILK = _P LV_P LVE_P U 9 V_HV_ SILK = SILK = 99 V_HV_ nalogue 9 V_HV REF 9 SILK = HV alypso M QFP PKGE OF POWER PINS SILK = HVFL VR_TRL Flash.v ore & External allast VSS_HV_ VSS_LV_9 V_HV V_HV 9 V_HV V_HV V_HV V_LV_ V_LV_ V_LV_ V_LV_ V_HV_FL V_LP_E VSS_HV_ 9 9 VSS_HV_ VSS_HV_ VSS_HV_ VSS_HV_ VSS_HV_ VSS_HV_ VSS_HV_ E_P VSS_HV/VPP 9 R9 PPGSKMKU Notes on signal Grounds: - The scheme shown has the analogue and digital grounds connected to the same plane - This results in better performance than using an analogue grond plane with single entry point (or ferrite) to digital ground plane. TPH SILK = VSS_HV_VPP esigner: rawn IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG alypso MU Power pproved: Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

4 alypso MU ecoupling and bulk storage _P _P REF_P Flash HVFL_P.UF.UF.UF.UF.UF.uF Place small aps as close as possible to MU pins V_HV HV_P V_HV HV_P.uF.UF.UF.UF.UF.UF One.uF cap per V_HV_x pin. Place as close as possible to pin V_LV LV_P LP Internal Reg ap LVE_P.UF.UF.UF.UF.UF.UF.UF.UF V_LV (.V) ecoupling. Place one of the.uf caps close to each V_LV pin. Place the.uf caps on each side of the package such that there is no cap on the side with the ballast transistor (For regulator stability the total capacitance should be around.uf). esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG alypso MU ecoupling Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

5 Reset and External lock In Reset is in the V_HV domain. Reset Input / Output PER_HV.UF V_SR R PORST onnect an external LVI to pad when supplying external.v so that PORST is asserted until exterbal.v supply is at threshold and stable TPH SILK = PORSTx PER_HV R9 K PORSTx [] [] JTG-RSTx Reset from ebugger Reset Switch SW SKRPE SILK = RESET R K R K RST-SWITHx TPV.UF Note: S LE_YELLOW U V TRGET RESET LE SYSTEM-RSTx RST-INx R LVG STM (. to.v operation).uf Tri-State uffered RESET signal to reset the MU The Reset pad on alypso is in the V_HV_ domain which can be run from either.v or V (selected by the V_HV_ and PER_HV jumpers) To maintian brightness on the LE's irrespective of the voltage setting, the LE's are powered from constant.v, grounded via the reset line. U V MR RST VSS R9 K uffered RESET-out i irectional reset line to/from MU ctive reset drive (high / low) for any periperhals that need to be reset when MU is in reset V_SR U R S RE SILK = MU_RST MU-RSTx [,,,] RST-OUTx [] LVG JTG Standard -pin onnector PER_HV R.K R.K Layout Note: learly mark pin numbers,, and ONE onnector [] TI_HEER [,] P [] TLK_HEER [] JTG-RSTx [,,,] MU-RSTx TI TO TLK (buffered reset TO MU) (bidirectional MU reset) R R Optional onfig UG-RSTx (TI) (TO) (TLK) (EVTI) (RESET) (VREF) (RY) P 9 HR_ SILK = JTG Place One P next to each connector () () () (N/) (TMS) () JOMP R.K [] TMS_HEER TMS esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG Reset ircuitry & External lock In, JTG Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

6 locks Oscillators [] ETL PF [] TL R M Y.KHZ 9 PF S-.KHZ-T (Load apacitance.pf) [] MU-ETL [] MU-TL R M Y PF MHZ PF GPTV (Optimised for utomotive, pf Load capacitance) esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG locks Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

7 alypso GPIO of U [] P [] P [] P [] P [] P [] P [] P [] P [] P [] P9 [] P [] P [] P [] P [] P [] P (LE) (SW) (LE) (LE) (RMII_R) (RMII_R) (LE) (RMII_RER) 9 9 P/GPIO/EU /LKOUT/EU H/WKPU9/NR P/GPIO/EU G/WKPU/NR/NMI P/GPIO/EU G/EU /_M/WKPU P/GPIO/EU G/LINT/S_/MII_R_LK/EIRQ/_S P/GPIO/EU G/S_/EU /LINR/WKPU9/MP_ P/GPIO/EU G/LINT/E_OIS/ULPI_STP P/GPIO/EU G/S_/E_OIS/LINR/EIRQ/ULPI_IR P/GPIO/EU G/LINT/MII_R/EIRQ/_S P/GPIO/EU /EU H/MII_RMII_R/EIRQ/RSV/LINR/_S9 P9/GPIO9/EU_9_H/S_/MII_RMII_R/RSV/_S P/GPIO/EU H/S/LINT/MII_OL/SIN_/_S P/GPIO/EU H/SL/ULPI_FULT/MII_RMII_R_ER/EIRQ/LINR/_S P/GPIO/EU Y/S_/EU Y/EIRQ/SIN_/MP_ P/GPIO/SOUT_/EU_9_Y/EU Y/NT/MP_ P/GPIO/SLK_/S_/EU /EU /EIRQ/MP_ P/GPIO/S_/SLK_/EU G/EU Y/NR/WKPU/MP_ LINR/WKPU/NR/SL/EU /GPIO/PE S/NT/EU Y/GPIO/PE ULPI_LK/EIRQ/SIN_/S_T/FR T_EN/EU Y/GPIO/PE ULPI_NT/WKPU9/FR R/S_M/SOUT_/EU_9_Y/GPIO/PE EIRQ9/ULPI_/S_T/FR T/SLK_/EU Y/GPIO/PE WKPU/FR R/ULPI_/S_T/_M/S_/EU Y/GPIO9/PE EIRQ/S_M/_M/_M/S_/EU /GPIO/PE EIRQ/S_LK/_M/_M/S_/EU /GPIO/PE S/NT/EU /NT/GPIO/PE NR/NR/WKPU/SL/EU /GPIO/PE9 EIRQ/S/EU Y/S_/LINT/GPIO/PE WKPU/LINR/SL/LKOUT/S_/EU /GPIO/PE _S/EIRQ/SIN_/MII_RS/ULPI_FULT/EU_9_Y/GPIO/PE _/MII_R/EU Y/SOUT_/GPIO/PE EIRQ/ULPI_/EU Y/SLK_/GPIO/PE ULPI_/SLK_/EU /S_/GPIO9/PE (FR T_EN) (FR R) (SW) (US_) (US_) PE [] PE [] PE [] PE [] PE [] PE [] PE [] PE [] PE [] PE9 [] PE [] PE [] PE [] PE [] PE [] PE [] [9] P [9] P [9] P [9] P [,] P [] P [] P [] P [] TL [] ETL [] P [] P [] P [] P [] P [] P (N_T) (N_R) (LIN_T) (LIN_R) (_POT) P/GPIO/NT/EU Y/LINT/EU Y/MP_ P/GPIO/EU Y/EU Y/LINR/WKPU/MP_/NR P/GPIO/LINT/S/EU Y/S_T P/GPIO9/EU Y/SL/EU /WKPU/LINR P/GPI/_P P/GPI/_P P/GPI/_P P/GPI/_P P/GPI/_S/WKPU/OSK_TL P9/GPI/_S/WKPU/OSK_ETL P/GPIO/SOUT_/NT/MP_O/SI_SYN/EU_9_Y/_S/WKPU/NR P/GPIO/EU G/S_/_S P/GPIO/EU G/S_/O/_ P/GPIO9/EU G/S_/MLN/_ P/GPIO/EU G/S_/FR_G/MLSN/_ P/GPIO/EU G/S_/MLSIG/MLN/_ SI_MLK/MP_/_S/NT/SOUT_/S_/EU H/GPIO/PF SIN_/MP_/_S9/SI_LK/S_/S_/EU H/GPIO/PF MP_/_S/SI_/SLK_/S_/EU H/GPIO/PF MP_9/_S/SI_/S_/S_/EU H/GPIO/PF MP_/_S/SI_/SOUT_/S_/EU H/GPIO/PF SIN_/MP_/_S/SI_/S_/S_/EU /GPIO/PF MP_/_S/_S/EU Y/SI_SYN/SLK_/S_/EU /GPIO/PF SI_MLK/MP_/_S/S_/S_/SLK_/GPIO/PF MP_/EU Y/NT/S_/NT/GPIO/PF MP_/WKPU/NR/NR/EU Y/S_/EU H/GPIO9/PF9 MP_/EU_9_Y/EU H/LINT/S_/GPIO9/PF MP_9/WKPU/LINR/EU Y/EU H/S_/GPIO9/PF MP_/EU /LINT/EU Y/GPIO9/PF MP_/WKPU/LINR/EU /EU Y/GPIO9/PF _/MII_RMII_MIO/NT/EU Y/NT/GPIO9/PF _/EIRQ/NR/NR/MII_RMII_R_V/EU H/GPIO9/PF 9 9 (RMII_MIO) (MII_RS) PF [] PF [] PF [] PF [] PF [] PF [] PF [] PF [] PF [] PF9 [] PF [] PF [] PF [] PF [] PF [] PF [,] [] P [,] P [] P [] P [] P [] P [] P [] P [] P [] P9 [] P [] P [] P [] P [] P [] P (TI) (TO) (US_LK) (US_IR) (LE) (FR T) (RS_T) (RS_R) (FR_G) (FR_G) (FR_G) (FR_G) 9 9 P/GPIO/RSV/TI P/GPIO/TO/RSV P/GPIO/SLK_/NT/EU /SSM_G/EIRQ/ULPI_LK P/GPIO/S_/_M/EU /SSM_G/NR/NR/EIRQ/ULPI_IR P/GPIO/EU Y/FR T_EN/S_T/ULPI_/SSM_G/SIN_/NR/EIRQ P/GPIO/SOUT_/NT/EU /FR T/S_LK/ULPI_/SSM_G/EIRQ P/GPIO/LINT/EU Y/EU Y/SSM_G/MP_ P/GPIO9/EU_9_Y/MP_O/EU Y/SSM_G/LINR/WKPU P/GPIO/LINT/EU G/S_T/SSM_G P9/GPIO/EU G/EU Y/SSM_G/LINR/WKPU P/GPIO/NT/NT/_M/MP_O P/GPIO/_M/EU Y/NR/NR/WKPU P/GPIO/EU H/FR_G/S_T/SIN_/EIRQ9 P/GPIO/EU H/SOUT_/FR_G/S_T P/GPIO/EU H/SLK_/EU Y/FR_G/EIRQ P/GPIO/EU H/S_/EU Y/FR_G/EIRQ _/MII_RMII_M/EU /NT/GPIO9/PG _S/EIRQ/NR/MII_RMII_T_LK/EU /GPIO9/PG LINT/NT/SOUT_/EU H/GPIO9/PG NR/WKPU/EU Y/S_/EU H/GPIO99/PG LINT/SLK_/EU HGPIO/PG LINR/SIN_/WKPU/EU Y/EU H/GPIO/PG MP_/EU Y/LKOUT/LINT/EU H/GPIO/PG MP_/WKPU/LINR/EU Y/LKOUT/EU Y/EU /GPIO/PG EIRQ/NT/S_/LINT/EU Y/GPIO/PG NR/WKPU/LINR/EU /SLK_/EU Y/GPIO/PG9 SIN_/ULPI_/EU Y/EU /GPIO/PG ULPI_/S_/S_/EU Y/GPIO/PG _S/MII_T/EU Y/SOUT_/EU Y/GPIO/PG _S/MII_T/EU Y/SLK_/EU Y/GPIO9/PG SIN_/ULPI_/LINT/EU /GPIO/PG LINR/ULPI_/SOUT_/EU H/GPIO/PG 9 (RMII_M) (MII_TLK) (US_) (US_) (US_) (US_) PG [] PG [] PG [] PG [] PG [] PG [] PG [] PG [] PG [] PG9 [] PG [] PG [] PG [] PG [] PG [] PG [] [] P [] P [] P [] P [] P [] P [] P [] P [] P [] P9 [] P [] P [] P [] P [] P P/GPI/_P/WKPU P/GPI9/_P/WKPU P/GPI/_P P/GPI/_P P/GPI/_P P/GPI/_P9 P/GPI/_P P/GPI/_P P/GPI/_P P9/GPI/_P P/GPI/_P alypso QFP PKGE OF GPIO PINS P/GPIO/S_/EU /O/_S P/GPIO/S_/EU Y/_S P/GPIO/S_/EU Y/FR_G/MLP/_S P/GPIO/S_/EU Y/FR_G/MLSP/MLT/_S _S/SIN_/MII_RMII_T/EU Y/EU H/GPIO/PH _S/MII_RMII_T/EU Y/SOUT_/EU H/GPIO/PH _S/MII_RMII_T_EN/EU_9_Y/SLK_/EU H/GPIO/PH _S/MII_T_ER/S_/EU H/GPIO/PH ULPI_/SL/SOUT_/EU H/GPIO/PH SIN_/ULPI_/S/EU H/GPIO/PH ULPI_/_M/_M/SLK_/EU /GPIO/PH ULPI_/_M/S_/_M/S_/EU_9_H/GPIO9/PH S_WP/S_RST/_M/_M/S_/EU H/GPIO/PH TK/RSV/GPIO/PH9 TMS/RSV/GPIO/PH ULPI_/EU H/S_/SOUT_/GPIO/PH ULPI_/EU Y/S_/SLK_/GPIO/PH EOUT/EU Y/S_/SOUT_/GPIO/PH EIN_ERR/EU Y/S_/SLK_/GPIO/PH EOUT/EU Y/EU Y/SOUT_/GPIO/PH 9 9 (RMII_T) (RMII_T) (RMII_TEN) (TK) (TMS) (US_) (US_) (LE) PH [] PH [] PH [] PH [] PH [] PH [] PH [] PH [] PH [] PH9 [] PH [] PH [] PH [] PH [] PH [] PH [] [,,] MU-RSTx [] PORSTx 9 RESET PORST [] MU-TL [] MU-ETL TL ETL Key to text colours: Purple - omms Physical Interfaces Orange - Other Peripherals and I/O lue - ebug (JTG & Nexus) lack - lock, Reset and ontrol RE - I/O Matrix and other functions (eg LE) Green - I/O Matrix (dedicated) PPGSKMKU utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: EVKIT-MPG alypso GPIO of Size ocument Number Rev SH-9 PF: SPF-9 Thursday, July, ate: Sheet of

8 alypso GPIO of U Key to text colours: Purple - omms Physical Interfaces Orange - Other Peripherals and I/O lue - ebug (JTG & Nexus) lack - lock, Reset and ontrol RE - I/O Matrix and other functions (eg LE) Green - I/O Matrix (dedicated) [] PI [] PI [] PI [] PI [] PI [] PI [] PI [,] PI [] PI (US_STP) (US_NT) (US_RST) PI PI PI PI PI PI PI PI PI 9 PI/GPIO/EU Y/LINT/S/S_T PI/GPIO9/EU_9_Y/SL/S_T/WKPU/LINR PI/GPIO/EU Y/LIN9T/S/S_T PI/GPIO/EU Y/SL/S_T/WKPU/LIN9R PI/GPIO/EU Y/SOUT_/ULPI_STP PI/GPIO/EU_9_Y/SLK_/S_/S_/ULPI_NT PI/GPIO/EU Y/S_/S_/S_ PI/GPIO/EU Y/S_/S_/S_ PI/GPIO/EU Y/MLP/MLLK/_S alypso QFP PKGE OF GPIO PINS [,] PI [] PI [] PI [] PI [] PI (ENET_RST) PI PI PI PI PI PI/GPIO9/EU Y/_S9/SIN_ PI/GPIO/S_/S_/_S PI/GPIO/S_/S_/_S PI/GPIO/SI_/E_OIS/E_OIS/_S/SIN_ PI/GPIO/S_/S_/E_OIS/E_OIS/_S/SI_MLK [] PJ [] PJ [] PJ [] PJ [] PJ (LE) PJ/GPIO/S_/S_/SI_SYN/EU_9_Y/E_OIS/E_OIS/_S PJ/GPIO/SOUT_/SI_LK/E_OIS/E_OIS/_S/SIN_ PJ/GPIO/S_/S_/S_/SI_/_S PJ/GPIO/S_/S_/S_/SI_LK/_S PJ/GPIO/SLK_/EU Y/EU Y PPGSKMKU esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG alypso GPIO of Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

9 N & LIN Physical N Physical Interface V_SR PER_HV V -.V input supply for N transceiver (. to.v) [] P [] P ll N and LIN signals are in power domain V_HV_. ll interfaces will work at.v or.v (PER_HV) [] P [] P VI/O - determines the signal level on MU T and R pins and can range from. to.v ST - High for Standby mode, pulled low for normal mode. (N_T) (N_R) LIN Physical Interface (LIN_R) (LIN_T) R R R R PER_HV LIN-R (Enable) (Wake) LIN-T (LEF = K aud) EN = PER_HV enables Transceiver and sets I/O for V_HV_ WKE = ensures no spurious wakeups U R EN WKE T R9.K MLEF.uF TPV N_T N_R N-S SILK = N-S INH VSUP LIN N-NH N-NL Master Mode Pullup Enable R J SRUP.UF.UF U T R ST HR V.uF VIO NH NL 9.uF M9WEF SRUP attery Reverse polarity & Pulse Protection.UF R.K R.K N termination resistor footprint. Place on underside of P R. LIN-VSUP LIN-LIN Total current through resistors (LIN us at ) = m (.W) Each resistor spec =.W (.W total) P HR R SILK = N VSUP P HR R MLEF LIN transceiver is newer version of offering: - Full LIN compliance ( no longer compliant) - Improved ES protection on LIN pin up to KV - Improved ES on Wake and VSUP Pins - Other EM and performance improvements See freescale.com for more details esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG N and LIN Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet 9 of

10 9 PER_HV OpenS interface [] TLK_HEER R K R K TLK U TLK PH9 [] K_VOUT LVG PER_HV S_USSHIEL SHELL SHELL SHELL SHELL SHELL efault -> K internal regulator V output -> external power supply through J as - US_MIRO_ VUS - + I J SILK = S L OHM L OHM V_SR S_US_ONN_N S_US_ONN_P T_S_US_I_TP PV_S TP.UF R SILK = VT T_VT_TP (Layout Note: Route US_N and US_P with PV_S 9 Ohm ifferential Pair. Keep tracks K_VOUT as short as possible) R9 R TP TP.UF S_US_N S_US_P PV_S R K SILK = S_JTG_RST uf.uf S_JTG_RST PV_S 9 9 U V V VSS VT VREGIN VOUT US_M US_P ETL TL RESET VSS JTG_TLK/SW_LK/EZP_LK/TSI_H/PT/URT_TS/URT_OL/FTM_H JTG_TI/EZP_I/TSI_H/PT/URT_R/FTM_H JTG_TO/TRE_SWO/EZP_O/TSI_H/PT/URT_T/FTM_H JTG_TMS/SW_IO/TSI_H/PT/URT_RTS/FTM_H NMI/EZP_S/TSI_H/PT/FTM_H/LLWU_P ETL/PT/FTM_FLT/FTM_LKIN TL/PT9/FTM_FLT/FTM_LKIN/LPTMR_LT _SE/TSI_H/PT/I_SL/FTM_H/FTM_Q_PH/LLWU_P _SE9/TSI_H/PT/I_S/FTM_H/FTM_Q_PH _SE/TSI_H/PT/SPI_PS/URT_RTS/FTM_H/IS_T/LLWU_P _SE/MP_IN/TSI_H/PT/SPI_PS/URT_TS/FTM_H/IS_T_FS MP_IN/PT/SPI_PS/URT_R/FTM_H/IS_T_LK/LLWU_P PT/SPI_PS/URT_T/FTM_H/MP_OUT/LLWU_P PT/SPI_SK/LPTMR_LT/IS_R/MP_OUT/LLWU_P9 MP_IN/PT/SPI_SOUT/P_ETRG/IS_R_LK/IS_MLK/LLWU_P MP_IN/PT/SPI_SIN/US_SOF_OUT/IS_R_FS RST_K S_ETL S_TL OUT_EN_PSS OOT_ENTRY S_LE JOMP_K T_K R_K TLK_K TI_K TO_K TP OpenS INTERFE JTG ONNETOR S_JTG_TMS S_JTG_TLK S_JTG_TO S_JTG_TI S_JTG_RST PF S GREEN S GREEN J 9 HR Y MHZ R R PV_S 9 PF SW SKRPE SILK = OOT PV_S PV_S TLK_K TI_K TMS_K JOMP_K TO_K T_K PV_S RST_K PV_S PV_S PV_S R U V V IR LVTGM, V U V V IR U LVTGM, V V IR U V IR LVTGM, PER_HV PER_HV JOMP TLK TI OUT_EN_PSS TMS PER_HV PER_HV Note: For PowerP devices with JOMP pin available, extra circuitry is needed to support it OUT_EN_PSS TO T_US_URT MU-RSTx [,,] R R K P [,] P [] K [] [] TI_HEER TMS_HEER R K R9 K TI PER_HV R K R K U TMS PER_HV U V TI LVG LVG PER_HV V TMS Y N P [] PH [].K LVHT % EP 9 PT/SPI_PS/URT_RTS/FTM_H/EWM_IN/LLWU_P _SE/PT/SPI_PS/URT_TS/URT_OL/FTM_H/EWM_OUT _SE/PT/SPI_PS/URT_R/FTM_H/FTM_FLT/LLWU_P PT/MT_IRO/URT_T/FTM_H/FTM_FLT R_T_EN TMS_K VTGT_EN VFLG R K PV_S PER_HV U R_T_EN V V IR R_K R_US_URT P9 [] MKVFM OpenS INTERFE PV_S uf R K R K U9 NPGVH VIN VOUT FULT ILIM EN V_TGT_OUT uf R.K LVHT utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: EVKIT-MPG OpenS Size ocument Number Rev SH-9 PF: SPF-9 Thursday, July, ate: Sheet of

11 US (Type Host and Type OTG) US Signals are in power domain V_HV_ The US interface only supports.v operation. ll I/O signals must be.v. If V_HV is set to V, US MU pads must be left as tri-state with no pullups or series resistors to be removed uf (Layout Note: Place Series Termination resistor ( Ohm) close to US I) V_SR [,] PI [] PH [] PH [] PG [] PG [] PE [] PE [] PG [] PG [] PI [] PI [] P [] P.UF PF R R R R99 R9 R9 R9 R R R R R Y R R M MHZ RYSTL (US_) (US_) (US_) (US_) (US_) (US_) (US_) (US_) (US_STP) (US_NT) (US_IR) US_LK V_SR _O _I 9 PF US V. (US_RST ctive Low) R9 K.UF U RESET T 9 T T T T T T 9 T STP NT IR LKOUT O REFLK VIO VP_ VP_ RIS US R.K % (Select MHz LKOUT with MHz TL) REFSEL REFSEL REFSEL Layout Note: Place caps & resistor as close to device as possible PEN VUS VT VP SPK_L I P SPK_R N_ M 9 V_SR US EN US VUS US V. V_SR US_I.UF.UF R uf 9 uf K (I= for HOST mode) R V_SR TPV R K SILK = FULT US Power Switch (K for HOST) US_N US_P (Layout Note: Route US_N and US_P with 9 Ohm ifferential Pair. Keep tracks as short as possible) R K U VIN FULT EN uf NPGVH.UF VOUT ILIM pf L OHM US PWR R.K uf US V pf US_MIRO_ VUS - + I J9 SILK = US 9 SHELL SHELL SHELL SHELL SHELL L OHM General Layout Note. Recommendation is to keep all tracks between MU and US PHI less than " esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG US Type / Type Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

12 9 Ethernet Physical Interface J HR V_SR L OHM V_ENET V_SR VIO_ENET R.UF.UF.UF R VIO_ENET VPLL_.V 9.UF. UF VIO_ENET.UF Layout Note: PLESE ROUT T/R N/P SIGNLS STRIGHTFORWR N VOI T-STUS ON RESISTOR P INTERONNETION V_ENET VIO_ENET [] RST-OUTx [,] PI PF V_SR R K Y R R9 PHY_RESET_ must be a GPIO toggeld after LKIN is active. MHZ R 9 PF R R9.K.K RMII_M [] PG RMII_MIO [] PF RMII_TLI RMII_TLO R RLK [] PG VIO_ENET R.K UF R9 PHY_RST_ TWTG U TP TM M RP RM MIO T I T O TEN 9 R REF_LK R RER RST LE/NEN_SPEE RS_RV/PHY/PHY INTRP V_V V_V VIO 9 RET KSZRN ENET_T_P ENET_T_N ENET_R_P ENET_R_N R R LE/SPEE RS_V RET PF R R R R9 (Layout Note: Ohm ifferential Pair. Keep tracks as short as possible Match pair within mils R.9K R9.K R.K RMII_T_ RMII_T_ RMII_TEN RMII_R_ RMII_R_ RMII_RER RMII_RS_V R.K PH [] PH [] PH [] P9 [] P [] P [] PF [,] R 9.9 ENET T_RIV.UF R 9.9 R 9.9 R 9.9 ENET R_RIV.UF R9 R9.UF R9 ENET_TT ENET_RT.UF J T+ T- TT N N RT R+ R- SH SH R LE_LINK L L VIO_ENET L L R-G R9 PHY_INT_ J HR PU_PER RST_ RMII_INT_ MU can drive the Pullup required by this signal Reset ontrol: - Reset from MU Reset Out (will reset with MU) - Reset from GPIO. llows MU to reset PHY as well as hold PHY in reset while reset config data can be driven onto pins to change mode etc. utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: EVKIT-MPG Ethernet Size ocument Number Rev SH-9 PF: SPF-9 Thursday, July, ate: Sheet of

13 FlexRY Physical Interface ll Signals are in power domain V_HV_. FlexRY interface will work at.v or.v (PER_HV) [] P [] P [] P [] P (FR_G) (FR_G) FlexRY debug connector P SILK = FR_G (FR_G) (FR_G) Note on VT: - Operational range is.v to V - Undervoltage detection is max.v On EV this is supplied from v, In theory this should be to battery with us delay between applying Vbat and I/O voltages. If necessary, V can be externally supplied by removing the resistor and connecting pad to v PER_HV V_SR FRT TPV R SILK = T uf ecoupling. Place next to power pins. FRT V_SR PER_HV uf.uf VT VUF V VIO.UF MOE EN STN Normal Rec Only Go to Sleep Sleep [] P [] PE [] PE GE: us Guardian Enable. Pull high to enable transmitter STN: Standby Input. Pull High for non standby mode EN: Enable Input. PUll high to enable (FR T) (FR T_EN) (FR R) PER_HV R R R R R R R K K K K FR-JT FR-JTEN FR-JR R K R K FR-GE FR-STN FR-EN FR-WKE U T TEN GE STN EN WKE VIO V VT INH P M R REN 9 ERRN TJ FR-INH FR-P FR-M FR-REN FR-ERRN TPV L LWSH TPV TPV FR-T- FR-T- R % R % 9 pf PF PF us voltage +/- V (VT = v) omponents spec'd for V operation P SILK = FLERY rimped lead Receptacle housing esigner: rawn IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG FlexRY Physical Interface pproved: Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

14 User Peripherals (Led's, Switches and Pot) Switches are hard wired to.v rather than V so it's not possible to drive V into a.v pad (which would cause damage) Similarly, the LE's are active low with.v supply so can be safely coupled to pads on either.v or V domains The input is limited to.v, again to prevent driving V into a.v pad which would cause damage Input Pot and Test Point [] PJ [] P [] P User LE's (ctive Low) (USR_LE) (USR_LE) (USR_LE) SILK = PJ SILK = P SILK = P S9 S S R R R V_SR PER_HV RV K.UF TP SILK = _P R (_P[]) P [,] [] P [] P [] P [] PH (USR_LE) (USR_LE) (USR_LE) (USR_LE) SILK = P SILK = P SILK = P SILK = PH S S S S R9 R R R User Pushbutton Switches (ctive High) SW SKRPE PER_HV SILK = SW_P (P_SW) P [] [] PH (USR_LE) SILK = PH S R9 SW SKRPE (P_SW) PE [] SILK = SW_PE R K R K esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group William annon rive West ustin, T -9 This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. EVKIT-MPG User Peripherals Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of

15 [] PH [] PH PER_HV SILK = PH TPV TPV9 SILK = PH [] PE [] PE [] PE [] PE9 [] PE [] PE [,] PF [] PE [] P [] P [] P [] P [] PI [,] PI [] PG [] PG [] PG [] PG9 GPIO onnectors PE [] PE [] PE [] PE [] P [] P [] PG [] PG [] PER_HV PER_HV [] PI [] PI R.K R.K [] PF [] PF [] PF [] PF [] P [] P [] P [] P [] P [] P [] P [] P [] P [] P J ESQ---T J ESQ---T- 9 9 J ESQ---T- PG [] PG [] PI [] PI [] P [] P [] PF [] PF [] R.K R.K PH [] PH [] NOTE: J,J,J and J: rduino UNO compatible headers. J and J: rduino Mega compatible headers. PER_HV SRUP V_IN V_SR V_SR [] PI [] PI [] PI [] PI [,] PI [] PI [] PG [] PG [,,] MU-RSTx P [] P [] P [] PH [] PH [] PH [] PJ [] PJ [] PJ [] PJ [].uf [] PF [] PF [] PF [] PF [] PF [] PF [] PF [] PF9 [,] P [] P [] P [] P [] P [] P [] P [] P J ESQ---T- 9 9 J ESQ---T- 9 9 J ESQ---T- P [] William annon rive West P [] PER_HV ustin, T -9 P [] P [] This document contains information proprietary to NP and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of NP Semiconductors. P [] P9 [] P [] P [] esigner: rawn pproved: IP lassification: P: IUO: PUI: rawing Title: utomotive Product Group EVKIT-MPG GPIO onnectors Size ocument Number Rev SH-9 PF: SPF-9 ate: Thursday, July, Sheet of