Direct Digital Synthesizers (DDS)

Transcription

1 pplication Note irect igital Synthesizers (S) Using the nalog evices 9 bit S to Generate Precision Frequencies in the range 0 to 0MHz and Precision ontiguous Phase hanges down to ns. 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

2 Introduction Precision irect igital Synthesizers are now available that allow a multitude of special functions to be implemented with excellent precision and at high speed. This application note describes a fairly simple application of the 9 bit precision S to produce precision frequencies in the range from 0Hz () to 0MHz, implemented in the Precise Time and Frequency, Inc. option pcb model number 9 0. In addition, the module can be used to generate a precision phase contiguous phase change down to as small as ns. Overview of Implementation In this application, the requirement is not for high speed mode switching of the S, but rather to use the S in the "Single Tone" mode generate a preselected output frequency that can be locked to a precision input 0MHz reference frequency. Frequency range has been limited to 0MHz maximum in order to minimize heat generation within the device. Frequency Setup and Range For the purpose used here, high speed communication with the S is not critical as the frequency to be set is preselected, calculated and then the bit word loaded into the appropriate register of the S. In some applications (e.g. frequency hopping) this method may be inadequate and the much faster parallel communication method should be used, however this substantially increases the complexity of layout using address and bi directional data bits, instead of a single serial communication line. The serial method also substantially reduces interconnection complexity if the controlling device(s), in this case a PL / Microprocessor combination are located off board. When operated in the Single Tone mode, the device can be programmed to generate any frequency from 0Hz () up to 0, x System lock frequency. There are a number of factors to take into account when determining the maximum frequency to be output, but the overriding parameter to consider is device heat generation. In order to operate, the S must be supplied with an external reference clock. If the internal clock multiplier is enabled, the system clock can then be up to 0 times the external reference clock, with permissible reference clock frequencies up to 0MHz (TZ version) or MHz (VZ version) with the limitation that maximum allowable system clock frequency is 00MHz. The downside of this is that the device will generate significant heat when utilizing this function, and therefore adequate cooling must be provided if system failure is to be avoided, and reliability maintained. 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

3 For this application, it was determined to use a 00MHz external clock with the S internal multiplier disabled, giving a System lock frequency of 00MHz. The 00MHz external clock was integrated into a PLL locked to an incoming precision 0MHz reference, to insure precision output frequencies. This implementation therefore limits the maximum frequency to 0MHz (0. x System lock), although provision has been made to modify the external clock frequency (through a divider in the PL) to allow the S internal multiplier to be used to attain System lock frequencies of 00MHz, giving output frequency capability up to 00MHz, if desired. If the higher System lock frequency is invoked, attention is required to provide revised cooling system to avoid overheating. In order to setup a particular frequency out of the S, it is necessary to calculate a "Frequency Tuning Word" (FTW). The value of the FTW is dependent upon S resolution n ( bit in this case), system clock frequency f clk (00MHz in this case), and of course the output frequency desired, f o. The equation is: FTW = so to calculate the frequency tuning word required to setup a 0MHz output frequency, the equation becomes; FTW = 0,000,000,, FTW =,,,, =,9,99,,. FTW is always an integer, with a minimum value of, so the smallest step size (i.e. resolution) f min possible with a 00MHz clock can be calculated from by setting FTW to as follows: =,, 00,000,000 giving a maximum resolution attainable of approximately 0. milli Hz. 00,000, ,,9,0, 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

4 Setting up the 9 to ccept a FTW efore loading the Frequency Tuning Word (FTW) into the 9, it is necessary to configure the device to be ready to accept the FTW. The various input / output hardware connections required are shown on the diagram below. For a full schematic please see ppendix. 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

5 The sequence is as follows; Following initial power on, the Master Reset line on each 9 device must be toggled high for a minimum of 0 system clock cycles ( 00 nano seconds in this case) to initialized the device. This initializes the device default values, and initializes the communications. Following the Master Reset line returning to low, the Reference lock is temporarily disable to allow loading of the initial control word setting the I/O update line to external. The sequence of events is then;. Synchronize communications. Send an bit instruction byte which tells the S what data to expect (e.g. mode setup, FTW etc), and how many bytes of data to expect.. Sending of the data defined in step. (an be,, or bytes depending upon data type) for the FTW this is bytes (i.e. bits). Toggle the I/O update line to load the data just sent. For added security and integrity, the 9 0 then enters a "read back" mode whereby the data just written is read back to insure it was transmitted correctly and accepted. Theoretically the device is then ready for the next instruction byte, however again to insure synchronization of communications is maintained, the 9 0 re synchronizes communications before each new instruction/data set. The above communication sequence is followed to first setup the mode (in this case it is Single Mode and mode setup is somewhat redundant as Single Mode is set by default after a power on Master Reset), then In order to provide high quality sine wave outputs, following the 9 output there is a th order low pass elliptic filter with a bandwidth of 0MHz. This would need to be redesigned to cater for higher output frequencies if implemented. lso the "Inverse Sync" mode of operation is selected to reduce output amplitude variations with different frequency selections. Each 9 0 pcb houses two S devices, allowing two completely independent precision frequency outputs. In order to control which device is being accessed, the chip select lines are setup by the supervisory processor/pl and then decoded on each pcb. 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

6 Implementing Phase ontiguous Phase hanges To change the phase of the output frequency, a small frequency offset is applied for a precise amount of time. the frequency offset is calculated from: where: or:. dt = the phase shift required in seconds T = the time for which the offset frequency is to be applied F = the output frequency df = the desired frequency change for time T For example, if the output frequency is set to 0MHz (00 ns per cycle) then to change the phase of the output by 0ns in 0.0 seconds we would need to apply a frequency offset of; df = 0 E. = 00 Hz frequency change for 0.0 seconds lso, dependent upon whether we wish a positive or negative phase change, we would either decrease or increase the frequency by the df value respectively. Implementation of this function is relatively straightforward by utilizing the dual frequency register feature of the 9 device. First the desired phase change is determined and the offset frequency required to achieve the change is calculated. required Frequency Tuning Word (FTW) is then calculated and loaded into the second frequency register, Frequency Tuning Word. precision time interval can be attained by dividing down the 0MHz (or 00MHz clock) and once Frequency Register has been set to the desired offset frequency, the precision time interval is applied to the FSK input (pin 9). This has the effect of switching to Frequency Register for precisely the amount of time the pulse is applied, changing the output phase by the desired amount. 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

7 ependent upon slew rates required/time to achieve new phase, the time period of application and offset frequency can be calculated accordingly, bearing in mind that it is generally far simpler to develop an integer precision pulse, and leave any fractional requirement to the frequency offset! onclusion This note is intended as an aid to those people wishing to use a precision bit S and while it is not a fully comprehensive description it may save many hours trying to determine functionality/criticality of the multitude of i/o pins provided. Using the same configuration it is also a relatively small jump to implement some of the more complex functions of the device if desired. Finally, detailed source code (in '') for the calculations/interfacing to the device are available from Precise Time and Frequency, Inc. upon request. 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

8 ppendix 9 0 Schematic 0L udubon Road, Wakefield, M 00, US Tel: 9090 Fax:

9 With heat sink pad U TP0 V LMI OUT.V.V 0.uf 0uf, V GN R 00 0uf, V 0.uf R uss Optional ontrols Power J J J.V Logic Levels R 0k R 0k V V I/O Update Sata I/O Reset Sclk /S MR R 0k -V Fault R 0k R 0k R 0k S 00MHz Master Reset I/O Update In I/O Update In FSK In OSK In FSK In OSK In I/O Reset Sata I/O Update V V GN GN N /IO RESET /SO 0/SIO I/O U LK V 0 V 9 GN GN GN GN V V GN MSTER RESET S/P SELET 0 REFLK 9 REFLK GN GN V IFF LK ENLE N GN PLL FILTER U9 9 WR/SLK R/S V V V GN GN GN FSK/PSK/HOL SHPE KEYG V V GN GN N VOUT V V GN GN uf V 0 GN 9 N N RSET P V GN IOUT IOUT V 0 IOUT 9 IOUT GN GN GN V VN VP GN R.k 0 0.0uf R 9.9 R 9.9 TP omparator Reference R9.9k TP R0 9.9 R 9.9 S O/P Vpp w/ 0.V omparator MTG # MTG # Sclk /S OSK 0V /S MR.V U0 VHG0.V.V Vcc U VH0 Gnd FSK /S Master Reset.V 0.uf 0 0uf V Vs OE Vs- VH GN VL U0 ELS R9 0. W J N up to 0MHz Operation Logic Level Output Vcc U VH0 Gnd.V 9 0.uf.V 0.0uf Master Reset 0.0uf 0.0uf 0.0uf 0.0uf 0.uf 0.uf 0.uf 0.uf 9 0uf V Title 9 S oard S Size ocument Number R ev 9 ate: Tuesday, ecember, 00 Sheet of

10 .V V R 00 R0 0k R.k Q LT Lock LE V R 0 R.k R 0 fault lock power J LE onnector R K Zero dj. R.99k R uf V 0.0uf V - LMH0 U -V 0 R 9. R 00 Fault R9 0k R 0k G S Q FNN omparator -V 0.0uf V S O/P 0 pf.pf L 0nH 0pf pf L 0nH 0pf pf L 0nH 9pf R k Z R uf V - LMH0 U -V R 9.9 J N dm Output -V 0.0uf th Order Low Pass Elliptic Filter with 0MHz andwidth TP U U9 V LMI OUT LMIMP V -V Vin Vout -V dj GN R0 R 0uf, V uf, V 0uf, V 0.uf 0.uf 0uf, V 0.uf 0.uf TP R9 R Title 9 S oard S O/P Size ocument Number R ev 9 ate: Tuesday, ecember, 00 Sheet of

11 With heat sink pad U TP V LMI OUT.V.V 0.uf 0uf, V GN R uf, V 0.uf S 00MHz R Master Reset 0.0uf I/O Reset Sata I/O Update V V GN GN N /IO RESET /SO 0/SIO I/O U LK V 0 V 9 GN GN GN GN V V GN MSTER RESET S/P SELET 0 REFLK 9 REFLK GN GN V IFF LK ENLE N GN PLL FILTER U 9 WR/SLK R/S V V V GN GN GN FSK/PSK/HOL SHPE KEYG V V GN GN N VOUT V V GN GN V 0 GN 9 N N RSET P V GN IOUT IOUT V 0 IOUT 9 IOUT GN GN GN V VN VP GN R.k 0.0uf R 9.9 R 9.9 TP9 omparator Reference R.9k TP R9 9.9 R0 9.9 S O/P Vpp w/ 0.V omparator Sclk /S 0V OSK FSK 9 0.uf 0uf V Vs OE Vs- VH GN VL U ELS up to 0MHz Operation R0 0. W J0 N Logic Level Output.V 9 0.0uf 0 0.0uf 0.0uf 0.0uf 0.uf 0.uf 0.uf 0.uf 0uf V Title 9 S oard S Size ocument Number R ev 9 ate: Tuesday, ecember, 00 Sheet of

12 V R 00 R.99k V 9 0.0uf R K Zero dj. R uf V - LMH0 U -V 9 R 9. R 00 omparator -V 0.0uf V 9 S O/P pf.pf L 0nH 0pf pf L 0nH 0pf 9 pf L 0nH 9pf R9 k Z R uf V - LMH0 U -V 9 R0 9.9 J N dm Output -V 0.0uf th Order Low Pass Elliptic Filter with 0MHz andwidth With heat sink pad U TP U TP LMI V OUT LMI 0V V OUT.V 00 0.uf 9 0uf, V GN R 0 9 0uf, V 99 0.uf 0 0.uf 0 0uf, V GN R uf, V 0 0.uf R.0k R Title 9 S oard S O/P Size ocument Number R ev 9 ate: Tuesday, ecember, 00 Sheet of

13 Phase et Hi 0 MHz Phase et Low J Power 0MHz Input J SM R0 k 0MHz Output J9 SM V -V V Fault R 9.9 R.k GN.V U LVGUR uf R9 k 0.0uf R0 0k.V Vcc R k 0.0uf J 0-0.0uf 0.0uf R. Termination.V R 0k R 0k.V U V - LMV9 GN U 0 HI LO ENL OMM F OFLT VPOS Vout 9 0.0uf R 9.9k.V Nominal 0.0uf R 00k TP Input Level 0.0uf TP Test 0pf 0MHz 0dm Threshold (.0V) select R k R 9.9k R 9.9k 0.uf R 0 R 0k.V U V - LMV GN R 00k R.0k 0pf 0.00uf PLL ontrol Red High = PLL Operation Low = Fixed ontrol Voltage.V U V - LMV9 GN R Meg 0.uf Fault Fault LE TP PLL ontrol 0.0uf GN.V R9 k 0.uf U LVGUR.V Vcc U N OSK In FSK In I/O Update In I/O Update In TI TMS TK PLL ontrol OSK In FSK In Hi = ext RF input R k VHG0 0 0.uf.V V TK TO TI TMS.V 0.0uf R k 9 0.0uf 0.uf Lock LE Test I/O Update PLL ontrol.v ontrol Voltage V 9 0.uf TP 0.0uf I/O/GK I/O- I/O- GN I/O- I/O- I/O- I/O- 9 TI 0 TMS TK J 0- V JTG 0.00uf Title R 00k 0.uf Vc GN U X9VQ V VXO V X 00MHz I/OGK I/OGK I/O- I/O- I/O- 0 I/O- 9 I/O- I/O- I/OGTS VTV I/OGTS I/O- I/O- I/O-9 VTV I/O-0 GN I/O- I/O- I/O- I/O- I/O- 9 0 Gnd Set U Out iv LT99 J SM Vcc O/P.V I/OGSR I/O- I/O-0 I/O-9 0 I/O- 9 I/O- I/O- VIO.V/V GN TO I/OGK 0.0uf.V 0.0uf uf 00kHz.V 9 S oard PLL 00MHz Phase et Hi 00MHz Phase et Low FSK OSK S 00MHz I/O Update 00kHz TO I/O Update 0MHz OSK FSK S 00MHz Size ocument Number R ev 9 ate: Tuesday, ecember, 00 Sheet of TP 0.uf