PI3HDMI1210(-A) PI3HDMI1210-A Demo Board Rev.A User Manual
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1 PI3HDMI1210(-A) PI3HDMI1210-A Demo Board Rev.A User Manual Introduction This user manual describes the components and the usage of PI3HDMI1210(-A) demo Board Rev.A. Figure 1: Top View of PI3HDMI1210-A Demo Board Figure 2: Bottom View of PI3HDMI1210-A Demo Board Page 1 of 11 AN208 09/24/07
2 Key Components / Circuits a. As PI3HDMI1210(-A) is a 2:1 MUX, a SPDT switch at reference SW1 is used to choose either Port A or B as the input port manually. Figure 3: SPDT Switch SW1 When switch SW1 is tied to low, IN and SEL pins of PI3HDMI1210(-A) are set to 0V and 1.5V, respectively, in order to transfer high speed and side-band signals through Port A. When SW1 is switched to high, IN and SEL pins are pulled to 3.3V, Port B is then selected. Figure 4: Schematic of Port Selection Page 2 of 11 AN208 09/24/07
3 b. PI3HDMI1210-A demo board can be powered up via three ways, i.e. using 5V supplied from Power Jack (J7), from USB Type B Connector (J8), or from Port A/B (J6). Jumper J6 is not connected at default. Figure 5: Schematic of 5V Power Supply c. Two AT24C02B EEPROMs are implemented in PI3HDMI1210-A demo board to model I2C application. The EEPROMs are for DDC line capacitance measurement purpose. Please refer to p.8 for measurement result. A0 and A1 address inputs of AT24C02B are pulled to low by external pull-down resistors while address A2 is pulled high. Write protection of the EEPROM is disabled. Figure 6: Schematic of EEPROM Page 3 of 11 AN208 09/24/07
4 d. HPD reset circuitry is implemented at SEL pin. When switching port using switch SW1, a 300ms pulse is sent to reset the HPD pin at the de-selected port so as to reset HDCP Transmitter Link State back to reset state H0. For details, please refer to Application Note AN202 of PI3HDMI1210 for TV Application. Figure 7: Schematic of HPD Reset Circuit Page 4 of 11 AN208 09/24/07
5 TDR Measurement Differential impedance of PI3HDMI1210(-A) on a demo board is measured to confirm the trace impedance is within the requirement described in Test ID 8-8 in HDMI Compliance Test Specification Version 1.3a. Table 1: HDMI Pre-test Test ID 8-8 Specification CDF field Sink_Diff_PowerOn = Y for this device. This means no termination impedance can be obtained. Filter of 180ps is employed throughout the measurement. For Port A: Sink_Term_Distance of D2 = 0.68ns Sink_Term_Distance of D1 = 0.66ns Sink_Term_Distance of D0 = 0.66ns Sink_Term_Distance of CLK = 0.64ns For Port B: Sink_Term_Distance of D2 = 0.60ns Sink_Term_Distance of D1 = 0.60ns Sink_Term_Distance of D0 = 0.62ns Sink_Term_Distance of CLK = 0.62ns Through Impedance D2 D1 D0 CLK Spec Min Max Units Port A Port B Min Ω Max Ω Min Ω Max Ω Table 2: TDR Through Impedance Result Page 5 of 11 AN208 09/24/07
6 Figure 8a: TDR at D2 of Port A Figure 8b: TDR at D1 of Port A Figure 8c: TDR at D0 of Port A Figure 8d: TDR at CLK of Port A Page 6 of 11 AN208 09/24/07
7 Figure 9a: TDR at D2 of Port B Figure 9b: TDR at D1 of Port B Figure 9c: TDR at D0 of Port B Figure 9d: TDR at CLK of Port B Page 7 of 11 AN208 09/24/07
8 DDC/CEC Line Capacitance Measurement The capacitances of SDA and SCL signals which go through EEPROM AT24C02B are tested and ensured within HDMI CTS V1.3a requirement. The capacitance of CEC line connecting input to output HDMI is also measured. C DUT = C2 C1 Setting of Impedance Analyzer for measuring capacitance: For SDA/SCL, Freq=100kHz, DC Bias=2.5V, Power=15dBm (AC~1.8Vpp at DUT), IF BW=1kHz, Sweep Time=1s For CEC, Freq=100kHz, DC Bias=1.65V, Power=15dBm (AC~1.8Vpp at DUT), IF BW=1kHz, Sweep Time=1s Connector J1 Pin Parameter DUT Power Spec Off On Min Max Units SDA SCL CEC C NA NA pf C NA NA pf C DUT pf C NA NA pf C NA NA pf C DUT pf C NA NA pf C NA NA pf C DUT pf Table 3a: DDC/CEC Line Capacitance Result at Connector J1 Connector J3 Pin Parameter DUT Power Spec Off On Min Max Units SDA SCL CEC C NA NA pf C NA NA pf C DUT pf C NA NA pf C NA NA pf C DUT pf C NA NA pf C NA NA pf C DUT pf Table 3b: DDC/CEC Line Capacitance Result at Connector J3 Page 8 of 11 AN208 09/24/07
9 Appendix A: PCB Schematic Note: 0Ω resistor should be soldered at C7 if PI3HDMI1210-A is assembled on the demo board. If the board is used for PI3HDMI1210, 10nF decoupling capacitor should be placed at C7. Page 9 of 11 AN208 09/24/07
10 Appendix B: PCB Layout Requirements a. Stack Up: Plane Material Thickness (mil) Signal 1.9 Prepreg Ground 1.2 Core 44 Power 1.2 Prepreg Signal 1.9 b. Isolation Spacing = 30 mil c. Width & Spacing (W/S) of 100Ω Differential Trace = 9.0 / 11 mil Page 10 of 11 AN208 09/24/07
11 Appendix C: BOM List Item Quantity Reference Description 1 3 C1, C14, C15 0.1uF Capacitor 2 7 C2, C3, C4, C5, C6, C8 10nF Capacitor 3 2 C9, C10 4.7uF Capacitor 4 1 C11 22uF Capacitor 5 3 C12, C13, C17 1uF Capacitor 6 1 D1 BAV70 Double Diode with Common Cathodes 7 1 D2 BAW56 Double Diode in Series 8 3 D3, D4, D5 B0520LW Schottky Rectifier 9 2 J1, J3 HDMI Receptacle Connector 10 1 J2 HDMI Plug Connector 11 3 J4, J5, J6 2-pin Header 12 1 J7 Power Jack 13 1 J8 USB Type B Connector 14 5 Q1, Q2, Q3, Q4, Q5 MMBT3906 PNP Transistor 15 5 Q6, Q7, Q8, Q9, Q10 MMBT3904 NPN Transistor 16 5 R1, R6, R7, R8, R19 4.7kΩ Resistor 17 3 R2, R9, R14 1kΩ Resistor R3, R4, R5, R10, R11, R26, R30, R34, R35, R37, R38, R39, R41 47kΩ Resistor 19 1 R12 18kΩ Resistor 20 1 R13 15kΩ Resistor 21 1 R15 68kΩ Resistor 22 1 R16 10kΩ Resistor 23 1 R17 2.7kΩ Resistor 24 4 R18, R21, R22, R23 20kΩ Resistor 25 1 R20 1.5kΩ Resistor 26 2 R33, C7 0Ω Resistor 27 8 R24, R25, R27, R28, R29, R31, R36, R40 NOT AVAILABLE 28 1 SW1 SPDT Switch 29 1 U1 PI3HDMI1210 HDMI Switch 30 1 U Regulator 31 2 U3, U4 AT24C02B EEPROM Page 11 of 11 AN208 09/24/07
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