PPTS ON INTEGRATED CIRCUIT APPLICATIONS (ECE) III B.Tech V semester (Autonomous R16) ( )

Transcription

1 PPTS ON INTEGRATED CIRCUIT APPLICATIONS (ECE) III B.Tech V semester (Autonomous R16) ( ) Prepared by Ms. C. Deepthi, AssistantProfessor Ms. N.Anusha, AssistantProfessor Ms. P Saritha, AssociateProfessor ELECTRONICS AND COMMUNICATION ENGINEERING 1

2 Unit-1 Integrated circuits 2

3 Introduction to ICs Classifications of ICs: Analogue IC - work with a composite signal - an example is operational amplifier Digital IC - work with digital signal - an example is logical circuit 3

4 Package types and temperature ranges Package types and temperature ranges 4

5 Package types and temperature ranges The IC packages are classified as, Metal Can Dual In Line Flat Pack Metal Can 5

6 Package types and temperature ranges Dual- In-Line package 6

7 Package types and temperature ranges Flat Pack 7

8 Package types and temperature ranges Military temperature range : -55 o C to +125 o C(-55 o C to +85 o C) Industrial temperature range : -20 o Cto +85 o C (-40 o C to +85 o C) Commercial temperature range: 0 o C to +70 o C (0 o C to +75 o C) 8

9 Differential Amplifier Differential Amplifier 9

10 Differential amplifier A differential amplifier is a type of electronic amplifier that amplifies the difference between two input voltages but suppresses any voltage common to the two inputs. It is an analog circuit with two inputs and one output in which the output is ideally proportional to the difference between the two voltages. Two identical emitter biased circuits Dual i/p, balanced o/p differential amplifier 10

11 Differential amplifier configurations The four differential amplifier configurations are : Dual input, balanced output differential amplifier. Dual input, unbalanced output differential amplifier. Single input balanced output differential amplifier. Single input unbalanced output differential amplifier. 11

12 Dual i/p, balanced o/p differential amplifier 12

13 Dual i/p, unbalanced o/p differential amplifier 13

14 Single i/p, balanced o/p differential amplifier 14

15 Single i/p, unbalanced o/p differential amplifier 15

16 Dual i/p, balanced o/p - DC analysis Dual i/p, balanced o/p - DC analysis 16

17 Dual i/p, balanced o/p DC - analysis DC equivalent circuit V CEQ =V CE = V CC + V BE - I C R C 17

18 Dual i/p, balanced o/p - DC analysis Dual i/p, balanced o/p - DC analysis 18

19 Dual i/p, balanced o/p - DC analysis DC equivalent circuit V CEQ =V CE = V CC + V BE - I C R C 19

20 Dual i/p, balanced o/p - AC analysis Dual i/p, balanced o/p - AC analysis 20

21 Dual i/p, balanced o/p - AC analysis AC Equivalent circuit Voltage gain,a d =R C /r e 21

22 Dual i/p, balanced o/p - AC analysis Dual i/p, balanced o/p - AC analysis 22

23 Dual i/p, balanced o/p - AC analysis AC Equivalent circuit Voltage gain,a d =R C /r e 23

24 Properties of differential amplifier Properties of differential amplifier 24

25 Properties of differential amplifier Dual i/p and balanced o/p configuration Voltage Gain, A d = R C /r e I/P Resistance, R i1 = R i2 = 2β ac r e O/P Resistance, R o1 =R o2 =R C 25

26 Properties of differential amplifier Dual i/p and unbalanced o/p differentialamplifier Voltage Gain, A d = R C /2r e I/P Resistance, R i1 = R i2 = 2β ac r e O/P Resistance, R o =R C 26

27 Properties of differential amplifier Single i/p and balanced o/p configuration Voltage Gain, A d = R C /r e I/P Resistance, R i = 2β ac r e O/P Resistance, R o1 =R o2 =R C 27

28 Properties of differential amplifier Single i/p and unbalanced o/p differentialamplifier Voltage Gain, A d = R C /2r e I/P Resistance, R i = 2β ac r e O/P Resistance, R o =R C 28

29 Cascade Differential Amplifier Cascade Differential Amplifier 29

30 Cascade Differential Amplifier DC Coupling amplifier The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MH Z to which feedback is added to control its overall response characteristic i.e. gain and bandwidth. The op-amp exhibits the gain down to zero frequency. Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since these would reduce the amplification to zero at zero frequency. 30

31 Cascade Differential Amplifier Cascade differential amplifier stages 31

32 Level Translator Level Translator 32

33 Level Translator Fig: a) Common collector Amplifier with voltage divide b) Emitter follower with constant current bias c) Emitter follower with current mirror 33

34 Op-Amp block diagram & specifications Op-Amp block diagram & specifications 34

35 Op-Amp block diagram & specifications Op-amp Block Diagram Block Diagram Symbol 35

36 Op-Amp block diagram & specifications Ideal Op-Amp specifications The input resistance R IN would beinfinite The output resistance R OUT would be zero The voltage gain, V G would be infinite The bandwidth (how quickly the output will follow the input) would be infinite If the voltages on the two inputs are equal than the output voltage is zero ( If the output is not zero it is said to have an offset) 36

37 Op-Amp block diagram & specifications Practical OP-AMP characteristics The open loop gain of practical Op Amp is around7000. Practical Op Amp has non zero offset voltage. That is, the zero output is obtained for the non zero differential input voltage only. The bandwidth of practical Op Amp is very small value. This can be increased to desired value by applying an adequate negative feedback to the Op Amp. 37

38 Op-Amp block diagram & specifications Practical Op-Amp specifications The output impedance is in the order of hundreds. This can be minimized by applying an adequate negative feedback to the Op Amp. The input impedance is in the order of Mega Ohms only. (Whereas the ideal Op Amp has infinite input impedance). 38

39 DC Characteristics of Op-Amp DC Characteristics of Op-Amp 39

40 DC Characteristics of Op-Amp Input bias current Input offset current Input offset voltage Thermal drift 40

41 Input bias current DC Characteristics of Op-Amp Input bias current Inverting amplifier with bias current I B = (I B + +I B - )/2 V o = I - B R f and 41

42 Input bias current DC Characteristics of Op-Amp R Comp = R 1 ǁ R f Bias current compensation in an invertingamplifier 42

43 DC Characteristics of Op-Amp In put offset current Inverting amplifier with T-Feedback network ǀI os ǀ = I + - I -, V = R I and R = R 2 / (R 2R) B B o f os s t f t 43

44 DC Characteristics of Op-Amp DC Characteristics of Op-Amp 44

45 DC Characteristics of Op-Amp Input bias current Input offset current Input offset voltage Thermal drift 45

46 Input offset voltage DC Characteristics of Op-Amp Op-Amp with input offset voltage 46

47 DC Characteristics of Op-Amp Input offset voltage Inverting Amplifier Equivalent circuit for Vi = 0V V o = (1+R f /R 1 )V ios 47

48 DC Characteristics of Op-Amp Total O/P offset voltage Offset null circuit for IC741 Balancing circuit for inverting amplifier 48

49 DC Characteristics of Op-Amp Total O/P offset voltage Balancing circuit for non-inverting amplifier 49

50 DC Characteristics of Op-Amp Thermal Drift Bias current, offset current, and offset voltage change with temperature A circuit carefully nulled at 25 o Cmay not remain. So when the temperature rises to 35 o C. This is called drift. Offset current drift is expressed in na/ o C. These indicate the change in offset for each degree Celsius change in temperature. 50

51 DC Characteristics of Op-Amp DC Characteristics of Op-Amp 51

52 DC Characteristics of Op-Amp Design an inverting amplifier circuit using IC 741 Op-Amp to get a gain of -10 and an input impedance o 10MΩ. That is, calculate Rt, Rs and R1. Sol : Set input impedance Ri = 10MΩ, pick R1 = 10MΩ Since ACL = -(RF /R1) Therfore RF = ACL R1 = 100MΩ Choose Rt = 47KΩ Rs = Rt 2 / (Rf 2Rt) =22Ω 52

53 AC Characteristics of Op-Amp AC Characteristics of Op-Amp 53

54 AC Characteristics of Op-Amp Frequency response Stability of an Op-Amp Frequency compensation Slew rate 54

55 AC Characteristics of Op-Amp Frequency Response High frequency model of an Op-Amp with single corner frequency A = A ol /(1+j(f/f 1 )) where f 1 = 1/2πR o C Φ = -tan -1 (f/f 1 ) 55

56 AC Characteristics of Op-Amp Frequency Response Open loop magnitude characteristics and phase characteristics for an op-amp with single break frequency 56

57 AC Characteristics of Op-Amp Frequency Response Approximation of open loop gain vs frequency curve A = A OL. ω 1. ω 2. ω 3 / ((s + ω 1 ) (s + ω 2 ) (s + ω 3 )) 57

58 AC Characteristics of Op-Amp Stability of an Op-Amp Typical closed loop system Condition for Magnitude ǀAβǀ = 1 Condition for Phase - Aβ=0 or - Aβ=π 58

59 AC Characteristics of Op-Amp AC Characteristics of Op-Amp 59

60 AC Characteristics of Op-Amp Frequency response Stability of an Op-Amp Frequency compensation Slew rate 60

61 AC Characteristics of Op-Amp Frequency compensation Two types of frequency compensation techniques: Dominant Pole compensation External compensation Pole zero (Lag) compensation Internal Compensation Dominant Pole Compensation Transfer function A = A OL /((1+jf/f d )( 1+jf/f 1 ) (1+jf/f 2 ) (1+jf/f 3 )) Where f d <f 1 <f 2 <f 3 61

62 AC Characteristics of Op-Amp fd Dominant-pole compensation No Compensation - 20dB/decade - 40dB/decade Gain Vs frequency curve for dominant pole compensation 62

63 AC Characteristics of Op-Amp Vi A R1 Vo C2 Pole-zero compensation Transfer function A = A OL /((1+jf/f o )( 1+jf/f 1 ) (1+jf/f 2 )(1+jf/f 3 )) Where 0<f 0 <f 1 <f 2 <f 3 63

64 AC Characteristics of Op-Amp Pole-zero compensation f0-20db/decade No Compensation -20dB/decade -40dB/decade Gain Vs frequency curve for Pole-zero compensation 64

65 AC Characteristics of Op-Amp Frequency response for internally compensated 65

66 AC Characteristics of Op-Amp Slew rate The maximum rate of change of output voltage caused by a step input voltage and is usually specified in V/µs. SR = = and SR = 2πfv m V/s 66

67 Features of IC741 Op-Amp Features of IC741 Op-Amp 67

68 Features of IC741 Op-Amp IC 741 Op-Amp Symbol IC 741 Op-Amp Pin diagram 68

69 Features of IC741 Op-Amp Features of Op-Amp No frequency compensation required. Short circuit protection provided. Offset voltage null capability. Large common mode and Differential voltage range. No latch up. No External frequency compensation is required Short circuit Protection Low Power Dissipation 69

70 CMRR & PSRR CMRR & PSRR 70

71 CMRR & PSRR CMRR Common mode rejection ratio is defined as the ratio of differentialgain A DM to the common mode gaina CM. CMRR is given by, ρ= A DM / A CM in db PSRR Power Supply Rejection Ratio. It is defined as the change in the input offset voltage due to the change in one of the two supply voltages when other voltage is maintained constant. 71

72 UNIT -2 OPAMP APPLICATIONS 72

73 Inverting amplifier Inverting amplifier 73

74 Inverting amplifier The inverting configuration with three inputs Va, Vb, and Vc. Depending on the relationship between the feedback resistor R f and the input resistors Ra, Rb, and Rc, the circuit can be used as either a summing amplifier, scaling amplifier, or averaging amplifier. The circuit s function can be verified by examining the expression for the output voltage V0, which is obtained from Kirchhoff s current equation written at node V2. 74

75 Inverting amplifier 75

76 Non Inverting amplifier Non-Inverting amplifier 76

77 Non Inverting amplifier 77

78 Non Inverting amplifier Substractor 78

79 INTEGRATOR INTEGRATOR 79

80 Integrator 80

81 Integrator 81

82 Integrator 82

83 PROBLEMS ON INTEGRATOR PROBLEMS ON INTEGRATOR 83

84 Problems on integrator Q1.consider the lossy integrator for the component values,r1=10k Rf=100K,Cf=10nF,Determine the lower frequency limit of integration and study the response for the inputs i)sine wave ii)step wave 84

85 Problems on integrator Q2.Find R1 and Rf in the lossy integrator so that the peak gain is 20dB and the gain is 3dB down from its peak when ω =10000 rad/s. use a capacitance of 0.01µF 85

86 DIFFERENTIATOR DIFFERENTIATOR 86

87 Differentiator 87

88 Differentiator 88

89 Differentiator Zero crossing Detector 89

90 PROBLEMS ON DIFFERENTIATOR PROBLEMS ON DIFFERENTIATOR 90

91 Problems on Differentiator Q1.a)Design a differentiator to differentiate an input signal that varies in frequency from 10HZ to about 1Khz. b)if a sine wave of 1V peak at 1000Hz is applied to the differentiator of part find V0 91

92 INSTRUMENTATION AMPLIFIER INSTRUMENTATION AMPLIFIER 92

93 INSTRUMENTATION AMPLIFIER 93

94 INSTRUMENTATION AMPLIFIER Instrumentation amplifier using transducer bridge 94

95 INSTRUMENTATION AMPLIFIER INSTRUMENTATION AMPLIFIER 95

96 Instrumentation amplifier 96

97 Instrumentation amplifier 97

98 AC AMPLIFIER AC AMPLIFIER 98

99 AC amplifier (a) AC Inverting Amplifier (b) AC Non Inverting Amplifier 99

100 AC amplifier V to I Converter: I to V Converter: 100

101 COMPARATORS COMPARATORS 101

102 Comparators Voltage comparator circuit: Voltage comparator is a circuit which compares two voltages and switches the output to either high or low state depending upon which voltage is higher. A voltage comparator based on opamp is shown here. Fig2.14 shows a voltage comparator in inverting mode and Fig shows a voltage comparator in non inverting mode. Circuit Diagram ofcomparator 102

103 Comparators Op-amp voltage comparator 103

104 Monostable Multivibrator Monostable Multivibrator 104

105 Monostable multivibrator MONOSTABLE MULTIVIBRATOR: The monostable multivibrator circuit using op-amp is shown in below fig(a). The diode D1 is clamping diode connected across C the diode clamps the capacitor voltage to 0.7volts when the ouput is at +Vsat. A narrow ve triggering pulse Vt is applied to the non-inverting input terminal through diode D2. To understand the operation of the circuit,let us assume that the output Vois at +Vsat that is in it s stable state. The diode D1 conducts and the voltage across the capacitor C that is Vc gets clamped to 0.7V. The voltage at the non-inverting input terminal is controlled by potentiometric divider of R1R2 to βvo that is +βvsat in the stable state. 105

106 Monostable multivibrator Monostable Multivibrator and input-output waveforms (a,b,c,d) 106

107 Astable Multivibrator ASTABLE MULTIVIBRATOR 107

108 Astable Multivibrator 108

109 Astable Multivibrator 109

110 WAVEFORM GENERATORS TRIANGULAR AND SQUARE WAVE GENERATORS 110

111 TRIANGULAR WAVE GENERATORS 111

112 SQUARE WAVE GENERATORS 112

113 Log Amplifier Logarithmic Amplifier 113

114 Logarithmic Amplifier An operational amplifier can be configured to function as a Logarithmic amplifier, or simply Log amplifier. Log amplifier is a non-linear circuit configuration, where the output is K times the logarithmic value of the input voltage applied. Log amplifiers find the applications in computations such as multiplication and division of signals, computation of powers and roots, signal compression and decompression, as well as in process control in industrial applications. A log amplifier can be constructed using a bipolar junction transistor in the feedback to the op-amp, since the collector current of a BJT is logarithmically related to its base-emitter voltage. 114

115 Logarithmic Amplifier 115

116 Logarithmic Amplifier The circuit of a fundamental log amplifier using op-amp is shown in the figure above. The necessary condition of the log amplifier to work is that the input voltage always must be positive. It can be seen that V out = V be. Since the the base collector terminal terminal is also of the grounded, transistor is held at virtual ground and becomes that of a diode and is given by, the voltage-current relationship I E = I S.[e q(vbe)/kt 1] Where, I S = the saturation current, k = Boltzmann s constant T = absolute temperature (in K) 116

117 Logarithmic Amplifier Since I E = I C for grounded base transistor, I C = I S. [e q(vbe)/kt 1] (I C /I S ) = [e q(vbe)/kt 1] (I C /I S ) + 1 = [e q(vbe)/kt ] (I C +I S )/I S = e q(vbe)/kt e q(vbe)/kt = (I C /I S ) since I C >> I S Taking natural log on both sides of the above equation, weget V be = (kt/q) ln[i C /I S ] The collector current I C = V in /R 1 and V out = -V be Therefore, V out = -(kt/q) ln[v in /R 1.I S ] 117

118 Anti log amplifiers. Anti-Logarithmic Amplifier or Exponential Amplifier 118

119 Anti log amplifiers. Anti-logarithmic or exponential amplifier (or simply antilog amplifier) is an op-amp circuit configuration, whose output is proportional to the exponential value or anti-log value of the input. Antilog amplifier does the exact opposite of a log amplifier. Antilog amplifiers along with log amplifiers are used to perform analogue computations on the input signals. The circuit of an antilog amplifier using op-amp is shown in the figurebelow. 119

120 Anti log amplifiers It is noted that by exchanging the positions of the transistor and the resistor, the log amplifier can be made to work as antilog amplifier. The base-collector voltage of the transistor is maintained at ground potential, from the virtual ground concept. The current I E for the transistor is given by, I E = I S.[e q(vbe)/kt 1] For a grounded base transistor, I E = I C. Therefore, I C = I S.[e q(vbe)/kt 1] Where, I S = saturation current of the transistor, V out = I C.R 1 V out = I S.[e q(vbe)/kt 1].R 1 Also, for the above circuit V in = -V be. Therefore, V out = R 1.I S.[e q(-v in )/kt 1] 120

121 Problems on log and antilog Problems on log and antilog 121

122 Problems on log and antilog Q1. Calculate the base voltage of Q 2 transistor in the log-amp using two op-amps? 122

123 Problems on log and antilog Q2.The input voltage, 6v and reference voltage, 4 v are applied to a log-amp with saturation current and temperature compensation. Find the output voltage of the log-amp? 123

124 Unit-3 ACTIVE FILTERS AND TIMERS 124

125 Active Filters Active Filters: Classification of filters 125

126 Active Filters Active filters: An electric filter is often a frequency-selective circuit that passes a specified band of frequencies and blocks or attenuates signals of frequencies outside this band. Filters may be classified in a number of ways: 1. Analog or digital 2. Passive or active 3. Audio (AF) or radio frequency (RF) 126

127 Active Filters The most commonly used filters are : Low-pass filter High-pass filter Band-pass filter Band-reject filter All-pass filter 127

128 Active Filters FIRST-ORDER LOW-PASS BUTTER WORTH FILTER 128

129 Active Filters According to the voltage-divider rule, the voltage at the non-inverting terminal across capacitor is 129

130 Active Filters 130

131 Active Filters FIRST-ORDER HIGH-PASS BUITERWORTH FILTER 131

132 For the first-order high-pass filter of Figure 8-6(a), the output voltage is Active Filters For the first-order high-pass filter of Figure 8-6(a), the output voltage is 132

133 Active Filters Hence the magnitude of the voltage gain is 133

134 Active Filters SECOND-ORDER LOW-PASS BUTTER WORTH FILTER 134

135 Active Filters 135

136 Active Filters 136

137 Active Filters Second-order filters are important because higher-order filters can be designed using them. The gain of the second-order filter is set by R1 and R F, while the high cutoff frequency f H is determined by R2, C2, R3, and C3, as follows: 137

138 Active Filters Second-order filters are important because higher-order filters can be designed using them. The gain of the second-order filter is set by R1 and R F, while the high cutoff frequency f H is determined by R2, C2, R3, and C3, as follows: 138

139 Active Filters 139

140 Active Filters SECOND-ORDER HIGH-PASS BUTTERWORTH FILTER 140

141 Active Filters As in the case of the first-order filter, a second-order high-pass filter can be formed from a second-order low-pass filter simply by interchanging the frequency-determining resistors and capacitors. Figure 8-8(a) shows the second-order high-pass filter. 141

142 Active Filters The voltage gain magnitude equation of the second-order high-pass filter is as follows: Where A F = = passband gain for the second-order Butterworth response f = frequency of the input signal (Hz) f L = low cutoff frequency (Hz) Since second-order low-pass and high-pass filters are the same circuits except that the positions of resistors and capacitors are interchanged, the design and frequency scaling procedures for the high-pass filter are the same as those for the low-pass filter. 142

143 Active Filters BAND-PASS FILTERS 143

144 Active Filters A band-pass filter has a passband between two cutoff frequencies f H and f L such that f H > f L. Any input frequency outside this passband is attenuated. Basically, there are two types of band-pass filters: Wide band pass, and Narrow band pass. Unfortunately, there is no set dividing line between the two. However, we will define a filter as wide band pass if its figure of merit or quality factor Q<10.On the other hand, if we will call the filter a narrow band-pass filter. Thus Q is a measure of selectivity, meaning the higher the value Q, the more selective is the filter or the narrower its bandwidth (BW). The relationship between Q, the 3-dB bandwidth, and the center frequency fc is given by 144

145 Active Filters 145

146 Narrow Band-Pass Filter Where A F is the gain at fc, given by The gain A F, however, must satisfy the condition This is accomplished simply by changing R 2 to R 2 sothat 146

147 Active Filters 2 nd order BAND - REJECT FILTERS 147

148 Active Filters Wide Band-Reject Filter Figure shows a wide band-reject filter using a low-pass filter, a high-pass filter, and a summing amplifier. To realize a band-reject response, the low cutoff frequency f L of the high- pass filter must be larger than the high cutoff frequency f H of the low-pass filter. In addition, the passband gain of both the high-pass and low-pass sections must be equal. The frequency response of the wide band-reject filter is shown in Figure. 148

149 Active Filters Narrow Band-Reject Filter 149

150 Active Filters ALL-PASS FILTER Where f is the frequency of the input signal in hertz. 150

151 Introduction555 Timer INTRODUCTION TO 555 TIMER 151

152 Introduction 555 Timer Pin diagram of 555Timer One of the most versatile linear integrated Block Diagram circuits is the 555 timer. A sample of these applications includes mono-stable and astable multivibrators, dc-dc converters, digital logic probes, waveform generators, analog frequency meters and tachometers, temperature measurement and control, infrared transmitters, burglar and toxic gas alarms, voltage regulators, electric eyes, and many others. 152

153 Introduction555 Timer FUNCTIONAL BLOCK DIAGRAM OF 555 TIMER 153

154 555 Timer 555 AS A MONOSTABLE MULTIVIBRATOR 154

155 555 Timer IC555 as monostable multivibrator 155

156 555 Timer Fig: Monostable Multivibrator with wave shaping network to prevent +ve pulse edge triggering 156

157 Monostable Applications Monostable applications 157

158 Monostable Applications Frequency divider The monostable multivibrator can be used as a frequency divider by adjusting the length of the timing cycle tp, with respect to the tine period T of the trigger input signal applied to pin 2. To use monostable multivibrator as a divide-by-2 circuit, the timing interval tp must be slightly larger than the time period T of the trigger input signal, as shown in Figure.By the same concept, to use the monostable multivibrator as a divide-by-3 circuit, tp must be slightly larger than twice the period of the input trigger signal, and so on. The frequency-divider application is possible because the monostable multivibrator cannot be triggered during the timing cycle. 158

159 Frequency divider 159

160 Monostable Applications Pulse stretcher: Monostable multivibrator as a Pulse stretcher Basic Monostable used as a pulse stretcher with an LED indicator at the output. The LED will be on during the timing interval tp = 1.1RAC, which can be varied by changing the value of RA and/or C. 160

161 555 As Astable operation Astable operation 161

162 Astable operation The 555 as an Astable Multivibrator, often called a free-running multivibrator, is a rectangular wave-generating circuit. Unlike the monostable multivibrator, this circuit does not require an external trigger to change the state of the output, hence the name free running. The 555 as a Astable Multivibrator (a)circuit(b)voltage across Capacitor and O/P waveforms. 162

163 Astable operation The time during which the capacitor charges from 1/3 V to 2/3 V. is equal to the time the output is high and is given by Similarly, the time during which the capacitor discharges from 2/3V to 1/3 V is equal to the time the output is low and is given by where RB is in ohms and C is in farads. Thus the total period of the output waveform is This, in turn, gives the frequency of oscillation as The duty cycle is the ratio of the time t during which the output is high to the total time period T. It is generally expressed as a percentage. In equation form, 163

164 Astable applications Astable applications 164

165 Astable applications Astable Multivibrator Applications: Square-wave oscillator: Free-running ramp generator: 165

166 Astable applications a) Free Running ramp generator (b) Output waveform. 166

167 Schmitt trigger Schmitt trigger 167

168 Schmitt trigger 555 Timer as Schmitt trigger 168

169 Schmitt trigger The input is given to the pin 2 and pin 6 which are tied together. Pins 4 and 8 are connected to supply voltage +Vcc. The common point of two pins 2 and 6 are externally biased at Vcc/2 through the resistance network R1 and R2. Generally R1=R2 to the gate biasing of Vcc/2.The upper comparator will trip at 2/3Vccwhile lower comparator at 1/3Vcc. The bias provided by R1 and R2 is centered within these two thresholds. Thus when sine wave of sufficient amplitude, greater than Vcc/6 is applied to the circuit as input, it causes the internal flip flop to alternately set and reset. Due to this, the circuit produces the square wave at the output. 169

170 Introduction to PLL Introduction to PLL, block schematic diagram 170

171 Introduction to PLL Block Schematic and Operating Principle 171

172 Introduction to PLL The phase-locked loop principle has been used in applications such as FM (frequency modulation) stereo decoders, motor speed controls, tracking filters, frequency synthesized transmitters and receivers, FM demodulators, frequency shift keying (FSK) decoders, and a generation of local oscillator frequencies in TV and in FM tuners. Today the phase-locked loop is even available as a single package, typical examples of which include the Signetics SE/NE 560 series (the 560, 561, 562, 564, 565, and 567). However, for more economical operation, discrete ICs can be used to construct a phase- locked loop. 172

173 Description of individual blocks Principles and description of individual blocks 173

174 Description of individual blocks Phase detector: A double-balanced mixer is a classic example of an analog phase detector. On the other hand, examples of digital phase detectors are these: Exclusive-OR phase detector Edge-triggered phase detector Monolithic phase detector (such as type 4044) 174

175 Description of individual blocks Exclusive-OR phase detector (a) Exclusive-OR phase detector: connection and logic diagram. (b) Input and output waveforms. (c) Average output voltage versus phase difference between fin and fout curve. 175

176 Description of individual blocks Principles and description of individual blocks 176

177 Description of individual blocks Low-pass filter: The function of the low-pass filter is to remove the high-frequency components in the output of the phase detector and to remove highfrequency noise. 177

178 Description of individual blocks Voltage-controlled oscillator: A third section of the PLL is the voltage-controlled oscillator. The VCO generates an output frequency that is directly proportional to its input voltage. Typical example of VCO is Signetics NE/SE 566 VCO, which provides simultaneous square wave and triangular wave outputs as a function of input voltage. The frequency of oscillations is determined by three external R1 and capacitor C1 and the voltage VC applied to the control terminal 5. VCO Block Diagram 178

179 565 PLL MONOLITHIC PHASE LOCK LOOP IC

180 565 PLL Monolithic PLLs are introduced by signetics as SE/NE 560 series and by national semiconductors LM 560 series. Pin configuration of IC

181 565 PLL Block Diagram of IC

182 UNIT- 4 DATA CONVERTERS 182

183 DATA CONVERTERS DATA CONVERTERS&Need of Data Converters 183

184 DATA CONVERTERS: Introduction Introduction In electronics a digital to analog converter is a system that converts a digital signal into analog signal. An analog to digital converter is a system that converts a analog signal into digital signal. 184

185 DATA CONVERTERS Classification of ADCs Direct type ADC. Integrating type ADC Direct type ADCs Flash (comparator) type converter Counter type converter Tracking or servo converter. Successive approximation type converter 185

186 DATA CONVERTERS Integrating type converters An ADC converter that perform conversion in an indirect manner by first changing the analog I/P signal to a linear function of time or frequency and then to a digital code is known as integrating type A/D converter 186

187 Need of Data Converters 187

188 DAC Techniques DAC Techniques-Weighted resistor DAC, R-2R ladder DAC 188

189 DAC Techniques Weighted resistor DAC R-2R ladder DAC Inverted R-2R ladder DAC IC 1408 DAC 189

190 DAC Techniques Weighted Resistor DAC V ref V 1 V 2 R 2R I Rf V 3 4R - + V out V n 2 n-1 R 190

191 DAC Techniques 191

192 IC 1408 DAC & Inverted R-2R DAC IC 1408 DAC & Inverted R-2R DAC 192

193 IC 1408 DAC & Inverted R-2R DAC Inverted R-2R DAC 193

194 IC 1408 DAC & Inverted R-2R DAC IC 1408 DAC 194

195 IC 1408 DAC & Inverted R-2R DAC IC 1408 DAC Specifications: Resolution Non-linearity or Linearity Error Gain error and Offset Error Settling Time 195

196 IC 1408 DAC & Inverted R-2R DAC IC 1408 DAC Applications Microcomputer interfacing CRT Graphics Generation Programmable Power Supplies Digitally controlled gain circuits Digital Filters 196

197 DAC characteristics and specifications DAC Characteristics and specifications 197

198 DAC characteristics and specifications DAC characteristics Resolution Reference Voltage Speed Settling Time Linearity 198

199 DAC characteristics and specifications Resolution The change in output voltage for a change of the LSB. Related to the size of the binary representation of the voltage. (8-bit) Higher resolution results in smaller steps between voltage values 199

200 DAC characteristics and specifications Reference Voltage Multiplier DAC Reference voltage is a constant set by the manufacturer Non-Multiplier DAC Reference voltage is variable Full scale Voltage Slightly less than the reference voltage (V ref -V LSB ) 200

201 DAC characteristics and specifications Speed Also called the conversion rate or sampling rate rate at which the register value is updated For sampling rates of over 1 MHz a DAC is designated as high speed. Speed is limited by the clock speed of the microcontroller and the settling time of the DAC 201

202 DAC characteristics and specifications Settling Time Time in which the DAC output settles at the desired value ± ½ V LSB. Faster DACs decrease the settling time 202

203 DAC characteristics and specifications Linearity Represents the relationship between digital values and analog outputs. Should be related by a single proportionality constant. (constantslope) 203

204 DAC characteristics and specifications ADC Techniques Flash ADC Sigma-delta ADC Dual slope converter Successive approximation converter 204

205 Successive Approximation ADC Successive Approximation ADC 205

206 Successive Approximation ADC A Successive Approximation Register (SAR) is added to the circuit Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the MSB and finishing at the LSB. The register monitors the comparators output to see if the binary count is greater or less than the analog signal input and adjusts the bits accordingly 206

207 Successive Approximation ADC 207

208 Successive Approximation ADC Advantages Capable of high speed and reliable Medium accuracy compared to other ADC types Good tradeoff between speed and cost Capable of outputting the binary number in serial (one bit at a time) format. 208

209 Successive Approximation ADC Disadvantages Higher resolution successive approximation ADC s will be slower Speed limited to ~5Msamples/s 209

210 FLASH CONVERTER,ADC CHARACTERISTICS FLASH CONVERTERS & ADC CHARACTERISTICS 210

211 FLASH CONVERTER,ADC CHARACTERISTICS FLASH CONVERTERS Consists of a series of comparators, each one comparing the input signal to a unique reference voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which produces a binary output 211

212 FLASH CONVERTER,ADC CHARACTERISTICS FLASH CONVERTERS 212

213 FLASH CONVERTER,ADC CHARACTERISTICS FLASH CONVERTERS As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The priority encoder generates a binary number based on the highestorder active input, ignoring all other active inputs. 213

214 FLASH CONVERTER,ADC CHARACTERISTICS FLASH CONVERTERS -Advantages Simplest in terms of operational theory Most efficient in terms of speed, very fast limited only in terms of comparator and gate propagationdelays Disadvantages Lower resolution Expensive For each additional output bit, the number of comparators is doubled i.e. for 8 bits, 256 comparators needed 214

215 FLASH CONVERTER,ADC CHARACTERISTICS ADC characteristics Resolution Accuracy Sampling rate Aliasing 215

216 FLASH CONVERTER,ADC CHARACTERISTICS Resolution The resolution of the converter indicates the number of discrete values it can produce. It is usually expressed in bits. For example, an ADC that encodes an analogue input to one of 256 discrete values has a resolution of 2 8 eight bits, since = 256. Resolution can also be defined electrically, and expressed in volts. 216

217 FLASH CONVERTER,ADC CHARACTERISTICS Accuracy Accuracy depends on the error in the conversion. If the ADC is not broken, this error has two components: quantization error and (assuming the ADC is intended to be linear) non-linearity. These errors are measured in a unit called the LSB, which is an abbreviation for least significant bit. In the above example of an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%. 217

218 FLASH CONVERTER,ADC CHARACTERISTICS Sampling rate The analogue signal is continuous in time and it is necessary toconvert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analogue signal. The rate of new values is called the sampling rate or sampling frequency of the converter. 218

219 FLASH CONVERTER,ADC CHARACTERISTICS Aliasing If the digital values produced by the ADC are, at some later stage in the system, converted back to analogue values by a digital to analogue converter or DAC, it is desirable that the output of the DAC be a faithful representation of the original signal. If the input signal is changing much faster than the sample rate, then this will not be the case, and spurious signals called aliases will be produced at the output of the DAC. The frequency of the aliased signal is the difference between the signal frequency and the sampling rate. 219

220 UNIT-5 DIGITAL IC APPLICATIONS 220

221 Introduction to Digital IC s Introduction to Digital IC s 221

222 Introduction to Digital IC s, Logic delays, TTL/CMOS interfacing CLASSIFICATION OF IC S: Based on mode of operation Linear IC s Digital IC s Linear IC s: Linear IC s are equivalents of discrete transistor networks, such as amplifiers, filters, frequency multipliers, and modulators that often require additional external components for satisfactory operation. Digital IC s: Digital IC s are complete functioning logic networks that are equivalents of basic transistor logic circuits. 222

223 Introduction to Digital IC s CLASSIFICATION OF DIGITAL INTEGRATED CIRCUIT Classification of ICs based on complexity Small Scale Integration or (SSI) Medium Scale Integration or (MSI) Large Scale Integration or (LSI) Very-Large Scale Integration or (VLSI) Super-Large Scale Integration or (SLSI) Ultra-Large Scale Integration or (ULSI) 223

224 Logic delay, TTL/CMOS interfacing CMOS DRIVING TTL AND CMOS DRIVING TTL Interfacing a CMOS to a TTL under 5Volts power supply 224

225 Logic delay, TTL/CMOS interfacing Interfacing ICs with different power supply voltages: Interfacing a CMOS to a TTL with different power supply voltages 225

226 Logic delay, TTL/CMOS interfacing Interfacing a TTL to a CMOS with different power supply voltages 226

227 Adders Adders 227

228 Adders The Half Adder 228

229 Adders 229

230 Adders The Full Adder: 230

231 Adders 231

232 Adders TYPES OF ADDERS Binary Parallel Adder Ripple carry adder The Look-Ahead Carry Adder Serial Adder 232

233 Multiplexers and De-multiplexers Multiplexers and De-multiplexers 233

234 Multiplexers and Demultiplexers Multiplexer: Multiplexer is a digital switch. it allows digital information from several sources to be routed onto a single output line 4*1 Mux 234

235 Multiplexers and Demultiplexers 4 : 1 MUX 235

236 Multiplexers and Demultiplexers Applications of multiplexer: The logic function generator Digital counter with multiplexeddisplays Data selection and data routing Parallel to serial conversion 236

237 De multiplexer Multiplexers an.d Demultiplexers A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital output lines. A demultiplexer of outputs has n select lines, which are used to select which output line to send the input. A demultiplexer is also called a data distributor. 2 n 237

238 Multiplexers and Demultiplexers Applications of Demultiplexer: Data distributor Security monitoring system Synchronous data transmissionsystem 238

239 Multiplexers and Demultiplexers. 239

240 Multiplexers and Demultiplexers 240

241 Decoders and Encoder Decoders and Encoder 241

242 Decoders and Encoder Decoders The decoder is an electronic device that is used to convert digital signal to an analogue signal. It allows single input line and produces multiple output lines. The decoders are used in many communication projects that are used to communicate between two devices. The decoder allows N- inputs and generates 2 power N-numbers of outputs. For example, if we give 2 inputs that will produce 4 outputs by using 4 by 2 decoder. 242

243 Decoders and Encoder 2-to-4 line Decoder In this type of encoders and decoders, decoders contain two inputs A0, A1, and four outputs represented by D0, D1, D2, and D3. As you can see in the truth table for each input combination, one output line is activated. 243

244 Decoders and Encoder 3 : 8 Line Decoder 244

245 Decoders and Encoder Encoder: An encoder is multiple input and multiple output combinational circuit it performs reverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output 4 : 2 Encoder 4 : 2 Encoder Truth Table 245

246 Decoders and Encoder 8 : 3 Priority Encoder 8 : 3 Priority Encoder Truth Table 246

247 Decoders and Encoder Priority Encoder A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number ofoutputs. The output of a priority encoder is the binary representation of the original number starting from zero of the most significant input bit. They are often used to control interrupt requests by acting on the highest priority encoder. 247

248 Decoders and Encoder 4 : 2 Encoder 248

249 SR, JK, T, and D flip-flops SR, JK, T, and D flip-flops 249

250 SR, JK, T, and D flip-flops RS Flip-flop: 250

251 SR, JK, T, and D flip-flops Operation: 1. When CP=0 the output of N3 and N4 are 1 regardless of the value of S and R. This is given as input to N1 and N2. This makes the previous value of Q and Q unchanged. 2.When CP=1 the information at S and R inputs are allowed to reach the latch and change of state in flip-flop takes place. 3. CP=1, S=1, R=0 gives the SET state i.e., Q=1, Q =0. 4. CP=1, S=0, R=1 gives the RESET state i.e., Q=0, Q =1. 5. CP=1, S=0, R=0 does not affect the state of flip-flop. 6.CP=1, S=1, R=1 is not allowed, because it is not able to determine the next state. This condition is said to be a race condition. 251

252 SR, JK, T, and D flip-flops - SR FF 252

253 SR, JK, T, and D flip-flops JK flip-flop (edge triggered JK flip-flop) 253

254 SR, JK, T, and D flip-flops - JK FF 254

255 SR, JK, T, and D flip-flops Operation: When J=0, K=0 then both N3 and N4 will produce high output and the previous value of Q and Q retained as it is. When J=0, K=1, N3 will get an output as 1 and output of N4 depends on the value of Q. The final output is Q=0, Q =1 i.e., reset state When J=1, K=0 the output of N4 is 1 and N3 depends on the value of Q. The final output is Q=1 and Q =0 i.e., set state When J=1, K=1 it is possible to set (or) reset the flip-flop depending on the current state of output. If Q=1, Q =0 then N4 passes 0 to N2 which produces Q =1, Q=0 which is reset state. When J=1, K=1, Q changes to the complement of the last state. The flip-flop is said to be in the toggle state. 255

256 SR, JK, T, and D flip-flops D flip-flop: 256

257 SR, JK, T, and D flip-flops Operation: When the clock is low both the NAND gates (N1 and N2) are disabled and Q retains its last value. When clock is high both the gates are enabled and the input value at D is transferred to its output Q. D flip-flop is also called Dataflip-flop. 257

258 SR, JK, T, and D flip-flops T flip-flop: If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previousvalue. Symbol for T flip-flop 258

259 SR, JK, T, and D flip-flops Truth table T FF 259

260 Synchronous counters Synchronous counters 260

261 Synchronous counters Counters Counter number is a device which stores (and sometimes displays) the of relationship to a clock signal. times particular event or process has occurred, often in A Digital counter is a set of flip flops whose state change in response to pulses applied at the input to the counter. Counters may be asynchronous counters or synchronouscounters. Asynchronous counters are also called ripple counters 261

262 Synchronous counters Asynchronous counters are serial counters. They are slow because each FF can change state only if all the preceding FFs have changed their state. If the clock frequency is very high, the asynchronous counter may skip some of the states. This problem is overcome in synchronous counters or parallelcounters. Synchronous counters are counters in which all the flip flops are triggered simultaneously by the clock pulses. Synchronous counters have a common clock pulse applied simultaneously to all flip-flops. 262

263 Synchronous counters 2-Bit Synchronous Binary Counter 263

264 Asynchronous counters Decade counter Asynchronous counters Decade counter 264

265 Asynchronous counters Decade counter An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0). This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0 265

266 Asynchronous counters Decade counter Two-bit ripple up-counter using negative edge triggered flip flop: 266

267 Asynchronous counters Decade counter Two-bit ripple down-counter using negative edge triggered flip flop: 267

268 Asynchronous counters Decade counter A decade counter is one of which goes through 10 unique combinations of output and then reset as the clock proceeds. We may use some sort of feedback in 4 bit binary counter to skip any six of the sixteen possible output state from 0000 to 1111 to get decade counter. A decade counter does not necessarily count from 0000 to 1001, it could count as 0000,0001,0010,1000,1010,1011,1110,0000,0001, and so on. 268

269 Asynchronous counters Decade counter Design of a decade or mod-10 asynchronous counter using T-flipflops: 269

270 Asynchronous counters Decade counter Truth table for Mod-10 Counter 270

271 Shift registers, Universal shift registers Shift registers, universal shift registers 271

272 Shift registers, universal shift registers Shift registers: In digital circuits, a shift register is a cascade of flip-flops sharing the same clock, in which the output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, at each transition of the clock input 272

273 Shift registers, universal shift registers Types of shift registers. Serial in, serial out, shift right, shift registers Serial in, serial out, shift left, shift registers Parallel in, serial out shift registers Parallel in, parallel out shift registers 273

274 Shift registers, universal shift registers Serial IN, serial OUT, shift right, shift left register: 274

275 Shift registers, universal shift registers Serial-in, parallel-out, shift register: 275

276 Shift registers, universal shift registers Applications of shift register: Delay line parallel to serial converter Serial to parallel converter Sequence generator Shift register counters 276

277 Shift registers,universal shift registers. Shift registers, universal shift registers 277

278 Shift registers, universal shift registers Parallel-in, parallel-out, shift register 278

279 Shift registers, universal shift registers Parallel In - Serial Out Shift Registers 279

280 Shift registers, universal shift registers Bidirectional shift register: A bidirectional shift register is one which the data bits can be shifted from left to right or from right to left. 280

281 Ring counters and Johnson counters Ring counters and Johnson counters 281

282 Ring counters and Johnson counters Shift register counters: One of the applications of shift register is that they can be arranged to form several types of counters. The most widely used shift register counter is ring counter as well as the twisted ring counter. Types of shift register counters Ring counter Johnson counters 282

283 Ring counters and Johnson counters Ring counter 283

284 Ring counters and Johnson counters Ring Counter Timing Diagram 284

285 Ring counters and Johnson counters Twisted Ring counter (Johnson counter): 285

286 Ring counters and Johnson counters Johnson Counter Timing Diagram 286