A 3.8 Gb/s LARGE-SCALE MIMO DETECTOR FOR 3GPP LTE-ADVANCED

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1 2014 IEEE Inernaional Conference on Acousic, Speech and Signal Processing (ICASSP) A 3.8 Gb/s LARGE-SCALE MIMO ETECTOR FOR 3GPP LTE-AVANCE Bei Yin 1, Michael Wu 1, Guohui Wang 1, Chris ick 2, Joseph R. Cavallaro 1, and Chrisoph Suder 3 1 Rice Universiy, Houson, TX; {by2, mb2, gh, cavallar}@rice.edu 2 Xilinx, San Jose, CA; chrisd@xilinx.com 3 Cornell Universiy, Ihaca, NY; suder@cornell.edu ABSTRACT This paper proposes o he bes of our knoledge he firs ASIC design for high-hroughpu daa deecion in single carrier frequency division muliple access (SC-FMA)-based large-scale MIMO sysems, such as sysems building on fuure 3GPP LTE-Advanced sandards. In order o subsanially reduce he complexiy of linear sof-oupu daa deecion in sysems having hundreds of anennas a he base saion (BS), he proposed deecor builds upon a runcaed Neumann series expansion o compue he necessary marix inverse a lo complexiy. To achieve high hroughpu in he 3GPP LTE-A uplink, e develop a sysolic VLSI archiecure including all necessary processing blocks. We presen a corresponding ASIC design ha achieves 3.8 Gb/s for a 128 anenna, 8 user 3GPP LTE-A based large-scale MIMO sysem, hile occupying 11.1 mm 2 in a TSMC 45 nm CMOS echnology. Index Terms Large-scale (or massive) MIMO, linear sof-oupu deecion, Neumann series, ASIC design Large-scale MIMO 1. INTROUCTION Large-scale (or massive) MIMO posulaes he use of anenna arrays having hundreds of anennas a he base saion (BS), hile serving ens of users simulaneously and in he same frequency band [2]. This echnology promises significan improvemens in erms of specral efficiency, link reliabiliy, and coverage over convenional (small-scale) MIMO sysems [2 5]. The benefis of large-scale MIMO, hoever, come a he cos of significanly increased compuaional complexiy a he BS compared o small-scale MIMO sysems (e.g., sysems equipped ih six or feer anennas). In addiion, cellular sysems, such as 3GPP LTE [6] or LTE Advanced (LTE-A) [7], rely on single carrier frequency division muliple access (SC-FMA) hich furher increases he dimensionaliy of he underlying deecion problem. Hence, opimal deecion mehods, such as maximum-likelihood (ML) deecion [8] or sof-oupu sphere decoding (S) [9, 10], An exended version of his paper deailing an FPGA design ill appear in [1]. This ork as suppored in par by he US Naional Science Foundaion under grans CNS , ECCS , and CNS hose compuaional complexiy scales exponenially in he number of ransmi sreams [11, 12] resul in prohibiive complexiy. Consequenly, lo-complexiy (bu sub-opimal) deecion schemes [3] ha scale favorably o he highdimensional deecion problems faced in SC-FMA-based large-scale MIMO sysems are necessary in pracice Conribuions We propose o he bes of our knoledge he firs applicaion specific inegraed circui (ASIC) for he uplink in SC- FMA-based large-scale MIMO sysems, i.e., here muliple users communicae ih he BS. To significanly reduce he compuaional complexiy of linear sof-oupu deecion, e build our deecor upon he runcaed Neumann series expansion mehod for approximae maxxrix inversion developed in [13, 14]. We presen a corresponding sysolic VLSI archiecure ha is able o achieve high hroughpu a lo silicon area, even for very large BS anenna arrays. The resuling ASIC design for a TSMC 45 nm CMOS echnology achieves a peak uplink hroughpu of 3.8 Gb/s in a 128 anenna, 8 user scenario, exceeding he 1.5 Gb/s peak uplink rae specified in LTE-A operaing a 100 MHz bandidh [7]. 2. APPROXIMATE SOFT-OUTPUT ETECTION IN THE LARGE-SCALE MIMO LTE-A UPLINK 2.1. SC-FMA uplink model We consider an SC-FMA-based large-scale muli-user MIMO uplink ih B anennas a he BS communicaing ih U B single-anenna users. The i h user firs maps he coded bi sream ono consellaion poins in a finie alphabe O (such as QPSK or 16-QAM) ih average poer of E s per symbol. A discree Fourier ransform (FT) block hen ransforms each L group of consellaion poins, x (i) = [ x (i) 1,..., ] T x(i) L, ino FT modulaed symbols s (i) = [ s (i) 1,..., ] T s(i) L. These symbols are mapped ono L daa-carrying subcarriers and ransmied by he user. A he BS, he received symbols in he frequency domain on he h subcarrier are modeled as y = H s + n. Here, he vecor y = [ y (1),..., y (B) ] T conains symbols received a he base-saion anennas on he h subcarrier /14/$ IEEE 3907

2 The vecor s = [ s (1),..., s (U) ] T conains he symbols ransmied by he users simulaneously on he h subcarrier. The B U marix H conains he channel gains beeen he receive anennas and ransmi anennas on he h subcarrier, and n = [ n (1),..., n (B) ] T models hermal noise a he h subcarrier in he frequency domain. The enries of he vecor n are assumed o be i.i.d. zero-mean complex Gaussian random variables ih variance N 0 per complex enry Linear sof-oupu MMSE deecion To arrive a lo compuaional complexiy for daa deecion in SC-FMA-based large-scale MIMO sysems, e focus on linear sof-oupu deecion. Linear sof-oupu deecion for SC-FMA mainly consiss of he folloing o seps: (i) channel equalizaion o generae esimaes of he frequency domain symbols, and (ii) sof-oupu compuaion o generae LLRs from he equalized frequency domain symbols. For channel equalizaion, e apply a minimum-mean square error (MMSE) equalizer on a per-subcarrier basis in he frequency domain. To reduce he amoun of recurren compuaions [15], e firs compue he machedfiler (MF) oupus as y MF = H H y and he Gram marices G = H H H for each subcarrier, folloed by forming he regularized Gram marix A = G +N 0 E 1 s I U. The equalized symbols per subcarrier are compued as ŝ = A 1 hich requires an U U-dimensional marix inversion; his inversion causes mos of he deecor s complexiy. For sof-oupu compuaion, e model he esimaed h y MF, symbol ransmied from he i h user as ˆx (i) = µ (i) x (i) + e (i), here µ (i) is he effecive channel gain and e (i) is he posequalizaion noise-plus-inerference ih variance νi 2. By defining ρ 2 i = ( µ (i)) 2 /ν 2 i as he pos-equalizaion signal-onoise-plus-inerference raio (SINR) and b as he bi index of he LLR associaed ih he h symbol ransmied from he i h user, e can compue he max-log LLRs as [15] L (i) (b) = ρ 2 i min a O 0 b ˆx (i) µ a (i) 2 min a O 1 b µ ˆx (i) a (i) 2, (1) here Ob 0 and O1 b correspond o he ses of consellaion symbols for hich he b h bi equals o 0 and 1, respecively Approximae MMSE deecion via Neumann series For SC-FMA-based large-scale MIMO sysems ih a large number of users U, compuaion of he inverse A 1 can resul in significan compuaional complexiy. Hence, o reduce he complexiy of compuing he inverse A 1, e use he folloing Neumann series expansion [16]: A 1 = n=0 ( X 1 (X A ) ) n X 1. (2) By decomposing A such ha A = + E, here is he main diagonal of A and E is he hollo regularized BLER SNR[dB] B=64, K=1 B=64, K=2 B=64, K=3 FP B=64, K=3 B=64, exac B=128, K=1 B=128, K=2 B=128, K=3 FP B=128, K=3 B=128, exac Fig. 1. Block error-rae (BLER) performance for U = 4 single-anenna users; FP indicaes fixed-poin performance. Gram marix, e can approximae he inverse A 1 by keeping only he firs K erms of he Neumann series [13, 14] à 1 K = K 1 n=0 ( 1 E ) n, (3) hich can be compued a (ofen significanly) loer compuaional complexiy han an exac inverse for K 3. Compuaion of he max-log LLRs (1) using (3) is carried ou by replacing he exac inverse A 1 by he approximaion. Wih his approximaion, he effecive channel gain à 1 K µ (i) K and he variance of he residual pos-equalizaion NPI variance ν i 2 K no depend on he number of Neumann series erms. To reduce complexiy, e propose o use he effecive channel gain and residual pos-equalizaion NPI variance of he 1-erm approximaion. Wih his approximaion, he effecive frequency domain channel gain a he h subcarrier for he K erm approximaion is given by H 1 = H H H. Furher, by exploiing properies of he IFT, he ime domain channel gain of he i h user is µ (i) K = L 1 L =1 h (i,i) 1, here h (i,i) K is he ih diagonal enry of H 1. We also approximae he noise-plus-inerference variance as follos: Here, d (i,i) ν 2 i E s L =1 (d(i,i) ) 1 g (i,i) E s µ (i) 1 2. (4) is he i h diagonal enry of G. Noe ha he NPI approximaion (4) performs almos equally ell as using he exac NPI variance. is he i h diagonal enry of, and g (i,i) 2.4. Simulaion resuls To characerize he performance of he proposed algorihms, e consider modulaion and coding scheme (MCS) 28 ih a bandidh of 20 MHz and 1200 daa carrying subcarriers, as specified by he LTE sandard [6]; his mode corresponds o 64-QAM, and a rae 0.75 urbo code. The channel marices are generaed using he WINNER-Phase-2 model [17], here e use a linear anenna array ih spacing of 10 m/ m, similar o he channel measuremen 3908

3 campaign in [18]. A he BS, e perform exac as ell as approximae sof-oupu MMSE deecion. We furhermore use a log-map LTE urbo decoder performing 16 (full-)ieraions. Figure 1 shos he block-error rae (BLER) performance of he proposed approximae deecion algorihm compared o ha of an exac MMSE deecor for U = 4. The proposed mehod ih K = 3 approaches he performance of he exac deecor, bu a significanly loer compuaional complexiy Archiecure overvie 3. VLSI ARCHITECTURE The proposed VLSI archiecure is illusraed in Fig. 2. The deecor consiss of hree main unis: (i) he preprocessing uni, (ii) he subcarrier processing uni, and (iii) he user processing uni. The preprocessing uni performs mached filering y MF = H H y and compues he regularized Gram marix A as ell as he corresponding (approximae) marix inversion in (3). These resuls, along ih inermediae values and G, are hen passed o he subcarrier processing uni. This uni performs equalizaion, i.e., compues ŝ = à 1 K ymf and he pos-equalizaion SINR a each subcarrier. Since daa deecion is carried ou for each user, a daa buffer is required o conver all equalized symbols and SINR values from a per-subcarrier basis o a per-user basis. The user processing uni convers he equalized symbols for each user ino he ime domain using an IFFT block and generaes sof-oupu informaion in he form of max-log LLRs using he buffered pos-equalizaion NPI values. We noe ha he preprocessing uni operaes a symbol rae as channel esimaes may change from symbol o symbol in LTE sysems [19]. To mee he LTE-A peak hroughpu, e use muliple insances of he preprocessing uni. We nex provide he deails for he o mos crucial blocks. The archiecures of he remaining blocks are sraighforard Approximae marix inversion uni Figure 2 shos he riangular sysolic array used for compuing he Gram marix and he K-erm Neumann series approximaion. The sysolic array consiss of o processing elemens (s): s on he diagonal of he sysolic array (-) and s on he off-diagonal (-O). Boh s have differen modes in he four compuaion phases summarized nex. Firs phase: This phase firs compues he U U regularized Gram marix A = G + N 0 Es 1 I U as ell as using reciprocal unis (denoed by inv in Fig. 2) in he - unis. Since A is diagonally dominan ih diagonal values close o B, e miigae dynamic-range issues by he scale don uni. The resuls and E are sored in disribued regiser files for he subsequen phases. Second phase: The sysolic array compues E using and E obained in he firs phase. Since he marix E is no Hermiian, he sysolic array compues he upper- and loer-riangular par of E separaely. As is diagonal, compuaion of E only requires a series of scalar muliplicaions. Third phase: The sysolic array compues he 2-erm Neumann series approximaion: à 1 2 = 1 E. Since E is Hermiian, only he loerriangular par needs o be compued. Furhermore, since is diagonal, compuaion of E only requires enry-ise muliplicaions. The compuaion is carried ou by loading and E ino all s and performing scalar muliplicaions. We hen add o he resul in he diagonal and sore he resul E in he disribued regiser files. Fourh phase: In his phase, he sysolic array ieraively compues a K-erm Neumann series approximaion using he (K 1)-erm approximaion residing in he disribued regiser files. The sysolic array performs a marix muliplicaion of E ih à 1 K 1 and hen, adds 1 o he diagonal. The resuling K-erm approximaion à 1 K is hen sored in he regiser files. Since e can repea his phase for a configurable number of ieraions, e can compue an arbirary K-erm approximaion ih he same sysolic array IFFT and LLR compuaion uni In order o ransform he per-subcarrier daa ino he user (or ime) domain, e use an IFFT o suppor 3GPP LTE [6] sandard. The core suppors he ransform size of L = 2 x 3 y 5 z, hich consiss of Radix-2, Radix-3, and Radix-5 operaions. The IFFT uni reads and oupus complex daa in serial manner, and achieves a hroughpu ell-beyond 1.9 Gb/s for 8 users, 64-QAM, and 100 MHz bandidh. The LLR compuaion uni compues (1) given he effecive channel gains µ (i) from he IFFT block and he pos-equalizaion SINR values ρ 2 i obained from he SINR block. Since LTE specifies Gray mappings for all modulaion schemes, LLR compuaion is accomplished a lo complexiy (see [15] for he deails). A single insance of his uni is able o processes one symbol every clock cycle, resuling in a hroughpu of 6 Gb/s for 64-QAM hen running a 1 GHz. 4. ASIC IMPLEMENTATION 4.1. Fixed-poin design parameers The proposed design is implemened ih fixed-poin arihmeic o minimize he hardare complexiy and o maximize he hroughpu. The channel marices H, receive vecors y, mached filer oupus y MF, approximae inverses à 1 K, and he Gram marices G, are represened by 15 bi for real and imaginary pars, respecively. All muliplier unis use 22 bi precision, excep in he FFT uni, hich uses 18 bi precision. To reduce he size of he daa buffer, e quanize is conens o 12 bi. The inpus and oupus of he IFFT and of he LLR compuaion uni use 12 bi. The negligible BLER 3909

4 y Mached filer MF y H 1 A Gram N 1 0 & Inverse, G Equalizer SINR sˆ aa buffer, 2 1 i i Preprocessing Subcarrier processing User processing () sˆ i IFFT () xˆ i LLR () i L ( b) U O Gram & Inverse - a b MAC Scale don 1 NE 0 s Inv g d O O U Fig. 2. High-level VLSI archiecure of he approximae MIMO deecor for large-scale 3GPP LTE-A sysems. -O a b MAC Scale don g od Anenna configuraion Inversion algorihm Technology 128 BS anennas, 8 users K = 3 erm approximaion TSMC 45nm CMOS Max. clock frequency 1 GHz Throughpu 3.8 Gb/s Core area (uilizaion) 11.1 mm 2 (73 %) Cell area (excluding memories) 12.6 MGE Memory size (ROM & RAM) Kb Poer consumpion 8 1 GHz and 0.81 V Table 1. Pos-layou implemenaion resuls of he proposed approximae MIMO deecor for large-scale 3GPP LTE-A. Memory 1 Neumann series MIMO deecor core 1 Neumann series MIMO deecor core 2 Memory 2 performance loss resuling from fixed-poin precision arifacs is shon in Fig. 1. Fig. 3. ASIC layou of he dual-core large-scale MIMO deecor for 3GPP LTE-A in TSMC 45nm CMOS echnology 4.2. Implemenaion resuls Table 1 summarizes he key (pos-layou) characerisics of he implemened approximae MIMO deecor for large-scale 3GPP LTE-A in TSMC 45nm CMOS echnology. In order o mee he uplink hroughpu specified in 3GPP LTE-A for a 8 user, 128 BS anenna sysem, e need o insances of he deecor. Each deecor consiss of 8 preprocessing unis, 1 subcarrier processing uni, and 1 user processing uni. The layou of he resuling dual-core ASIC is shon in Fig. 3 and occupies a oal of 12.6 MGE and 11.1 mm 2. Noe ha all RAMs and ROMs (for he daa buffer, he IFFT s iddle facors, and he reciprocal unis) have been generaed using he ARM memory compiler [20]. The final design achieves a peak hroughpu of 3.8 Gb/s, hich exceeds he 1.5 Gb/s peak daa rae of LTE-A ih 4 users and 100 MHz bandidh, as i suppors daa deecion for up o 8 users communicaing concurrenly and in he same frequency band. To he bes of our knoledge, here are no exising largescale MIMO deecor designs for LTE-A. Exising LTE uplink deecors [21 25] are designed for small-scale MIMO sysems and are, hence, significanly less complex, hich prohibis a fair comparison o our ASIC design. We emphasize ha our design demonsraes he feasibiliy of using largescale MIMO in fuure 3GPP LTE-A sandards, even hen having hundreds of anennas a he BS. The developmen of improved (e.g., non-linear) deecion mehods and corresponding VLSI/ASIC designs is par of on-going ork. 3910

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