A Low-Power Low-Cost 780MHz CMOS FSK Receiver for Short-Range Wireless Communication

Transcription

1 Chinese Journal of Electronics Vol.25, No.2, Mar A Low-Power Low-Cost 780MHz CMOS FSK Receiver for Short-Range Wireless Communication YIN Yadong 1, YANG Yuanting 2 and ZHANG Lihong 3 (1. College of Physics and Information Engineering, Fuzhou University, Fuzhou , China) (2. Fujian Polytechnic of Information Technology, Fuzhou , China) (3. Fujian Jiangxia University, Fuzhou , China) Abstract This paper presents a low-power low-cost 780MHz CMOS Frequency shift keying (FSK) receiver for short-range wireless communication. A current-reused Low power amplifier (LNA) and a single-balance passive mixer are employed to cut down the current consumption of the RF frontend in receiver. A 3 rd -order active-rc complex filter with reconfigurable bandwidth is implemented and a novel automatic tuning circuit is used in the filter to eliminate the negative effect of the Process, voltage, temperature (PVT) variations. A novel replica-circuit master-slave automatic tuning circuit and a discrete-time differentiator are employed in demodulator to keep the demodulation performances from the PVT variations and the frequency offset of Intermediate frequency (IF). The receiver is fabricated in 0.18µm CMOS and occupies a chip area of about 0.97mm 2. It can achieve a sensitivity of 83.7dBm and a tolerance of IF range from 1.5MHz to 3.7MHz with a 4.7mA current consumption under a 1.8V supply. Key words CMOS integrated circuit, Current reused, Frequency offset tolerance, Frequency shift keying (FSK) demodulation, Low power, Receiver. I. Introduction In recent years, the RF transceiver/receiver chip market has grown dramatically since the booming demands for the short-range wireless communication applications including Internet of things (IoTs), Wireless local area networks (WLANs), Wireless personal area networks (WPANs) and Wireless sensor networks (WSNs). These portable wireless communications always have strict constraints in power consumption, chip area and robust tolerances for PVT variations. FSK is a popular modulation scheme employed in the short-range wireless communication. Due to the constantenvelop property, FSK modulation requires less stringent linearity on the power amplifier in transmitter. Meanwhile, FSK demodulation can be implemented with a low IF receiver based on limiter and analog/mix-signal demodulator to cut down power consumption and chip area. As a coin has two sides, there are many challenges in FSK communication and the major is the performance degradation caused by the frequency offset between transmitter and receiver. In this paper, a low-power low-cost FSK receiver for short-range wireless communication is presented. It operates at MHz free China WSN frequency band and supports several reconfigurable data rates of 250kbps /500kbps/1Mbps/2Mbps with 3MHz IF. The receiver has been implemented in 0.18µm CMOS and verified through the measurements. Section II provides the architecture of the proposed receiver. Section III describes the circuit design of the building blocks in the receiver. Measurement results are discussed in Section IV. Finally, Section V concludes a summary. II. Architecture As is shown in Fig.1, the receiver is mainly composed of a current-reused LNA, a single-balance passive mixer, an image-reject complex filter, a limiter and a demodulator. The current consumed by the RF frontend generally comprising LNA and mixer dominates the total current of receiver. In this paper, the current reused technique has been employed in LNA to achieve high gain and low power, by stacking two amplifiers together vertically to Manuscript Received July 18, 2014; Accepted Aug. 30, This work is supported by the National Natural Science Foundation of China (No ). c 2016 Chinese Institute of Electronics. DOI: /cje

2 A Low-Power Low-Cost 780MHz CMOS FSK Receiver for Short-Range Wireless Communication 221 make them share a common bias current. The LNA output signal is AC-coupled fed to the single-balance passive mixer which mixes it with the Local oscillating (LO) signals from the outside PLL-based frequency synthesizer to obtain the quadrature baseband signals but consumes a little current. The complex filter lets the wanted signal pass but rejects the inherent image interferers. An automatic tuning circuit is attached to the filter to guarantee the filter performance constant under the PVT variations. The outputs of complex filter are AC-coupled fed to the limiters and then amplified to rail-to-rail level for demodulation. After several processes comprising zero-crossing detection, low-pass filtering and decision, the expected data is recovered from the IF signals by the demodulator ultimately. a novel pulse reshaper and a replica-circuit master-slave automatic calibration circuit are employed in demodulator to keep the pulse durations of zero-crossing detection output constant against the PVT variations, and a Discrete-time differentiator (DTD) is used to eliminate the negative effect of the frequency offset of LO signals between transmitter and receiver. Fig. 1. Architecture of the proposed FSK receiver III. Circuit Design 1. Current reused LNA and single-balance passive mixer Compared to the other blocks in the receiver, the RF frontend circuit contributes the most of power consuming and cost. In this paper, three methods including the single-end architecture of RF frontend, the current reuse technique and the passive-type mixer [1] are adopted to reduce the power and cost of the RF frontend effectively. The current-reused LNA, depicted in the Fig.2(a), seems to be a two-stage amplifier: the first stage amplifier, which is used to achieve low noise figure and input impedance matching, is an inductively degenerated cascade amplifier and mainly consists of the transistors M 1 and M 2. The second stage amplifier composed of the transistors M 3 and M 4 is an inverter-type amplifier stacked above the first stage to boost the gain and drive the following mixer directly without gain attenuation. The DC output of the second stage amplifier is fixed to the bias voltage V b3 through the Operational amplifier (Op-amp)-based negative feedback to abide low voltage headroom. A large bypass capacitor named C pd is added in LNA to provide a reliable AC ground. As the RF input signal has been amplified with enough gain in LNA, the conversion gain budget of mixer become insignificant, so a single-balance passive mixer with less gain but also less power compared with the active one can be used. As the Fig.2(b) shows, the single-balance passive mixer is mainly composed of the complementary switching transistor pairs marked as S 1 S 4. The second-order intermodulation (IM2) mainly caused by the self mixing of RF input signal, which will convert the RF interferers down to the baseband, is a noticeable issue [2].Itcanbe mitigated when the parameters of complementary transistors satisfy the formula as below [1] : μ n C ox W n L n = μ p C ox W p L p (1) where μ n C ox W n /L n and μ p C ox W p /L p is the transistor parameter of nmos and pmos in the switching pairs respectively. In Fig.2(b), the CMFB circuits are employed to provide appropriate bias voltages for the switching transistors, based on the common voltage of the mixer output. 2. Complex filter Fig.3 shows the 3 rd -order active-rc complex filter. It can be viewed as a low-pass filter, the certain frequency of which has been shift from zero to the IF in frequency spectrum [3], and this frequency-shift operation is completed by the interconnected resistors depicted in the dotted box of Fig.3(a). The filter is implemented based on the fully differential op-amps depicted in Fig.3(b), the capacitor tanks depicted in Fig.3(c), and the reconfigurable resistors. Reconfiguring those resistors harmonically can

3 222 Chinese Journal of Electronics 2016 Fig. 2. Schematics of the RF frontend. (a) Current-reused LNA; (b) Single-balance passive mixer Fig. 3. Schematics of complex filter with automatic tuning circuit. (a) Complex filter; (b) Fully differential op-amp; (c) Capacitor tank; (d) Automatic tuning circuit in filter achieve various bandwidths meanwhile keep the central frequency constant. The PVT variations will seriously make the resistance and capacitance in filter fluctuate and finally cause negative-effect on the gain, bandwidth and central frequency of the filter. To overcome it, the filter needs an automatic tuning circuit to detect and compensate these fluctuations [4,5]. In this paper, an automatic tuning circuit has been proposed and is depicted in Fig.3(d). As the figure shows, the digital controller compares the time constant τ of resistor R 3 and the capacitor tank, which is the replica of R I and the capacitor tank in filter respec-

4 A Low-Power Low-Cost 780MHz CMOS FSK Receiver for Short-Range Wireless Communication 223 tively, with T REF which is the period of the clock input CK REF. The comparison result is used to tune the capacitance of capacitor tank through regulating the value of CT[5 : 0]. If τ<t REF, the capacitance will be increased, or else, it will be decreased. Finally, τ can be expressed as: ( ) ( V dd τ = R 3 C t ln = R 3 C t ln 1+ R ) 2 T REF V dd V REF R 1 (2) where C t is the capacitance of capacitor tank. The output of digital controller D[5 : 0] is fed to the filter to make the capacitance of capacitor tanks in filter equal to the replica. When τ is close to T REF, and if the difference between the values of CT[5 : 0] and D[5 : 0] is larger than a preset threshold, D[5 : 0] will be updated to CT[5 : 0]. Due to directly inverse proportion to τ, the central frequency and bandwidth of the filter can be set to the expected through the automatic tuning. Compared with the states-of-the-art [4,5], this circuit does not need integrator, which means simpler and less power consumption. 3. Limiter & demodulator As depicted in Fig.4, the limiter consists of two single channels to suit for the quadrature architecture. Each channel is composed of three stage of amplifier: two front stages are formed by three cascading sub-stage amplifiers, and the hind one employs a differential buffer to make the output rail-to-rail. The AC-coupled capacitors are inserted between stages, as well as at the input, to eliminate the negative effect of the DC offset. In this paper, a novel architecture of FSK demodulatior is proposed to meet the requirements mentioned above. As Fig.1 shows, it consists of a Zero-crossing detector (ZCD), a pulse reshaper, a master-slave tuning circuit, a Low-pass filter (LPF), a Discrete-time differentiator (DTD) and a decision circuit. ZCD depicted in the Fig.5(a) is simply implemented with resistors, capacitors and logic gates. Both differential I and Q channel outputs of limiter are utilized to generate pulses, and then these pulses are combined together via a 4-input OR gate. The amplitude of the demodulated signal based on zero-crossing detection is obviously proportional to the frequency deviation of the original FSK modulation and the pulse duration of the ZCD output. It means that keeping pulse duration constant is critical during demodulation. In order to protect pulse duration from PVT variations, a replica-circuit master-slave automatic tuning circuit similar to the automatic tuning circuit in complex filter is utilized. Its schematic is depicted in Fig.5(b) and the operation principle can be derived from the timing diagram shown in Fig.6. The pulse reshaper output is filtered by a 4 th -order LPF and then fedtodtd,asdepictedinthefig.7. Fig. 5. (a) Zero-crossing detector; (b) Pulse reshaper with automatic calibration circuit Fig. 4. Schematics of limiter. (a) Limiter; (b) Sub-stage amplifier; (c) Differential buffer There are many kinds of all-analog or mixed-signal FSK demodulation technologies reported in recent years, such as phase-shift quadrature discriminator [6], delay line discriminator [7], time-to-digital conversion [8], zerocrossing detection [9], phase-domain ADC [10] and so on. Although those methods have their respective merits, they rarely can achieve low-cost, low-power, frequencyoffset and process-variation tolerance at the same time. The frequency offset of local oscillator between transmitter and receiver are a major issue in FSK system. It will be converted into DC fluctuation in most FSK demodulator which can degrade the demodulation performance greatly. In this paper, DTD is used to eliminate the effect of the frequency offset by cancelling the DC fluctuation with little power consumption. DTD is composed of a counter, two Analog multiplexers (AMUX), eight switched sample-and-hold capacitors marked as C 1 to C 8, and a programmable-gain fully-differential subtracter. The counter is driven by the sampling clock SCLK and its 3-bits outputs SD 1 and SD 2 are used for

5 224 Chinese Journal of Electronics 2016 h(z) = V DTD,DM(z) = R V (1 z 8 ) (4) V LPF (z) 2R C Its magnitude response can be given as H(ω) = R V R C (4 sin ω ) (5) f S where f S is the frequency of the sampling clock. The magnitude response of DTD exhibits a periodic band-pass property, the passband of which is proportional to f S,so the DC offset and low-frequency fluctuation component in V LPF will be attenuated appropriately. IV. Measurement Results Fig.8 shows the chip photo of the proposed FSK receiver integrated in a 0.18µmCMOSprocess,onwhichthe modules of the receiver, as well as other major circuits, are marked. The detail chip areas occupied are listed in Table 1 and the total area of receiver is about 0.97mm 2. Fig. 6. Timing diagram of the automatic calibration Fig. 8. The photo of the chip Fig. 7. (a) 4 th low-pass filter; (b) Discrete-time differentiator; (c) Decision circuit deciding which capacitor will be connected to the voltage input V LPF from the low-pass filter and the voltage output V AMUX, through AMUX U 1 and U 2 respectively. V AMUX subtracts V LPF in the subtracter, and the subtraction result V DTD is fed to the decision circuit depicted in Fig.7(c). The decision circuit compares V DTD with the threshold voltage V THH and V THL to create the final digital data D OUT. The differential-mode voltage of V DTD can be described as the below discrete-time formula: Table 1. Chip area and current consumption Chip area/mm 2 Current/mA LNA Mixer Complex filter Limiters Demodulator Total V DTD,DM (n) = R V 2R C (V LPF (n) V AMUX (n)) = R V 2R C (V LPF (n) V LPF (n 8)) (3) In z-domain, the transfer function of V DTD,DM vs. V LPF can be given as: Fig. 9. Measurement results of the complex filter The Fig.9 shows the measurement results of the complex filter. During measurement, four-channel quadrature signals were generated by using vector signal generator and then fed into the filter. One channel of the filter outputs was measured by using spectrum analyzer. As the figure shows, the central frequency was fixed at 3MHz and the bandwidth could be set to

6 A Low-Power Low-Cost 780MHz CMOS FSK Receiver for Short-Range Wireless Communication kHz/500kHz/1MHz/2MHz accurately. Through transposing the quadrature signals, the image rejection property has been measured. As the picture shows, the Image rejection rate (IRR) is more than 20dB. A series of FSK-modulated signals modulated by a 1Mb/s data frame with various IF frequencies had been generated to test the demodulation performance. The measurement results are presented in Fig.10, which shows that the circuit worked well and the recovered data was accurate enough to pass the Cyclic redundancy check (CRC) as IF was changed. The measurements mean that the IF frequency offset range which the demodulator can tolerant could achieve from 1.5MHz up to 3.7MHz. Fig.11 shows the measured BER property of the receiver versus the RF input power. The receiver was measured with 1Mb/s data streams, and can achieve a sensitivity of 83.7dBm at 0.1% BER derived from the picture. The current consumptions of each sub-circuit are also listed in Table 1 and the total current consumption of receiver is about 4.7mA under a 1.8V supply voltage. Table 2 summarizes the measured performance of the proposed receiver and the comparison with the states-of-theart. As the table shows, our design has a much more robust tolerance of frequency offset and obvious advantages in chip area and power consumption. Table 2. Performance summary and comparison Ref.[6] Ref.[8] Ref.[11] This work Tech./µm Area/mm Freq./GHz Sen./dBm Date Rate/bps 1M 1M 1M 1M Freq. Off. Tole. vs /MHz ±0.6 ± IIR/dB >20 Current/mA Only the chip area and the current of the receiver are considered. Fig. 10. Demodulation measurements with different IF. (a) with 3.7MHz IF; (b) with 1.5MHz IF V. Conclusion A low-power low-cost 780MHz CMOS FSK receiver for short-range wireless communication fabricated in 0.18µm CMOS is presented. A RF frontend composed of a current-reused LNA and a single-balance passive mixer is used to cut down the current consumption. A reconfigurable 3 rd -order active-rc complex filter with automatic tuning circuit is implemented to obtain various bandwidths with a fixed IF. The novel replica-circuit masterslave automatic tuning circuit and discrete-time differentiator are employed in demodulator to keep the performance of demodulator from the process variation and the frequency offset. The receiver occupies a chip area of about 0.97mm 2 and can achieve a sensitivity of 83.7dBm with a 4.7mA current consumption under a 1.8V supply. With the novel architecture, it can tolerate an IF range from 1.5MHz upward to 3.7MHz. References Fig. 11. Measured BER of receiver vs. the RF input power [1] YIN Yadong, ZHANG Lihong and YAN Yuepeng, A 780MHz low-power fully integrated CMOS receiver front-end for wireless sensor network, Chinese Journal of Electronics, Vol.21, No.2, pp , [2] Behzad Razavi, RF Microelectronics, Tsinghua University Press, Beijing, China, pp , [3] Ahmed A. Emira and Edgar Sanchez-Sinencio, A pseudo differential complex filter for bluetooth with frequency tuning, IEEE Trans Circuits Syst. II, Vol.50, No.10, pp , [4] Bo Xia, Shouli Yan and Edgar Sanchez-Sinencio, An RC time constant auto-tuning structure for high linearity continuoustime ΣΔ modulators and active filters, IEEE Trans Circuits Syst. I, Vol.51, No.11, pp , [5] Dingkun Du, Yongming Li, Zhihua Wang and Seeteck Tan, An active-rc complex filter with mixed signal tuning system for low-if receiver, APCCAS, Singapore, pp , [6] B.-Y. Chi, J.-K. Yao, P. Chiang and Z.-H. Wang, A 0.18µm CMOS GFSK analog front end using a Bessel-based quadrature discriminator with on-chip automatic tuning, IEEE Trans Circuits Syst. I, Reg. Papers, Vol.56, No.11, pp , [7] C.C. Lai, et al., A 0.5V GFSK 200µW limiter/demodulator with bulk-driven technique for low-if bluetooth, Solid-State Circuits Conf (A-SSCC), Kobe, Japan, pp , 2012.

7 226 Chinese Journal of Electronics 2016 [8] C.P. Chen, et al., A low-power 2.4-GHz CMOS GFSK transceiver with a digital demodulator using time-to-digital conversion, IEEE Trans Circuits Syst. I, Reg. Papers, Vol.56, No.12, pp , [9] P.P. Chen, et al., A low-power robust GFSK demodulation technique for WBAN applications, Proc. BioCAS, Rotterdam, Netherlands, pp , [10] J. Masuch and M.D. Restitto, A 190µW zero-if GFSK demodulator with a 4-b phase-domain ADC, IEEE J. Solid-State Circuits, Vol.47, No.11, pp , [11] S. Byun, C.H. Park and Y. Song, A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator, IEEE J. Solid-State Circuits, Vol.38, No.10, pp , YIN Yadong was born in He received the B.S. degree from the Department of Electrical Engineering of Beijing Jiaotong University, Beijing, China, in 2003, and the Ph.D. degree from the Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China. In 2009, he joined the Electronics System Technology Laboratory of the Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China. Since 2015, he has been with the College of Physics and Information Engineering, Fuzhou University, Fuzhou, China, as an associate research fellow. His current research interests include CMOS RF integrated circuit, wireless microimplantable system and ultra low-power wireless system. ( yatn@163.com) YANG Yuanting was born in He is now a professor of Fujian Polytechnic of Information Technology, Fuzhou, China. His research interests include advanced electronic system, communication and network technology. ZHANG Lihong was born in She is now an instructor of Fujian Jiangxia University, Fuzhou, China. Her current research interests include VLSI design and embedded system design.