A Low-Power All-Digital GFSK Demodulator with Robust Clock Data Recovery

Transcription

1 A Low-Power All-Digital GFSK Demodulator with Robust Clock Data Recovery ABSTRACT Pengpeng Chen Rong Luo This paper presents an all-digital Gaussian frequency shift keying (GFSK) demodulator with robust clock data recovery (CDR) for low-intermediate-frequency (low-if) receivers in wireless sensor networks (WSN). The proposed demodulator can detect and adapt to the intermediate frequency of the received signal automatically. In addition, the CDR can tolerate the frequency deviation of the input clock. An implementation of the demodulator with CDR is realized with HJTC 0.18 µm CMOS technology. The chip is designed for GFSK signals with a center frequency of 200 khz, a modulation index of 1 and a data rate of 100 kbps. Experimental results show that the chip consumes 0.53 ma from a 1.8 V power supply, and only a 11 db input signal to noise ratio (SNR) is required for 10 3 bit error rate (BER). The tolerance range for IF offset is ±12.5% at 11 db input SNR, and the CDR can tolerate frequency deviation of the input clock of ±0.1%. Categories and Subject Descriptors B.7.1 [Hardware]: INTEGRATED CIRCUITS Types and Design Styles General Terms Design This work was supported by China Postdoctoral Science Foundation(2011M500308). Bo Zhao is the corresponding author. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. GLSVLSI 12, May 3 4, 2012, Salt Lake City, Utah, USA. Copyright 2012 ACM /12/05...$ Bo Zhao zhao_bo@mail.tsinghua.edu.cn Huazhong Yang yanghz@tsinghua.edu.cn Keywords GFSK demodulator, low-if receiver, IF offset tolerance 1. INTRODUCTION Wireless sensor networks consist of a large number of lowcost micro-sensor nodes. WSN nodes are battery-powered, so low power consumption is very important to ensure a long life time of the sensor nodes. In addition, the power consumption of the transceiver is the largest in a WSN node. Therefore simple modulation schemes such as GFSK are often adopted. There has been a lot of research about receivers. Low-IF receivers are widely used in low power applications because of their high integration level, simpleness and low power consumption [12], [8], [6]. Because there is no information in the amplitude for GFSK signals, the low-if receiver can use limiting amplifiers instead of voltage controlled amplifiers (VGAs) and analog-to-digital converters (ADCs) to save power [2], as shown in Fig.1. The limiting amplifiers keep only zero-crossing information, which can be used to realize the demodulation with a digital, analog or mixedsignal demodulator. There are large IF offsets in low-if receivers caused by the leakage of RF signals or carrier signals. For demodulators in low-if receivers, the tolerance of IF offsets is an important factor that affects the performance of the whole transceiver. In recent years, mainly five methods are proposed to realize GFSK demodulation: 1) IF differentiator based method: Analog time-domain IF differentiator and mixer can realize frequency discrimination [5]. However, to determine the IF differentiator s center frequency, resisters and capacities which have large process induced variations are used. These variations result in DC components in the baseband which seriously depress the demodulator s performance. 2) Zerocrossing detection method: Generating pulses at zero-crossing points can demodulate the GFSK signal [13], [10]. A capacitance is used to decide the width of the pulses [13], while the capacitance has large process induced variations which make the pulse width inaccurate [14]. 3) Quadrature Dis- 123

2 Mixer Complex Filter Limiter IF detector synchronization detection LNA 0 90 PLL Limiter GFSK Dem Limiting amplified signal change dem-if demodulate according to dem-if data_noclk change index P data decision data_out data_out_clk Mixer Our work Demodulator CDR Figure 1: Block diagram of a low-if Receiver. criminator Based Method: Double the frequency of the input GFSK signal is used as a clock of a delay circuit to sample the GFSK signal [11]. Unfortunately, the Sallen-Key filter, which is used to turn a square wave into a sine wave, consumes a large amount of power. The work in [4] uses a Bessel low-pass filter to realize 90 delay and frequencyto-voltage transformation, but a PLL which increases power consumption severely is needed to tune the time constant of the filter to predefined values. 4) DLL based method: A delay-locked loop (DLL) and a replica delay line are adopted to realize GFSK demodulation and IF offset cancelation [1], but it can not be used in situations where the GFSK signal s frequency deviation is larger than half of the intermediate frequency. 5) TDC based method: The time-to-digitalconverter (TDC) based method has no need for a DLL so as to save power and chip area [2]. Nevertheless, it needs a high intermediate frequency, 5 MHz in [9] and 6 MHz in [2], which means a large gain-bandwidth product for amplifiers in the complex filter and more power consumption. Moreover, because of the thermometer-coded output, a large number of delay cells and D flip-flops, which consume a lot of power, are needed to achieve a good accuracy for the GFSK cycle period. In this paper, we present a low-power all-digital GFSK demodulator with robust CDR. The contributions of this paper can be summarized into the following aspects: A low-power all-digital GFSK demodulator with CDR. An all-digital demodulator with automatic IF correction. An all-digital CDR with clock deviation tolerance. The rest of our paper is organized as follows. Section II describes the digital demodulator with automatic IF correction and the robust CDR in detail. Section III gives an implementation and the experimental results. Section IV concludes the paper. 2. ALL-DIGITAL DEMODULATOR WITH ROBUST CDR The flow of our proposed digital demodulator with robust CDR is shown in Fig.2. The demodulator realizes frequency-to-voltage conversion and automatic IF correction. The CDR outputs the digital data from the baseband wave data out clk. When there is a rising edge in data out clk, data is outputted in data out. 2.1 All-Digital Demodulator Fig.3 shows the flow of the proposed digital demodula- Figure 2: Block diagram of the proposed all-digital GFSK demodulator with CDR. tor. The demodulator is designed for GFSK signals with intermediate frequency F c, frequency deviation F s and data rate F d. The input is a digital clock with a frequency of f o and the limiting amplified GFSK signal. The output is the demodulated signal data noclk. There are two functions that the demodulator realizes, which are described as follows: 1) Frequency to voltage conversion. The modulated signal is sampled by the input clock and accumulated. The space between two adjacent edges is shown by the number of clock periods. When the intermediate frequency is F c, the space between two adjacent edges is f o/2f c. So if the current space between two adjacent edges is smaller than f o/2f c, the current frequency is higher than F c, then the output signal data noclk is high. Or else, the data noclk is low. In fact, the current space between two adjacent edges is inversely proportional to the current frequency, so we can determine by how much the current frequency varies from the intermediate frequency. It can be seen that the signal is demodulated according to the signal s intermediate frequency. We call the intermediate frequency adopted by the demodulator dem-if. If dem-if and the input signal s intermediate frequency is not the same, there is IF offset, and the performance of the demodulation above will decrease. 2) Automatic IF correction. In our demodulator, the IF offset tolerance is realized by choosing a different dem-if. When the demodulator is receiving a signal, the demodulator can output the baseband signal, and detect the widest spaces and the narrowest spaces at the same time. If the input signal s intermediate frequency is F c and frequency deviation is F s, then the smallest space between two adjacent edges is f o/2(f c + F s) clock periods, and the largest space is f o/2(f c F s) clock periods. Firstly, we set the dem-if F c for example. If the detected space is smaller than f o/2(f c + F s), then the intermediate frequency of the input signal is larger than dem-if, the dem-if should be increased. If the detected space is larger than f o/2(f c F s), the dem-if should be reduced. Considering the affect of noise, a threshold M thrsd is defined. If the number of spaces larger than f o/2(f c F s) reaches the threshold before the number of spaces smaller than f o/2(f c + F s), the dem-if should be reduced and the number of wider and narrower spaces are counted from zero again. If the number of spaces larger than f o/2(f c F s) reaches the threshold after the number of spaces smaller than f o/2(f c + F s), the dem-if should be increased and the number of wider and narrower spaces are counted from zero again. 124

3 data_noclk P point to data_temp[x] every f 0 /F d periods Output 1 counter >0 Output 0 midnum > counter-midnum midnum < counter-midnum x+n > f o /F d -1? x-n < 0? x = x+n-f o /F d, output the data in out_temp x = x+n x = x-n x = f o /F d +x-n do not output next symbol Figure 4: Flow of CDR. It can be seen that the signal s intermediate frequency is tracked automatically and the tolerance of IF offset can be very large as long as the range of the dem-if for the demodulator is increased. increase Fc < f 0/(2(F c + F s)) M small = M small+1 M small = M thrsd? data_noclk high limiting amplified signal dem-if = Fc detect spaces > f 0/(2F c)? M small = 0, M large = 0 data_noclk low reduce Fc > f 0/(2(F c -F s)) M large = M large+1 M large = M thrsd? Figure 3: Flow of the proposed demodulator. 2.2 Robust CDR Due to the affect of noise and the resolution of the digital clock, the duty cycle of data noclk is not accurate, so a CDR is needed to get the digital information from data noclk. The flow of the proposed CDR is shown in Fig.4. To store one bit of data (one symbol) in the sampled data noclk, a f o/f d bits shift register named out temp is used. The data in the register moves 1 bit left every clock and data noclk is inputted into the right bit. An index P is used to point to a position x, i.e. out temp[x] in the register where to start counting the symbol. The moving step of the index P is set N. For every f o/f d clock periods, the data in out temp[x] is cumulated (plus 1 when out temp[x] ishighandminus1 when out temp[x] islow.). Thesumofout temp[x] inthe first f o/2f d clock periods is got and named midnum, and the sum of out temp[x] inthef o/f d clock periods is got and named counter. The midnum and counter are initially set to 0 before the start of every f o/f d periods. The CDR realizes symbol synchronization and tolerance of clock deviation: 1) Symbol synchronization. At the end of every f o/f d clock periods, if counter is larger than 0, the previous one symbol is 1. Then, if midnum is smaller than counter midnum, the number of zeros in the first f o/2f d periods is larger than the zeros in the second f o/2f d periods. That means x should be reduced to x N to make the startcumulate point coincide with the start of symbols. If midnum is larger than counter midnum, x should be increased to x + N. Ifcounter is smaller than 0, the previous symbol is 125

4 Table 1: Parameter setting of the digital demodulator. dem-if (khz) f o/2(f c + F s) f o/2f c f o/2(f c F s) For the situation that the previous symbol is 0, the flow is shown in Fig.4. 2) Tolerance of clock deviation. There may be frequency deviation for the clock signal. In our CDR, the frequency deviation of the clock is tolerated by the circulating movement of index P. Assuming that x is the start of the current symbol and the frequency of the clock is higher than the ideal clock, then the start of next symbol will be smaller than x and x should be reduced. So x will keep getting smaller as long as the frequency of the clock is higher than the ideal clock. If x N is smaller than 0, the next symbol will be counted at out temp[f o/f d + x N]. Because the symbol in the register out temp is already outputted, there will be no output data for next f o/f d periods. If the frequency of the clock is lower than the ideal clock, x will keep getting larger. If x + N is larger than f o/f d 1, the next symbol is counted at out temp[x + N f o/f d ]. Because the symbol in out temp is still not outputted, the data in out temp will be outputted first before the data in the next f o/f d periods. The tolerance range of clock frequency deviation depends on the moving step N of P. We know that x will keep getting smaller (larger) as long as the frequency of the clock is higher (lower) than the ideal clock. Additionally, larger frequency deviation of the clock means that larger changing speed of x is needed. So large N can realize a good CDR frequency tracking capability, but makes the resolution of the startcumulate point poor. If the frequency of the provided clock is relatively stable and accurate, then N should be set to a small number to get a good resolution of the start-cumulate point. N can be made programmable in the design. In fact, the clock is usually provided by a crystal oscillator, and the frequency of the crystal oscillator usually has high accuracy. So we prefer to set N to a small number. The latency of the digital CDR loop is f o/f d clock periods, i.e. a bit of data. Large latency ensures good CDR jitter/noise tolerance performance. 3. EXPERIMENTAL RESULTS The demodulator with CDR is realized using the verilog- HDL language and is implemented with HJTC 0.18um CMOS technology. The chip is designed for GFSK signals with an intermediate frequency of 200 khz, frequency deviation of 50 khz and a data rate of 100 kbps. The input clock is 20 MHz. 5 dem-ifs are implemented in the demodulator. The corresponding f o/2f c, f o/2(f c + F s)andf o/2(f c F s)are shown in Table 1. The relation between bit error rate (BER) and SNR is measured and shown in Fig.5. For 0.1% BER, only 11 db SNR is required. Fig.6 compares the measure result of the demodulator with automatic IF correction and without automatic IF correction. Because the dem-if range of the designed demodulator is 180 khz to 220 khz, the IF cover- BER BER SNR (db) Figure 5: Measured BER vs. SNR. With automatic IF correction Without automatic IF correction IF (khz) Figure 6: Measured BER vs. IF offset at 11dB SNR. 126

5 Table 2: Performance Comparison. References CMOS Technology Frequency Data Rate SNR IF Offset Tolerance Power Consumption (µm) (Hz) (b/s) (db) (mw) [11], M 1M % 6 [9], M 1 M/250 k 14.9/7.4 7%/-12% +9% 3.6 a [3], M N/A % 2.64 [7], M 0.1to2.0M 16.0 N/A 0.81 a This work k 100 k % b 0.95 a a The power consumption includes CDR. b The demodulator is measured at 11 db input SNR to get the IF offset tolerance. Figure 7: Die Photo. ing range of the demodulator is -12.5% +12.5% (180 khz to 220 khz). It shows that our method can tolerate IF offset effectively. The moving step N is set to 10 and the tolerance range of the clock frequency is -0.1% +0.1% (19.98 MHz MHz).The die photo of the chip is shown in Fig.7. Table 2 summarizes the demodulator s performance and lists the comparison of different IF circuits. It shows that the proposed demodulator has excellent IF offset tolerance and relatively low power consumption. In our design, a large part of power is consumed by the CDR circuit due to the use of the large register out temp. Infact,out temp can be made much smaller considering the effect of N, and thus the power consumption can be reduced further more. Whereas, acompletef o/f d bits shift register out temp ensures a more stable CDR performance. In our design, we adopted the complete f o/f d bits shift register out temp. 4. CONCLUSION A new kind of GFSK demodulator with CDR is presented in this paper. The proposed automatic IF correction method can realize ultra large IF offset tolerance. The CDR can tolerate frequency deviation of the clock. An implementation is realized with HJTC 0.18um CMOS technology. The chip consumes 0.53 ma from a 1.8 V power supply. Only 11 db SNR is required for 0.1% BER. The IF offset tolerance is ±12.5% at 11 db SNR, and the CDR can tolerate ±0.1% clock frequency. 5. REFERENCES [1] S. Byun, C.-H. Park, Y. Song, S. Wang, C. Conroy, and B. Kim. A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. IEEE Journal of Solid-State Circuits, 38(10): , [2] C.-P. Chen, M.-J. Yang, H.-H. Huang, T.-Y. Chiang, J.-L. Chen, M.-C. Chen, and K.-A. Wen. A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(12): , [3] Y.-C. Chen, Y.-C. Wu, and P.-C. Huang. A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver. In IEEE Custom Integrated Circuits Conference, pages , [4] B.Chi,J.Yao,P.Chiang,andZ.Wang.A0.18-µm CMOS GFSK Analog Front End Using a Bessel-Based Quadrature Discriminator With On-Chip Automatic Tuning. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(11): , [5] H. Darabi, S. Khorram, B. Ibrahim, M. Rofougaran, and A. Rofougaran. An IF FSK demodulator for Bluetooth in 0.35 µm CMOS.In IEEE Conference on Custom Integrated Circuits, pages , [6] B. Guthrie, J. Hughes, T. Sayers, and A. Spencer. A CMOS gyrator low-if filter for a dual-mode Bluetooth/ZigBee transceiver. IEEE Journal of Solid-State Circuits, 40(9): , [7] D. Han and Y. Zheng. A Mixed-Signal GFSK Demodulator Based on Multithreshold Linear Phase Quantization. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(9): , [8] H. Jeong, B.-J. Yoo, C. Han, S.-Y. Lee, K.-Y. Lee, S. Kim, D.-K. Jeong, and W. Kim. A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture. IEEE Journal of Solid-State Circuits, 42(6): , [9] H.-S. Kao, M.-J. Yang, and T.-C. Lee. A Delay-Line-Based GFSK Demodulator for Low-IF Receivers. In IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pages , [10] E. Lee. Zero-crossing baseband demodulator. In Sixth IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, volume 2, pages , [11] T.-C. Lee and C.-C. Chen. A mixed-signal GFSK demodulator for Bluetooth. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(3): , [12] A. Maxim, R. Poorfard, R. Johnson, P. Crawley, 127

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