24 GHz to 44 GHz, Wideband, Microwave Downconverter ADMV1014. Data Sheet FUNCTIONAL BLOCK DIAGRAM FEATURES APPLICATIONS GENERAL DESCRIPTION

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1 Data Sheet GHz to GHz, Wideband, Microwave Downconverter ADMV FEATURES Wideband RF input frequency range: GHz to GHz downconversion modes Direct conversion from RF to baseband I/Q Image rejecting downconversion to complex IF LO input frequency range:. GHz to. GHz LO quadrupler for up to GHz Matched Ω, single-ended RF input, and complex IF outputs Option between matched Ω balanced or Ω singleended LO inputs Ω balanced baseband I/Q output impedance with adjustable output common-mode voltage level Image rejection optimization Square law power detector for setting mixer input power Variable attenuator for receiver power control Programmable via a -wire SPI interface -terminal, mm mm LGA package APPLICATIONS Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE) SEN I_N I_P IF_I GND IF_Q Q_P Q_N FUNCTIONAL BLOCK DIAGRAM SDI SCLK DVDD VCC_MIXER GND LO_P LO_N GND ADMV VCC_QUAD BG_RBIAS RST VCC_BG 9 VCC_LNA_P GND RF_IN DET GND SDO VCC_IF_BB VDET VCC_VGA GND VCTRL VCC_VVA VCC_LNA_P - Figure. GENERAL DESCRIPTION The ADMV is a silicon germanium (SiGe), wideband, microwave downconverter optimized for point to point microwave radio designs operating in the GHz to GHz frequency range. The downconverter offers two modes of frequency translation. The device is capable of direct quadrature demodulation to baseband inphase (I)/quadrature (Q) output signals, as well as image rejection downconversion to a complex intermediate frequency (IF) output carrier frequency. The baseband outputs can be dc-coupled, or, more typically, the I/Q outputs are ac-coupled with a sufficiently low high-pass corner frequency to ensure adequate demodulation accuracy. The serial port interface (SPI) allows fine adjustment of the quadrature phase to allow the user to optimize I/Q demodulation performance. Alternatively, the baseband I/Q outputs can be disabled, and the I/Q signals can be passed through an on-chip active balun to provide two single-ended complex IF outputs anywhere between MHz and MHz. When used as an image rejecting downconverter, the unwanted image term is typically suppressed to better than dbc below the wanted sideband. The ADMV offers a flexible local oscillator (LO) system, including a frequency quadruple option allowing up to a GHz range of LO input frequencies to cover a radio frequency (RF) input range as wide as GHz to GHz. A square law power detector is provided to allow monitoring of the power levels at the mixer inputs. The detector output provides closed-loop control of the RF input variable attenuator through an external op amp error integrator circuit option. The ADMV downconverter comes in a compact, thermally enhanced, mm mm LGA package. The ADMV operates over the C to + C case temperature range. Rev. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel:.9. Analog Devices, Inc. All rights reserved. Technical Support

2 ADMV TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Serial Port Register Timing... Absolute Maximum Ratings... Thermal Resistance... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... 9 I/Q Mode... 9 IF Mode... Output Detector Performance... Return Loss... M N Spurious Performance... Theory of Operation... Start-Up Sequence... Baseband Quadrature Demodulation (I/Q Mode)... Data Sheet Image Rejection Downconversion... 9 Detector... 9 LO Input Path... 9 Power-Down... 9 Serial Port Interface (SPI)... Applications Information... Error Vector Magnitude (EVM) Performance... Baseband Quadrature Demodulation to Very Low Frequencies... Performance at Different Quad Filter Settings... VVA Temperature Compensation... Performance Between Differential vs. Single-Ended LO Input... Performance across RF Frequency at Fixed IF and Baseband Frequencies... Recommended Land Pattern... Evaluation Board Information... Register Summary... Register Details... Outline Dimensions... Ordering Guide... REVISION HISTORY / Revision : Initial Version Rev. Page of

3 Data Sheet ADMV SPECIFICATIONS RF amplitude = dbm, measurements performed with a mv dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB =. V, DVDD = VCC_VVA =. V, Register xb set to xc, Register x, Bits[:] set to, and ambient temperature (TA) = C, unless otherwise noted. Measurements are in IF mode, performed with a 9 hybrid, Register x, Bit =, and Register x, Bit =, unless otherwise noted. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) =. V, Register x, Bit =, and Register x, Bit =, unless otherwise noted. Table. Parameter Test Conditions/Comments Min Typ Max Unit FREQUENCY RANGES RF Input GHz LO Input.. GHz LO Quadrupler. GHz IF Output.. GHz Baseband (BB) I/Q Output DC. GHz LO AMPLITUDE RANGE + dbm I/Q DEMODULATOR PERFORMANCE Conversion Gain At maximum gain GHz to GHz. db GHz to GHz. db Voltage Variable Attenuator (VVA) Control Range 9 db Single Sideband (SSB) Noise Figure At maximum gain GHz to GHz. db GHz to GHz. db Input Third-Order Intercept (IP) At maximum gain GHz to GHz dbm GHz to GHz dbm Input Second-Order Intercept (IP) GHz to GHz, at maximum gain dbm Input db Compression Point (PdB) At maximum gain GHz to GHz dbm GHz to GHz dbm Amplitude Balance ±. db Phase Balance DC < baseband frequency (fbb) < GHz Degrees GHz < fbb < GHz Degrees GHz < fbb < GHz Degrees Image Rejection GHz to GHz, at maximum gain Uncalibrated dbc Calibrated dbc IF DOWNCONVERTER PERFORMANCE Conversion Gain At maximum gain GHz to GHz. db GHz to GHz. db VVA Control Range 9 db SSB Noise Figure At maximum gain GHz to GHz. db GHz to GHz. db Input IP At maximum gain GHz to GHz dbm GHz to GHz. dbm Rev. Page of

4 ADMV Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit Input PdB At maximum gain GHz to GHz 9 dbm GHz to GHz dbm Amplitude Balance. db Phase Balance MHz < IF frequency (fif) < GHz. Degrees GHz < fif < GHz Degrees GHz < fif < GHz. Degrees Image Rejection Uncalibrated dbc Calibrated dbc RECEIVER (Rx) POWER DETECTOR PERFORMANCE Input Level ± db dynamic range Minimum dbm Maximum dbm ± db Dynamic Range db Output Voltage Maximum DC Output. V RETURN LOSS RF Input Ω single-ended db LO Input Ω differential db IF Output Ω single-ended db BB Output Ω differential db BB I/Q Output Impedance Ω LEAKAGE At maximum gain Fundamental LO to RF dbm LO to RF dbm Fundamental LO to IF dbm Fundamental LO to I/Q dbm LOGIC INPUTS Input Voltage Range High, VINH DVDD.. V Low, VINL. V Input Current, IINH/IINL µa Input Capacitance, CIN pf LOGIC OUTPUTS Output Voltage Range High, VOH DVDD.. V Low, VOL. V Output High Current, IOH µa POWER INTERFACE VCC_IF_BB, VCC_VGA, VCC_LNA_P, VCC_MIXER,... V VCC_BG, VCC_QUAD. V Supply Current ma DVDD, VCC_VVA...9 V. V Supply Current. ma VCC_LNA_P... V. V Supply Current ma Total Power Consumption. W Power-Down 9 mw Rev. Page of

5 Data Sheet ADMV SERIAL PORT REGISTER TIMING Table. Parameter Description Min Typ Max Unit tsdi, SETUP Data to clock setup time ns tsdi, HOLD Data to clock hold time ns tsclk, HIGH Clock high duration to % tsclk, LOW Clock low duration to % tsclk, SEN_SETUP Clock to SEN setup time ns tsclk, DOT Clock to data out transition time ns tsclk, DOV Clock to data out valid time ns tsclk, SEN_INACTIVE Clock to SEN inactive ns t SEN_INACTIVE Inactive SEN (between two operations) ns Timing Diagram SCLK t SCLK, LOW t SCLK, HIGH t SCLK, SEN_SETU P t SEN_INACTIVE SEN SDO t SCLK, DOT t SCLK, DOV t SCLK, SEN_INACTIVE SDI t SDI, SETUP Figure. Serial Port Register Timing Diagram t SDI, HOLD - Rev. Page of

6 ADMV ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage VCC_IF_BB, VCC_VGA, VCC_LNA_P,. V VCC_MIXER, VCC_BG, VCC_QUAD, DVDD VCC_VVA, VCC_LNA_P. V RF Input Power dbm LO Input Power 9 dbm Maximum Junction Temperature C Maximum Power Dissipation.9 W Lifetime at Maximum Junction Temperature (TJ) hours Operating Case Temperature Range C to + C Storage Temperature Range C to + C Lead Temperature (Soldering sec) C Moisture Sensitivity Level (MSL) Rating MSL Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) V Field Induced Charged Device Model V (FICDM) The maximum power dissipation is a theoretical number calculated by (TJ C)/θJC_TOP. Based on IPC/JEDEC J-STD- MSL classifications. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Data Sheet THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θja is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θjc is the junction to case thermal resistance. Table. Thermal Resistance Package Type θja θjc_top θjb ΨJT ΨJB Unit CC C/W The thermal resistance values specified in Table are simulated based on JEDEC specifications, unless specified otherwise, and must be used in compliance with JESD-. θja is the junction to ambient thermal resistance in a natural convection, JEDEC environment. θjc_top is the junction to case (top) JEDEC thermal resistance. θjb is the junction to board JEDEC thermal resistance. ΨJT is the junction to top JEDEC thermal characterization parameter. ΨJB is the junction to board JEDEC thermal characterization parameter ESD CAUTION Rev. Page of

7 Data Sheet ADMV PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADMV TOP VIEW (Not to Scale) SEN VCC_QUAD I_N BG_RBIAS I_P SDI SCLK DVDD VCC_MIXER GND LO_P LO_N GND 9 RST IF_I VCC_BG GND VCC_LNA_P IF_Q 9 GND Q_P RF_IN Q_N GND 9 SDO VCC_IF_BB VDET VCC_VGA GND VCTRL VCC_VVA VCC_LNA_P NOTES. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PLANE. Figure. Pin Configuration - Table. Pin Function Descriptions Pin No. Mnemonic Description SEN SPI Serial Enable. SEN is a high impedance pin with a logic of. V., I_N, I_P Negative (I_N) and Positive (I_P) Differential BB I Outputs. These pins are dc-coupled., IF_I, IF_Q IF I and IF Q Single-Ended Complex Quadrature Outputs. These pins are dc-coupled to GND, and each pin is matched to Ω.,,, 9,, GND Ground., Q_P, Q_N Positive (Q_P) and Negative (Q_N) Differential Baseband Q Outputs. These pins are dc-coupled. 9 SDO SPI Serial Data Output. VCC_IF_BB. V Power Supply for BB and IF Section. Place a pf,. µf, and a µf capacitor close to this pin. VDET Square Law Detector Output Voltage. VCC_VGA. V Power Supply for RF Amplifier. Place a pf,. µf, and a µf capacitor close to this pin. VCTRL RF VVA Control Voltage. The voltage on this pin ranges from. V (minimum gain) to V (maximum gain). Refer to the ADMV-EVALZ user guide for the external component requirements. VCC_VVA. V Power Supply for VVA Control Circuit. Place a pf,. µf, and a µf capacitor close to this pin. VCC_LNA_P. V Power Supply for LNA. Place a pf,. µf, and a µf capacitor close to this pin. RF_IN RF Input. This pin is dc-coupled internally with a choke to GND, and matched to Ω, singleended. A dc input above V requires external ac coupling. VCC_LNA_P. V Power Supply for Low Noise Amplifier (LNA). Place a pf,. µf, and a µf capacitor close to this pin. VCC_BG. V Power Supply for Band Gap Circuit. Place a pf,. µf, and a µf capacitor close to this pin. RST SPI Reset. Connect this pin to logic high for normal operation. BG_RBIAS Bang Gap Circuit External High Precision Resistor. Place a. kω, high precision resistor shunt to ground close to this pin. VCC_QUAD. V Power Supply for Quadruple. Place a pf,. µf, and a µf capacitor close to this pin., LO_N, LO_P Negative (LO_N) and Positive (LO_P) Differential Local Oscillator Input. These pins are dc-coupled internally with a choke to GND and matched to Ω differential or Ω single-ended. A dc input above V requires external ac coupling. 9 VCC_MIXER. V Power Supply for the Mixer. Place a pf,. µf, and a µf capacitor close to this pin. DVDD. V SPI Digital Supply. Place a pf,. µf, and a µf capacitor close to this pin. Rev. Page of

8 ADMV Data Sheet SCLK SPI Clock Digital Input. SCLK is a high impedance pin. SDI SPI Serial Data Input. SDI is a high impedance pin. EPAD Exposed Pad. Solder the exposed pad to a low impedance ground plane. Rev. Page of

9 Data Sheet ADMV TYPICAL PERFORMANCE CHARACTERISTICS I/Q MODE RF amplitude = dbm, measurements performed with a mv dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB =. V, DVDD = VCC_VVA =. V, and TA = C, unless otherwise noted. Register xb is set to xc, Register x, Bits[:] are set to, VCM =. V, Register x, Bit =, Register x, Bit =, and measurements are a composite of the I and Q channels. VATT is the attenuation voltage at the VCTRL pin. VATT = V, unless otherwise specified. + C AT.V + C AT.V C AT.V + C AT.V + C AT.V C AT.V + C AT V + C AT V C AT V V ATT (V) + C AT 9GHz + C AT 9GHz C AT 9GHz + C AT GHz + C AT GHz C AT GHz - Figure. Conversion Gain vs. RF Frequency at Three Different Gain Settings for Various Temperatures, fbb = MHz (Upper Sideband) Figure. Conversion Gain vs. VATT for Various RF Frequencies (frf), fbb = MHz at frf = GHz and 9 GHz.V UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9 9 Figure. Conversion Gain vs. RF Frequency for Various Supply Voltages, fbb = MHz BASEBAND FREQUENCY (GHz) Figure. Conversion Gain vs. Baseband Frequency at frf = GHz and 9 GHz (Upper Sideband) - +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND BASEBAND FREQUENCY (GHz) Figure. Conversion Gain vs. RF Frequency for Various LO Inputs, fbb = MHz Figure 9. Conversion Gain vs. Baseband Frequency at frf = GHz and 9 GHz (Lower Sideband) Rev. Page 9 of -

10 ADMV Data Sheet. + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND. 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND INPUT IP (dbm) INPUT IP (dbm) Figure. Input IP vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) V ATT (V) Figure. Input IP vs. VATT for Various RF Frequencies (frf), RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) at frf = GHz and 9 GHz. - INPUT IP (dbm).v UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND. 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND. GHz LOWER SIDEBAND Figure. Input IP vs. RF Frequency at Maximum Gain for Various Supply Voltages, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure. Conversion Gain vs. Baseband Frequency at Maximum Gain, RF Amplitude = dbm per Tone at MHz Spacing at frf = GHz and 9 GHz, Upper Sideband and Lower Sideband - +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND INPUT IP (dbm) INPUT IP (dbm) 9 9 Figure. Input IP vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) - 9 INPUT POWER (dbm) Figure. Input IP vs. Input Power for Various RF Frequencies (frf) at MHz Spacing, fbb = MHz, frf = GHz and 9 GHz - Rev. Page of

11 Data Sheet ADMV NOISE FIGURE (db) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND NOISE FIGURE (db) + C AT 9GHz + C AT 9GHz C AT 9GHz + C AT GHz + C AT GHz C AT GHz V ATT (V) - Figure. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fbb = MHz Figure 9. Noise Figure vs. VATT for Various RF Frequencies, fbb = MHz at frf = GHz and 9 GHz 9.V UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND NOISE FIGURE (db) NOISE FIGURE (db) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9 9 Figure. Noise Figure vs. RF Frequency for Various Supply Voltages, fbb = MHz BASEBAND FREQUENCY (GHz) Figure. Noise Figure vs. Baseband Frequency at frf = GHz and 9 GHz (Upper Sideband) 9-9 +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND NOISE FIGURE (db) NOISE FIGURE (db) 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND 9 9 Figure. Noise Figure vs. RF Frequency for Various LO Inputs, fbb = MHz BASEBAND FREQUENCY (GHz) Figure. Noise Figure vs. Baseband Frequency at frf = GHz and 9 GHz (Lower Sideband) - Rev. Page of

12 ADMV Data Sheet IMAGE REJECTION (dbc) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND IMAGE REJECTION (dbc) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND 9 9 RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fbb = MHz, Uncalibrated RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency for Various LO Inputs, fbb = MHz - IMAGE REJECTION (dbc) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND IMAGE REJECTION (dbc) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9 9 RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fbb = MHz, Calibrated V ATT (V) Figure. Image Rejection vs. VATT for Various RF Frequencies (frf), fbb = MHz at frf = GHz and 9 GHz - IMAGE REJECTION (dbc).v UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND IMAGE REJECTION (dbc) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND 9 9 RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency for Various Supply Voltages, fbb = MHz - RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency at frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) - Rev. Page of

13 Data Sheet ADMV INPUT IP (dbm) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND INPUT IP (dbm) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9 9 Figure. Input IP vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) V ATT (V) Figure. Input IP vs. VATT for Various RF Frequencies (frf), RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) at frf = GHz and 9 GHz - INPUT IP (dbm).v UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND INPUT IP (dbm) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9 9 Figure 9. Input IP vs. RF Frequency (frf) at Maximum Gain for Various Supply Voltages, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure. Input IP vs. Baseband Frequency at Maximum Gain, RF Amplitude = dbm per Tone at MHz Spacing at frf = GHz and 9 GHz, Upper Sideband - INPUT IP (dbm) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND INPUT IP (dbm) 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND 9 9 Figure. Input IP vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = dbm per Tone at MHz Spacing, fbb = MHz (Upper Sideband) BASEBAND FREQUENCY (GHz) Figure. Input IP vs. Baseband Frequency for Various RF Frequencies (frf) at MHz Spacing, fbb = MHz, frf = GHz and 9 GHz - Rev. Page of

14 ADMV Data Sheet + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND INPUT PdB (dbm) INPUT PdB (dbm) + C AT 9GHz + C AT 9GHz C AT 9GHz + C AT GHz + C AT GHz C AT GHz V ATT (V) - Figure. Input PdB vs. RF Frequency at Maximum Gain for Various Temperatures, fbb = MHz Figure. Input PdB vs. VATT for Various RF Frequencies (frf), fbb = MHz at frf = GHz and 9 GHz.V UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND INPUT PdB (dbm) INPUT PdB (dbm) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9 9 Figure. Input PdB vs. RF Frequency for Various Supply Voltages, fbb = MHz BASEBAND FREQUENCY (GHz) Figure. Input PdB vs. Baseband Output Frequency at frf = GHz and 9 GHz (Upper Sideband) - +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND INPUT PdB (dbm) INPUT PdB (dbm) 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND 9 9 Figure. Input PdB vs. RF Frequency for Various LO Inputs, fbb = MHz BASEBAND FREQUENCY (GHz) Figure 9. Input PdB vs. Baseband Output Frequency at frf = GHz and 9 GHz (Lower Sideband) - Rev. Page of

15 Data Sheet ADMV MAGNITUDE ERROR (db) BB I_N + C BB I_N + C BB I_N C BB Q_N + C BB Q_N + C BB Q_N C. BASEBAND OUTPUT FREQUENCY (GHz) BB Q_P + C BB Q_P + C BB Q_P C Figure. Magnitude Error vs. Baseband Output Frequency, Referenced to I_P Output, frf = GHz, for Various Temperatures, at Maximum Gain PHASE ERROR (Degrees) BB I_N + C BB I_N + C BB I_N C BB Q_N + C BB Q_N + C BB Q_N C BASEBAND OUTPUT FREQUENCY (GHz) BB Q_P + C BB Q_P + C BB Q_P C Figure. Phase Error vs. Baseband Output Frequency, Referenced to I_P Output, frf = GHz, for Various Temperatures, at Maximum Gain - - MAGNITUDE ERROR (db) BB I_N + C BB Q_N + C BB Q_P + C. BB I_N + C BB Q_N + C BB Q_P + C BB I_N C BB Q_N C BB Q_P C. BASEBAND OUTPUT FREQUENCY (GHz) Figure. Magnitude Error vs. Baseband Output Frequency, Referenced to I_P Output, frf = 9 GHz, for Various Temperatures, at Maximum Gain PHASE ERROR (Degrees) BB I_N + C BB I_N + C BB I_N C BB Q_N + C BB Q_N + C BB Q_N C BASEBAND OUTPUT FREQUENCY (GHz) BB Q_P + C BB Q_P + C BB Q_P C Figure. Phase Error vs. Baseband Output Frequency, Referenced to I_P Output, frf = 9 GHz, for Various Temperatures, at Maximum Gain - - Rev. Page of

16 ADMV Data Sheet NOISE FIGURE (db) 9 9 Figure. Conversion Gain vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL (Register xa, Bits[:]) Settings, fbb = MHz (Upper Sideband) Figure. Noise Figure vs. RF Frequency Four Different BB_AMP_GAIN_CTRL (Register xa, Bits[:]) Settings, fbb = MHz (Upper Sideband) - INPUT IP (dbm) 9 9 Figure. Input IP vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL (Register A, Bits[:]) Settings, fbb = MHz (Upper Sideband) - Rev. Page of

17 Data Sheet ADMV IF MODE RF amplitude = dbm, measurements performed with a mv dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB =. V, DVDD = VCC_VVA =. V, TA = C unless otherwise specified. Register xb set to xc, Register x, Bits[:] set to, measurements performed with a 9 hybrid, Register x, Bit =, and Register x, Bit =. + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND 9 9 Figure. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures, fif =. GHz (Upper Sideband and Lower Sideband) IF FREQUENCY 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure. Conversion Gain vs. IF Frequency (fif) at Maximum Gain, frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) -.V UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND 9 9 Figure. Conversion Gain vs. RF Frequency at Maximum Gain for Various Supply Voltages, fif =. GHz (Upper Sideband and Lower Sideband) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND 9 9 Figure 9. Conversion Gain vs. RF Frequency at Maximum Gain for Various LO Inputs, fif =. GHz (Upper Sideband and Lower Sideband) V ATT (V) + C AT GHz + C AT GHz C AT GHz + C AT 9GHz + C AT 9GHz C AT 9GHz Figure. Conversion Gain vs. VATT at Various RF Frequencies (frf), fif =. GHz, frf = GHz and 9 GHz (Upper Sideband) V ATT (V) + C AT GHz + C AT GHz C AT GHz + C AT 9GHz + C AT 9GHz C AT 9GHz Figure. Conversion Gain vs. VATT at Various RF Frequencies (frf), fif =. GHz, frf = GHz and 9 GHz (Lower Sideband) - - Rev. Page of

18 ADMV Data Sheet INPUT IP (dbm) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND 9 9 Figure. Input IP vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = dbm per Tone at MHz Spacing, fif =. GHz (Upper Sideband and Lower Sideband) INPUT IP (dbm).v UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND 9 9 Figure. Input IP vs. RF Frequency at Maximum Gain for Various Supply Voltages, RF Amplitude = dbm per Tone at MHz Spacing, fif =. GHz (Upper Sideband and Lower Sideband) INPUT IP (dbm) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND 9 9 Figure. Input IP vs. RF Frequency at Maximum gain for Various LO Inputs, RF Amplitude = dbm per Tone at MHz Spacing, fif =. GHz (Upper Sideband and Lower Sideband) INPUT IP (dbm) V ATT (V) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure. Input IP vs. VATT for Various RF Frequencies (frf), RF Amplitude = dbm per Tone at MHz Spacing, fif =. GHz at frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) INPUT IP (dbm) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND IF FREQUENCY (GHz) Figure. Input IP vs. IF Frequency at Maximum Gain, RF Amplitude = dbm per Tone at MHz Spacing at frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) INPUT IP (dbm) 9 INPUT POWER (dbm) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND Figure. Input IP vs. Input Power for Various RF Frequencies (frf), at MHz Spacing, fif =. GHz, frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) Rev. Page of

19 Data Sheet ADMV + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND 9 NOISE FIGURE (db) NOISE FIGURE (db) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND 9 9 Figure 9. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fif =. GHz (Upper Sideband and Lower Sideband) NOISE FIGURE (db).v UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND 9 9 Figure. Noise Figure vs. RF Frequency at Maximum Gain for Various Supply Voltages, fif =. GHz (Upper Sideband and Lower Sideband) NOISE FIGURE (db) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND 9 9 Figure. Noise Figure vs. RF Frequency at Maximum Gain for Various LO Inputs, fif =. GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) Figure. Noise Figure vs. IF Frequency at Maximum Gain, frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) NOISE FIGURE (db) + C AT GHz + C AT GHz C AT GHz + C AT 9GHz + C AT 9GHz C AT 9GHz V ATT (V) Figure. Noise Figure vs. VATT at Various RF Frequencies (frf), fif =. GHz, frf = GHz and 9 GHz (Upper Sideband) NOISE FIGURE (db) + C AT GHz + C AT GHz C AT GHz + C AT 9GHz + C AT 9GHz C AT 9GHz V ATT (V) Figure. Noise Figure vs. VATT at Various RF Frequencies (frf), fif =. GHz, frf = GHz and 9 GHz (Lower Sideband) Rev. Page 9 of

20 ADMV Data Sheet INPUT PdB (dbm) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND INPUT PdB (dbm) 9 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND INPUT PdB (dbm) 9 9 Figure. Input PdB vs. RF Frequency at Maximum Gain for Various Temperatures, fif =. GHz (Upper Sideband and Lower Sideband).V UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND 9 9 Figure. Input PdB vs. RF Frequency at Maximum Gain for Various Supply Voltages, fif =. GHz (Upper Sideband and Lower Sideband) INPUT PdB (dbm) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND Figure. Input PdB vs. RF Frequency at Maximum Gain for Various LO Inputs, fif =. GHz (Upper Sideband and Lower Sideband) INPUT PdB (dbm) IF FREQUENCY (GHz) Figure. Input PdB vs. IF Frequency at Maximum Gain, frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) V ATT (V) + C AT GHz + C AT GHz C AT GHz + C AT 9GHz + C AT 9GHz C AT 9GHz Figure 9. Input PdB vs. VATT at Various RF Frequencies (frf), fif =. GHz, frf = GHz and 9 GHz (Upper Sideband) INPUT PdB (dbm) V ATT (V) + C AT GHz + C AT GHz C AT GHz + C AT 9GHz + C AT 9GHz C AT 9GHz Figure. Input PdB vs. VATT at Various RF Frequencies (frf), fif =. GHz, frf = GHz and 9 GHz (Lower Sideband) Rev. Page of

21 Data Sheet ADMV IMAGE REJECTION (dbc) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND IMAGE REJECTION (dbc) +dbm UPPER SIDEBAND dbm UPPER SIDEBAND dbm UPPER SIDEBAND +dbm LOWER SIDEBAND dbm LOWER SIDEBAND dbm LOWER SIDEBAND 9 9 RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fif =. GHz (Upper Sideband and Lower Sideband), Uncalibrated RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency at Maximum Gain for Various LO Inputs, fif =. GHz (Upper Sideband and Lower Sideband) - IMAGE REJECTION (dbc) + C UPPER SIDEBAND + C UPPER SIDEBAND C UPPER SIDEBAND + C LOWER SIDEBAND + C LOWER SIDEBAND C LOWER SIDEBAND IMAGE REJECTION (dbc) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND 9 9 RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Temperatures, fif =. GHz (Upper Sideband and Lower Sideband), Calibrated - IF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. IF Input Frequency at Maximum Gain, frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) - IMAGE REJECTION (dbc).v UPPER SIDEBAND.V UPPER SIDEBAND.V UPPER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND.V LOWER SIDEBAND IMAGE REJECTION (dbc) 9GHz UPPER SIDEBAND GHz UPPER SIDEBAND 9GHz LOWER SIDEBAND GHz LOWER SIDEBAND 9 9 RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Supply Voltages, fif =. GHz (Upper Sideband and Lower Sideband) V ATT (V) Figure. Image Rejection vs. VATT at Various RF Frequencies (frf), fif =. GHz, frf = GHz and 9 GHz (Upper Sideband and Lower Sideband) - Rev. Page of

22 ADMV Data Sheet 9 9 Figure. Conversion Gain vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x Settings, fif =. GHz (Upper Sideband); Settings for Register x, Bits[:] and Register x9, Bits[:] Are the Same Figure. Conversion Gain vs. RF Frequency at Different IF_AMP_ FINE_GAIN_x Settings, fif =. GHz (Upper Sideband); Register x, Bits[:] and Bits[:] Are the Same - INPUT IP (dbm) INPUT IP (dbm) Figure. Input IP vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x Settings, fif =. GHz (Upper Sideband); Settings for Register x, Bits[:] and Register x9, Bits[:] Are the Same Figure 9. Conversion Gain vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x Settings, fif =. GHz (Upper Sideband); Settings for Register x, Bits[:] and Register x9, Bits[:] Are the Same Figure. Input IP vs. RF Frequency at Different IF_AMP_FINE_GAIN_x Settings, fif =. GHz (Upper Sideband); Settings for Register x, Bits[:] and Bits[:] Are the Same NOISE FIGURE (db) Figure. Noise Figure vs. RF Frequency at Different IF_AMP_FINE_GAIN_x Settings, fif =. GHz (Upper Sideband); Settings for Register x, Bits[:] and Bits[:] Are the Same - - Rev. Page of

23 Data Sheet ADMV.. I/Q MAGNITUDE ERROR (db) C + C C I/Q MAGNITUDE ERROR (db) C + C C... IF OUTPUT FREQUENCY (GHz) Figure. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I Output, frf = GHz, for Various Temperatures, at Maximum Gain -. IF OUTPUT FREQUENCY (GHz) Figure. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I Output, frf = 9 GHz, for Various Temperatures, at Maximum Gain - I/Q PHASE ERROR (db) + C + C C I/Q PHASE ERROR (db) + C + C C IF OUTPUT FREQUENCY (GHz) Figure. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output, frf = GHz, for Various Temperatures, at Maximum Gain - IF OUTPUT FREQUENCY (GHz) Figure. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output, frf = 9 GHz, for Various Temperatures, at Maximum Gain - Rev. Page of

24 ADMV Data Sheet OUTPUT DETECTOR PERFORMANCE RF amplitude = dbm, measurements performed with a mv dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB =. V, DVDD = VCC_VVA =. V, Register xb is set to xc, Register x, Bit =, Register x, Bits[:] set to, and TA = C, unless otherwise noted. VDET (V) C = + C = + C = + C = + C = + C = RF INPUT POWER (dbm) C = C = C = Figure. VDET vs. RF Input Power, frf = GHz for Various Temperatures and DET_PROG Settings VDET (V) C = + C = + C = + C = + C = + C = RF INPUT POWER (dbm) C = C = C = Figure. VDET vs. RF Input Power, frf = 9 GHz for Various Temperatures and DET_PROG Settings VDET LINEARITY ERROR (db) + C = + C = + C = + C = + C = + C = C = C = C = RF INPUT POWER (dbm) Figure 9. VDET Linearity Error vs. RF Input Power, frf = GHz for Various Temperatures and DET_PROG Settings VDET LINEARITY ERROR (db) + C = + C = + C = + C = + C = + C = C = C = C = RF INPUT POWER (dbm) Figure 9. VDET Linearity Error vs. RF Input Power, frf = 9 GHz for Various Temperatures and DET_PROG Settings -9-9 VDET (V) RF INPUT FREQUENCY (GHz) Figure 9. VDET vs. RF Input Frequency at Various Input Power Levels, DET_PROG = -9 Rev. Page of

25 Data Sheet ADMV RETURN LOSS RF amplitude = dbm, measurements performed with a mv dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_IF_BB =. V, DVDD = VCC_VVA =. V, Register xb is set to xc, Register x, Bits[:] are set to, and TA = C, unless otherwise noted. Measurements in IF mode performed with a 9 hybrid, Register x, Bit =, Register x, Bit =, unless otherwise noted. Measurements in I/Q mode are measured as a composite of the I and Q channel performed, VCM =. V, Register x, Bit =, and Register x, Bit =, unless otherwise noted. RF RETURN LOSS (db) I/Q DIFFERENTIAL RETURN LOSS (db) I Q 9 9 Figure 9. RF Input Return Loss vs. RF Frequency -9 I/Q FREQUENCY (GHz) Figure 9. I/Q Differential Return Loss vs. I/Q Frequency (Taken Without Hybrids or Baluns) -9 LO RETURN LOSS (db) LO N LO P LO DIFF IF RETURN LOSS (db) IF_I IF_Q 9 LO FREQUENCY (GHz) Figure 9. LO Return Loss vs. LO Frequency -9 IF FREQUENCY (GHz) Figure 9. IF Return Loss vs. IF Frequency (Taken Without Hybrid) -99 LO TO RF LEAKAGE (dbm) 9 LOx = + C LOx = + C LOx = C LOx = + C LOx = + C LOx = C LO TO IF LEAKAGE (dbm) 9 I =. I =.9 I = Q =. Q =.9 Q = LO INPUT FREQUENCY (GHz) -9 9 LO INPUT FREQUENCY (GHz) Figure 9. LO to RF Leakage vs. LO Input Frequency for Various Temperatures Figure 9. LO to IF Leakage vs. LO Input Frequency at Different VCTRL Settings at Different Gain Settings Rev. Page of -

26 ADMV Data Sheet LO TO IF LEAKAGE (dbm) I = + C I = + C I = C Q = + C Q = + C Q = C LO TO IF LEAKAGE (dbm) I = I = I = I = I = Q = Q = Q = Q = Q = 9 LO INPUT FREQUENCY (GHz) Figure 9. LO to IF Leakage vs. LO Input Frequency at Various Temperatures LO TO I/Q LEAKAGE (dbm) 9 IP = + C IP = + C IP = C IN = + C IN = + C IN = C QP = + C QP = + C QP = C QN = + C QN = + C QN = C LO INPUT FREQUENCY (GHz) Figure 99. LO to I/Q Leakage vs. LO Input Frequency at Various Temperatures (Taken Without Hybrid) LO INPUT FREQUENCY (GHz) Figure. LO to IF Leakage, vs. LO Input Frequency at Different IF Amplifier Gain Settings (Taken Without Hybrid) FUNDAMENTAL LO TO I/Q LEAKAGE (db) I_P = I_P = I_N = I_N = Q_P = Q_P = Q_N = Q_N = 9 9 LO INPUT FREQUENCY (GHz) Figure. Fundamental LO to I/Q Leakage vs. LO Input Frequency at Different Baseband Amplifier Gain Settings - - Rev. Page of

27 Data Sheet M N SPURIOUS PERFORMANCE Mixer spurious products are measured in dbc from the IF output power level. Spurious values are measured using the following equation: (M RF)+ (N LO) N/A means not applicable. Blank cells in the spurious performance tables indicate that the frequency is above GHz and is not measured. The LO frequencies are referred from the frequencies applied to the LO_x pin of the ADMV. RF amplitude = dbm, measurements performed with a mv dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_ IF_BB =. V, DVDD = VCC_VVA =. V, Register xb is set to xc, Register x, Bits[:] are set to, and TA = C, unless otherwise noted. Measurements in IF mode performed with Register x, Bit = and Register x, Bit =, unless otherwise noted. The measurements in I/Q mode are as follows: VCM =. V, Register x, Bit =, and Register x, Bit =, unless otherwise noted. I/Q Mode Measurements are made on the I_P port. Data is taken without any hybrids or baluns. BB frequency (fbb) = MHz, LO=.9 GHz at dbm, and frf = GHz at dbm. M RF N LO N/A + 9 fbb = MHz, LO= 9. GHz at dbm, and frf = 9 GHz at dbm. M RF N LO 9 9 N/A + ADMV IF Mode Measurements are made on the IF_I port. Data is taken without any 9 hybrid. IF frequency (fif) =. GHz, LO=. GHz at dbm, and frf = GHz at dbm. M RF N LO N/A + fif =. GHz, LO=. GHz at dbm, and frf = 9 GHz at dbm. M RF N LO N/A + 9 fif =. GHz, LO=. GHz at dbm, and frf = GHz at dbm. M RF N LO N/A fif =. GHz, LO=. GHz at dbm, and frf =9 GHz at dbm M RF N LO N/A Rev. Page of

28 ADMV THEORY OF OPERATION The ADMV is a wideband microwave downconverter optimized for microwave radio designs operating in the GHz to GHz frequency range. See Figure for a functional block diagram of the device. The ADMV digital settings are controlled via the SPI. The ADMV has two modes of operation: Baseband quadrature demodulation (I/Q mode) Image reject I/Q downconversion (IF mode) START-UP SEQUENCE The ADMV SPI settings require its default settings to be changed during startup for optimum performance. Set Register xb to xc after every power-up or reset. Set Register x, Bits[:] to after every power-up or reset. BASEBAND QUADRATURE DEMODULATION (I/Q MODE) In I/Q mode, the output impedance of the baseband I/Q ports is Ω differential. These outputs are designed to be loaded to a dc-coupled, differential, Ω load. I_P and I_N are the differential baseband I outputs. Q_P and Q_N are the differential baseband Q outputs. To set the ADMV in I/Q mode, set BB_AMP_PD (Register x, Bit ) to and set IF_AMP_PD (Register x, Bit ) to. The baseband I/Q ports are designed to operate from dc to. GHz at each I and Q channel. Data Sheet The BB output VCM can be changed from. V to. V. To change the VCM, set BB_SWITCH_HIGH_LOW_COMMMON (Register xa, Bit ) to be the opposite of Register xa, Bit. Also, set the MIXER_VGATE bit field (Register x, Bits[:9]) and the BB_AMP_REF_GEN bit field (Register xa, Bits[:]) based on Table. Table provides the correct setting for these bit fields vs. the required common-mode voltage. The VCM can be further adjusted on each I or Q channel by ± mv by setting the BB_AMP_OFFSET_I bit field (Register x9, Bits[:]) and the BB_AMP_OFFSET_Q bit field (Register x9, Bits[9:]) for each VCM setting shown in Table. The most significant bit (MSB) for each bit field is the sign bit. When the MSB is, the values of the four lower bits are positive. When the MSB is, the values of the four lower bits are negative. These bits also offer input IP and common-mode rejection optimization. The BB I/Q section of the ADMV also features a baseband amplifier with a digital attenuator that is controlled by setting the BB_AMP_GAIN_CTRL bit field (Register xa, Bits[:]). Figure, Figure, and Figure show the performance of the baseband digital attenuator. The Baseband Quadrature Demodulation to Very Low Frequencies section shows the baseband performance to very low demodulation frequencies. Table. Common-Mode Voltage Settings MIXER_VGATE (Register x, Bits[:9]) VCM (V) BB_AMP_REF_GEN (Register xa, Bits[:]) BB_SWITCH_HIGH_LOW_COMMON_MODE (Register xa, Bit ) Rev. Page of

29 Data Sheet IMAGE REJECTION DOWNCONVERSION The ADMV features the ability to downconvert to a real IF output anywhere from MHz to MHz, while suppressing the unwanted image sideband by typically better than dbc. The IF outputs are quadrature to each other, Ω single-ended, and are internally ac coupled. IF_I and IF_Q are the quadrature IF outputs. An external 9 hybrid is required to select the appropriate sideband. To configure the ADMV in IF mode, set BB_AMP_PD (Register x, Bit ) to and set IF_AMP_PD (Register x, Bit ) to Each IF output features an amplifier with a digital attenuator. The digital attenuator can be adjusted using fine or coarse steps. The coarse steps for the IF_I can be adjusted using the IF_AMP_ COARSE_GAIN_I bit field (Register x, Bits[:]). The coarse steps for the IF_Q can be adjusted using the IF_AMP_COARSE_ GAIN_Q bit field (Register x9, Bits[:]). Each course gain bit field has five settings. The fine steps for IF_I can be adjusted using the IF_AMP_FINE_GAIN_I bit field (Register x, Bits[:]). The fine steps for the IF_Q can be adjusted using the IF_AMP_FINE_GAIN_Q bit field (Register x, Bits[:]). Figure to Figure show the performance of these four bit fields. DETECTOR The ADMV features a square law detector that produces a voltage linearly, according to the square of the RF voltage output from the low noise amplifier. The detector can be enabled by setting the DET_EN bit (Register x, Bit ) to. The detector can be turned off by setting this bit to. The detector linear range can be adjusted by setting the DET_PROG bit field (Register x, Bits[:]). These ranges are specified based on the input power into the detector coming from the output of the low noise amplifier. Each DET_PROG setting offers an approximate db of ± db dynamic range based on a twopoint linear regression from an ideal line for one temperature at each DET_PROG setting. See Figure 9 to Figure 9 for more performance information of the detector. LO INPUT PATH The LO input path operates from. GHz to. GHz with an LO amplitude range of dbm to + dbm. The LO has an internal quadrupler ( ) and a programmable band-pass filter. The LO band-pass filter is programmable using QUAD_FILTERS (Register x9 Bits[:]). See the Performance at Different Quad Filter Settings section for more information on the QUAD_FILTERS settings. The LO path can operate either differentially or single-ended (SE). LOIP and LOIN are the inputs to the LO path. The LO ADMV path can switch from differential to single-ended operation by setting the QUAD_SE_MODE bits (Register x, Bits[9:]). See the Performance Between Differential vs. Single-Ended LO Input section for more information. Figure shows a block diagram of the LO path. LO_N LO_P AMP Figure. LO Path Block Diagram LO_N LO_P Enable the quadrupler by setting the QUAD_IBIAS_PD bit (Register x, Bit ) to and the QUAD_BG_PD bit (Register x, Bit 9) to. To power down the quadrupler, set both of these bits to. An unwanted image can be downconverted from the quadrature error in generating the quadrature LO signals. Deviation from ideal quadrature (that is, total image rejection and no image tone is downconverted) on these signals limits the amount of achievable image rejection. The ADMV offers about of quadrature phase adjustment in the LO path quadrature signals. Make these adjustments through the LOAMP_PH_ADJ_I_FINE bits (Register x, Bits[:9]) and the LOAMP_PH_ADJ_Q_FINE (Register x, Bits[:]) bits. These bits reject the unwanted sideband signal. In IF mode amplitude adjustments can be made to the complex outputs via IF_AMP_FINE_GAIN_Q (Register x, Bits[:]) and IF_AMP_FINE_GAIN_I (Register x, Bits[:]) to further reduce the unwanted sideband. POWER-DOWN The SPI of the ADMV allows the user to power down device circuits and reduce power consumption. There are two power-down modes: band gap power-down mode (BG_PD) and individual power-down circuits mode. The BG_PD bit (Register x, Bit ) and the QUAD_BG_PD bit (Register x, Bit 9) power down the band gap circuit. The QUAD_IBIAS_PD bit (Register x, Bit ) and the IBIAS_PD bit (Register x, Bit ) power down the specific circuits. Table shows the circuits that are controlled by their related power-down bit, the typical power savings, and the latency requirement to power the circuits back up. - Rev. Page 9 of

30 ADMV Data Sheet Table. Power-Down Power and Latency Requirements Bit Name Circuit Typical Power Savings (mw) Power-Up Latency (µs) IBIAS_PD Receiver bias current (IBIAS) < QUAD_IBIAS_PD LO path < BG_PD and QUAD_BG_PD Band gap. < IBIAS_PD, IF_AMP_PD, QUAD_BG_PD, BB_AMP_PD, QUAD_IBIAS_PD, BG_PD Entire chip < Power-Down Latency (µs) SEN SCLK 9 9 SDI SEN R/W A A A A A A D D D D D D D9 D D D D D D D D D P Figure. Write Serial Port Timing Diagram - SCLK 9 9 SDI R/W A A A A A A SDO D D D D D D D9 D D D D D D D D D P Figure. Read Serial Port Timing Diagram - SERIAL PORT INTERFACE (SPI) The SPI of the ADMV allows the user to configure the device for specific functions or operations via a -pin SPI port. This interface provides users with added flexibility and customization. The SPI consists of four control lines: SCLK, SDIN, SDO, and SEN. The ADMV protocol consists of a write/read bit followed by six register address bits, data bits, and a parity bit. Both the address and data fields are organized most significant bit (MSB) first and end with the least significant bit (lower sideband). For a write, set the first bit to. For a read, set the first bit to. The write cycle sampling must be performed on the rising edge. The bits of the serial write data are shifted in, MSB to Lower Sideband. The ADMV input logic level for the write cycle supports an. V interface. For a read cycle, up to bits of serial read data are shifted out, MSB first. After the bits of data shift out, the parity bit shifts out. The output logic level for a read cycle is. V. The parity bit always follows the direction of the data. If parity is not used, the transmitting end transmits zero instead of parity. The parity is odd, which means that the total number of ones transmitted during a command, including the read/write bit, the address bit, the data bit, and the parity bit, must be odd. Figure and Figure show the SPI write and read protocol, respectively. Rev. Page of

31 Data Sheet ADMV APPLICATIONS INFORMATION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE Figure shows the EVM vs. input power performance of the ADMV in IF mode at maximum gain, upper sideband, C and dbm LO input power. The EVM measurement was performed using four MHz, G-NR, QAM waveforms. The EVM shown is the average of the four channels. The EVM of the test equipment was not de-embedded. Figure shows the constellation diagram and EVM statistics of each of the four channels at dbm input power. EVM (%) P IN (dbm) -9 Figure. EVM vs. Input Power at GHz, VCTRL = V, TA = C, LO = dbm, Upper Sideband (Low-Side LO), IF =. GHz Figure. Constellation Diagram and EVM Statistics per Channel - Rev. Page of

32 ADMV BASEBAND QUADRATURE DEMODULATION TO VERY LOW FREQUENCIES Figure to Figure show the I/Q mode performance at low baseband frequencies. The measurements were performed at GHz, dbm input power, VCM =. V, Register x, Bit =, Register x, Bit =, dbm LO input power, and TA = C. I AND Q DIFFERENTIAL PEAK-TO-PEAK VOLTAGE k k k M M M BASEBAND FREQUENCY (Hz) Q DIFFERENTIAL I DIFFERENTIAL Figure. I and Q Differential Peak-to-Peak Voltage vs. Baseband Frequency, k k k M M M BASEBAND FREQUENCY (Hz) Q GAIN I GAIN Figure. Conversion Gain vs. Baseband Frequency - - IMAGE REJECTION (dbc) COMMON MODE REJECTION (db) Data Sheet IMAGE REJECT k k k M M M BASEBAND FREQUENCY (Hz) Figure. Image Rejection vs. Baseband Frequency COMMON MODE REJECTION I COMMON MODE REJECTION Q k k k M M M BASEBAND FREQUENCY (Hz) Figure. Common-Mode Rejection vs. Baseband Frequency PERFORMANCE AT DIFFERENT QUAD FILTER SETTINGS Figure shows the conversion gain vs. RF frequency in IF mode at C and LO input power = dbm, for different QUAD_FILTERS settings. Figure shows the LO to IF_I and LO to IF_Q leakage vs. LO frequency at different quad filter settings. - - AMPLITUDE IMBALANCE (db)/ PHASE IMBALANCE (Degrees) AMPLITUDE IMBALANCE PHASE IMBALANCE QUAD_FILTERS = QUAD_FILTERS = QUAD_FILTERS = QUAD_FILTERS = k k k M M M BASEBAND FREQUENCY (Hz) Figure 9. Amplitude Imbalance and Phase Imbalance vs. Baseband Frequency - Rev. Page of 9 9 Figure. Conversion Gain vs. RF Frequency for Four Different QUAD_FILTERS Settings, fif =. GHz (Upper Sideband) -

33 Data Sheet ADMV LO TO IF LEAKAGE (dbm) IF I: QUAD_FILTERS = IF I: QUAD_FILTERS = IF I: QUAD_FILTERS = IF I: QUAD_FILTERS = IF Q: QUAD_FILTERS = IF Q: QUAD_FILTERS = IF Q: QUAD_FILTERS = IF Q: QUAD_FILTERS = 9 LO FREQUENCY (GHz) Figure. LO To IF Leakage vs. RF Frequency for Four Different QUAD_FILTERS Settings, fif =. GHz (Upper Sideband) VVA TEMPERATURE COMPENSATION Figure shows the conversion gain vs. RF frequency at two different Register xb settings and three different temperatures for IF mode. The recommended value suggested in the Start-Up Sequence section provides the highest conversion gain. If the priority is to decrease the conversion gain variation across temperature, Register xb can be set to xc. However, at this value, the conversion gain is lower at each temperature. + C AT REG xb = xc + C AT REG xb = xc C AT REG xb = xc + C AT REG xb = xc + C AT REG xb = xc C AT REG xb = xc 9 9 Figure. Conversion Gain vs. RF Frequency at Maximum Gain for Various Register xb Settings and Various Temperatures - - PERFORMANCE BETWEEN DIFFERENTIAL vs. SINGLE-ENDED LO INPUT Figure to Figure show the conversion gain, input IP and image rejection performance for operating the ADMV LO input as differential vs. SE. The measurements were performed with dbm LO input power, IF mode, with an IF frequency of. GHz, upper sideband, and TA = C. LO DIFF LO SE P SIDE LO SE N SIDE 9 9 Figure. Conversion Gain vs. RF Frequency for Three Different LO Mode Settings, fif =. GHz (Upper Sideband) INPUT IP (dbm) LO DIFF LO SE P SIDE LO SE N SIDE 9 9 Figure. Input IP vs. RF Frequency for Three Different LO Mode Settings, RF Amplitude = dbm per Tone at MHz Spacing, fif =. GHz (Upper Sideband -9 - Rev. Page of

34 ADMV Data Sheet IMAGE REJECTION (dbc) LO DIFF LO SE P SIDE LO SE N SIDE RF INPUT FREQUENCY (GHz) Figure. Image Rejection vs. RF Input Frequency for Three Different LO Mode Settings, RF Amplitude = dbm per Tone at MHz Spacing, fif =. GHz (Upper Sideband) PERFORMANCE ACROSS RF FREQUENCY AT FIXED IF AND BASEBAND FREQUENCIES The ADMV quadrupler operates from. GHz to GHz. When using high-side LO injection, the conversion gain starts rolling off gradually after the quadrupler frequency reaches GHz. When using low-side LO, the conversion gain starts rolling off when the quadrupler frequency is. GHz. Figure and Figure 9 show the conversion gain vs. RF frequency in IF mode for fixed IF frequencies (TA = C, LO = dbm) for upper sideband and lower sideband, respectively. Figure and Figure show the conversion gain vs. RF frequency in IQ mode for fixed BB frequencies (TA = C, LO = dbm) for upper sideband and lower sideband, respectively. 9 9.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND Figure. Conversion Gain vs. RF Frequency for Multiple IF Frequency Settings (Upper Sideband) - -.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND 9 9 Figure 9. Conversion Gain vs. RF Frequency at Multiple IF Frequency Settings (Lower Sideband) 9 9.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND.GHz UPPER SIDEBAND Figure. Conversion Gain vs. RF Frequency at Multiple I/Q Frequency Settings (Upper Sideband).GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND.GHz LOWER SIDEBAND 9 9 Figure. Conversion Gain vs. RF Frequency at Multiple IQ Frequency Settings (Lower Sideband) Rev. Page of

35 Data Sheet RECOMMENDED LAND PATTERN Solder the exposed pad on the underside of the ADMV to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package. ADMV EVALUATION BOARD INFORMATION For more information about the ADMV evaluation board, refer to the ADMV-EVALZ user guide. Figure. Evaluation Board Layout for the LGA package - Rev. Page of