I 2 C BUS compatible serial EEPROM

Transcription

1 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- I 2 BU compatible serial M B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- he B2401-, B2402-, and B2404- series are 2-wire (I 2 BU type) serial Ms which are electrically programmable. I 2 BU is a registered trademark of hilips.!pplications Vs, Vs, printers, car stereos, cordless telephones, short wave radios, programmable DI switches!features 1) 128 8bits (1k) serial M. (B2401- F- FJ- FV-) 256 8bits (2k) serial M. (B2402- F- FJ- FV-) 512 8bits (4k) serial M. (B2404- F- FJ- FV-) 2) wo wire serial interface. 3) perating voltage range : 2.V 5.5V 4) Low current consumption ctive (at 5V) : 1.5m (yp.) tandby (at 5V) : 0.1µ (yp.) 5) uto erase and auto complete functions can be used during write operations. 6) age write function. B2401- F- FJ- FV- : 8 bytes B2402- F- FJ- FV- : 8 bytes B2404- F- FJ- FV- : 16 bytes ) D security rite protect feature Inhibit to I at low V 8) Noise filters at L and D pins. 9) ddress can be incremented automatically during read operations. 10) ompact packages. 11) ewriting possible up to 100,000 times 12) Data can be stored for ten years without corruption.!bsolute maximum ratings (a = 25 ) arameter ymbol Limits Unit pplied voltage V 0.3~+6.5 V ower dissipation d 300( B8) 450(8, J8) 800(DI8) torage temperature stg 65~+125 perating temperature opr 40~+85 Input voltage 0.3~V+0.3 V 1 educed by 3.0m for each increase in a of 1 over educed by 4.5m for each increase in a of 1 over educed by 8.0m for each increase in a of 1 over m

2 B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- Memory Is B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV-!ecommended operating conditions (a = 25 ) arameter ymbol Limits Unit ower supply voltage V 2.~5.5 (I) 2.~5.5 (D) V V Input voltage VIN 0~V V!Block diagram B2401- F- FJ- FV-!in descriptions in name Function bits DD DD bits 1kbits M Y LV D DD GI 8bits D GI 8 V 0, 1, 2 lave address setting pin L erial data clock D erial data input output rite protect pin V ower supply GND Ground n open drain output requires a pull-up resistor. 2 3 NL LGI 6 L GND 4 HIGH VLG GN. V LVL D 5 D B2402- F- FJ- FV- in name Function bits DD DD 8bits 2kbits M Y LV D DD GI 8bits D GI 8 V 0, 1, 2 L D V GND lave address setting pin erial data clock erial data input output rite protect pin ower supply Ground n open drain output requires a pull-up resistor. 2 3 NL LGI 6 L GND 4 HIGH VLG GN. V LVL D 5 D B2404- F- FJ- FV- in name 0 N.. Function 0 1 4kbits M Y 8 V 1, 2 lave address setting pin 1 2 9bits DD DD 9bits LV D DD GI 8bits D GI L D V erial data clock erial data input output rite protect pin ower supply 2 3 NL LGI 6 L GND Ground n open drain output requires a pull-up resistor. GND 4 HIGH VLG GN. V LVL D 5 D

3 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV-!lectrical characteristics D characteristics (unless otherwise noted, a = 40 to + 85, V = 2. to 5.5V) arameter ymbol Min. yp. Max. Unit onditions Input high level voltage VIH 0.V V Input low level voltage VIL 0.3V V utput low level coltage VL 0.4 V IL=3.0m(D) Input leakage current ILI 1 1 µ VIN=0V~V utput leakage current IL 1 1 µ VU=0V~V operatingcurrent dissipation I 2.0 m V=5.5V, fl=400khz tandby current IB Not designed for radiation resistance. 2.0 µ V=5.5V, D L=V 0, 1, 2=GND, =GND perating timing characteristics (unless otherwise noted, a = 40 to + 85, V = 2. to 5.5V) L frequency Data clock HIGH time arameter ymbol fl thigh Data clock L time tl µs D L rise time t µs D L fall time tf µs tart condition hold time thd : µs tart condition setup time tu : µs Input data hold time thd : D 0 0 ns Input data setup time tu : D ns utput data delay time td µs utput data hold time tdh µs top condition setup time tu : µs Bus open time before start of transfer tbuf µs Internal write cycle time t Vcc=5V±10% Vcc=3V±10% Min. yp. Max. Min. yp. Max. Unit khz µs ms Noise erase valid time (L D pins) ti µs

4 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV-!iming charts t tf thigh L thd : tu : D tl thd : D D (input) tbuf td tdh D (output) L tu : thd : tu : D BI BI Data is read on the rising edge of L. Data is output in synchronization with the falling edge of L. Fig.1 ynchronized data input output timing L D rite data (n address) top condition t tart condition Fig.2 rite cycle timing!ircuit operation (1) tart condition (recognition of start bit) Before executing any command, when L is HIGH, a start condition (start bit) is required to cause D to fall from HIGH to L. his I is designed to constantly detect whether there is a start condition (start bit) for the D and L line, and no commands will be executed unless this condition is satisfied. (ee Fig.1 for the synchronized data input output timing.) (2) top condition (recognition of stop bit) o stop any command, a stop condition (stop bit) is required. stop condition is achieved when D goes from L to HIGH while L is HIGH. his enables commands to be completed. (ee Fig.1 for the synchronized data input output timing.) (3) recautions concerning write commands In the I mode, the transferred data is not written to the memory unless the stop bit is executed.

5 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- (4) Device addressing B2401- F- FJ- FV-, B2402- F- FJ- FV- 1) Make sure the slave address is output from the master immediately after the start condition. 2) he upper four bits of the slave address are used to determine the device type. he device code for this I is fixed at ) he next three bits of the slave address (2, 1, 0 device address) are used to select the device. his I can address up to eight devices on the same bus. 4) he lowermost bit of the slave address ( D I) is used to set the write or read mode as follows. set to 0 rite (andom read word address setting is also 0) set to 1 ead B2404- F- FJ- FV- 1) Make sure the slave address is output from the master in continuation with the start condition. 2) he upper four bits of the slave address are used to determine the device type. he device code for this I is fixed at ) he next two bits of the slave address (2, 1, device address) are used to select the device. his I can address up to four devices on the same bus. 4) he next bit of the slave address ( age elect) is used to select the page. s shown below, it can write to or read from any of the 256 words in the two pages in memory. set to 0 age 1 (000 to 0FF) set to 1 age 2 (100 to 1FF) 5) he lowermost bit of the slave address ( D I) is used to set the write or read mode as follows. set to 0 rite (andom read word address setting is also 0) set to 1 ead (5) rite protect () hen pin set to V (High level), write protect is set by all address. hen pin set to GND (Low level), enable to write to all address. ither control this pin or connect to GND (or V). It is inhibited from being left unconnected. (6) signal he acknowledge signal ( signal) is determined by software and is used to indicate whether or not a data transfer is proceeding normally. he transmitting device, whether the master or slave, opens the bus after an 8-bit data output (µ-m when a write or read command of the slave address input ; this I when reading data). For the receiving device during the ninth clock cycle, D is set to L and an acknowledge signal ( signal) is sent to indicate that it received the 8-bit data (this I when a write command or a read command of the slave address input, µ-m when a read command data output). he Is output a L acknowledge signal ( signal) after recognizing the start condition and slave address (8 bits). hen data is being write to the Is, a L acknowledge signal ( signal) is output after the receipt of each eight bits of data (word address and write data).

6 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- hen data is being read from the I, eight bits of data (read data) are output and the I waits for a returned L acknowledge signal ( signal). hen an acknowledge signal ( signal) is detected and a stop condition is not sent from the master (µ-m) side, the I continues to output data. If an acknowledge signal ( signal) is not detected, the I interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). he I then enters the waiting or standby state. (ee Fig.3 for acknowledge signal ( signal) response.) tart condition (start bit) L (from µ-m) D (µ-m output data) D (I output data) cknowledge signal ( signal) Fig.3 cknowledge ( signal) response (during write and read slave address input) () Byte write cycle B2401- F- FJ- FV- LV DD I D DD D D LIN D Fig.4

7 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- B2402- F- FJ- FV- I LV DD D DD D D LIN D Fig.5 B2404- F- FJ- FV- LV DD I D DD D D LIN D Data is written to the address designated by the word address (n address). fter eight bits of data are input, the data is written to the memory cell by issuing the stop bit. (8) age write cycle B2401- F- FJ- FV- Fig.6 LV DD I D DD(n) D(n) D(n+) D LIN D Fig.

8 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- 8-byte write is possible using this command. h page write command arbitrarily sets the upper four bits (6 to 3) of the word address. he lower three bits (2 and 0) can write up to eight bytes of data with the address being incremented internally. B2402- F- FJ- FV- LV DD I D DD(n) D(n) D(n+) D LIN D Fig.8 8-byte write is possible using this command. h page write command arbitrarily sets the upper five bits ( to 3) of the word address. he lower three bits (2 and 0) can write up to eight bytes of data with the address being incremented internally. B2404- F- FJ- FV- I LV DD D DD(n) D(n) D(n+15) D LIN D Fig.9 16-byte write is possible using this command. h page write command arbitrarily sets the upper four bits ( to 4) of the word address. he lower four bits (3 and 0) can write up to sixteen bytes of data with the address being incremented internally.

9 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- (9) urrent read cycle B2401- F- FJ- FV- LV DD D D D LIN D Fig.10 B2402- F- FJ- FV- LV DD D D D LIN D Fig.11 B2404- F- FJ- FV- LV DD D D D LIN D Fig.12 In case the previous operation is random or current read (which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). hus current read outputs the data of the next word address (n+1). If the last command is byte or page write, the internal address counter stays at the last address (n). hus current read outputs the data of the word address (n). If the master does not transfer the acknowledge but does generate a stop condition, the current address read operation only provides s single byte of data. t this point, this I discontinues transmission. hen an signal L is detected after and a stop condition is not sent from the master (µ-m), the next word address data can be read. [ll words all read enabled] (ee Fig.16 to 18 for the sequential read cycles.) his command is ended by inputting HIGH to the signal after and raising the D signal (stop condition) by setting L to HIGH.

10 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- (10) andom read cycle B2401- F- FJ- FV- I LV DD D DD(n) LV DD D D(n) D LIN D Fig.13 B2402- F- FJ- FV- I LV DD D DD(n) LV DD D D(n) D LIN D Fig.14 B2404- F- FJ- FV- LV DD I D DD(n) LV DD D D(n) D LIN D Fig.15 his command can read the designated word address data. hen an signal L is detected after and a stop condition is not sent from the master (µ-m), the next word address data can be read. [ll words all read enabled] (ee Fig.16 to 18 for the sequential read cycles.) his command is ended by inputting a HIGH signal to the signal after and raising the D signal (stop condition) by raising L to HIGH.

11 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV- (11) equential read cycle (For a current read) B2401- F- FJ- FV- LV DD D D(n) D(n+x) D LIN D D Fig.16 B2402- F- FJ- FV- LV DD D D(n) D(n+x) D LIN D D Fig.1 B2404- F- FJ- FV- LV DD D D(n) D(n+x) D LIN D D Fig.18 hen an signal L is detected after and a stop condition is not sent from the master (µ-m), the next word address data can be read. [ll words can be read] his command is ended by inputting a HIGH signal to the signal after and raising the D signal (stop condition) using the L signal HIGH. equential reading can also be done with a random read.

12 B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- Memory Is B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV-!peration notes (1) During power rise During power rise, the V may rise passing though the low voltage domain in which the I internal circuit does not work. For this reason, there is a risk of misoperation when the power rises without full I internal reset. o prevent this, pay attention to the following points during a power rise. 1) et L = D = HIGH 2) aise the power so as to active the ower n eset (.. ) circuit. Follow the steps below as to operate the... circuit properly. 1) et the power rise time (t) to within 10ms. 2) et the FF domain for once power has been cut to 100m minimum. V tff t (2) D terminal pull-up resistance he D terminal is an open drain output. onsequently, it requires an external pull-up resistance. he appropriate pull-up resistance value is selected from the I VL-IL features., which have been appended as measuring data, as well as VIL and ILI and other personal icons that control the I in question. ecommended values 2.0k to 10k UU VLG : VL (V) UU UN : IL (m) V=3.0V V=5.0V V=3.0V V=5.0V V=3.0V V=5.0V a=85 a=25 a= 40 Fig.19 VL IL features (Note : yp.) Note : ll memory array data are set to FF status at time of shipping.

13 Memory Is B2401- B2401F- B2401FJ- B2401FV- B2402- B2402F- B2402FJ- B2402FV- B2404- B2404F- B2404FJ- B2404FV-!xternal dimensions (Units : mm) B2401- B2402- B ± 0.3 B2401F- B2402F- B2404F ± ± ± Min ± ± ~ ± ± ± ± ± Min ± DI8 8 B2401FJ- B2402FJ- B2404FJ- 4.9 ± B2401FV- B2402FV- B2404FV- 3.0 ± ± ± ± Min ± ± ± ± ± 0.1 (0.52) ± Min ± J8 -B8