Description The PT7C4563 serial real-time clock is a low-power Supports I 2 C-Bus's high speed mode (400 khz)

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1 Real-time lock Module (I 2 Bus) Features Using external kHz quartz crystal Description The PT74563 serial real-time clock is a low-power Supports I 2 -Bus's high speed mode (400 khz) clock/calendar with a programmable square-wave output. Includes time (Hour/Minute/Second) and calendar (Year/Month/Date/Day) counter functions (BD code) Programmable square wave output signal Oscillator stop flag Low backup current: typ. 400n at V DD =3.0V and T =25 Operating range: 1.3V to 5.5V ddress and data are transferred serially via a 2-wire bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in the 24- hour format indicator. Table 1 shows the basic functions of PT More details are shown in section: overview of functions. Table 1. Basic functions of PT74563 Item Function PT Oscillator 2 Time Source: rystal: kHz Oscillator enable/disable - Oscillator fail detect Time display entury bit 12-hour - 24-hour Time count chain enable/disable - 3 Interrupt larm interrupt 4 Programmable square wave output (Hz) 1, 32, 1.024k, k 5 ommunicati on 2-wire I 2 bus Burst mode - ll trademarks are property of their respective owners. 11/10/2016 1

2 Pin onfiguration PT X1 V 8 2 X2 SQW 7 3 INT SL 6 4 GND SD 5 SOI-8, MSOP-8, DIP-8 TSSOP-8, TDFN-8 SOI-8 TSSOP-8 Pin Description Pin no. Pin Type Description 1 X1 I Oscillator ircuit Input. Together with X2, kHz crystal is connected between them. 2 X2 O Oscillator ircuit Output. Together with X1, kHz crystal is connected between them. 3 INT O Interrupt Output. Open drain, active low. 4 GND P Ground. 5 SD I/O Serial Data Input/Output. SD is the input/output pin for the 2-wire serial interface. The SD pin is open-drain output and requires an external pull-up resistor. 6 SL I Serial lock Input. SL is used to synchronize data movement on the I 2 serial interface. 7 SQW O lock Output. Open drain. Four frequencies selectable: k, 1.024k, 32, 1Hz when SQWE bit is set to 1. 8 V P Power. ll trademarks are property of their respective owners. 11/10/2016 2

3 Function Block PT74363 omparator larm Register (Min, Hour, Day, Date) X khz D OS ounter hain Time ounter (Sec,Min,Hour,Day,Date,Month,Year) X2 G INT SQW ontrol Register larm Interrupt ontrol Square Wave Output ontrol ddress Decoder Shift Register ddress Register I /O Interface (I 2 ) SL SD Note: Built in D = G =12pF Maximum Ratings Storage Temperature o to +150 o mbient Temperature with Power pplied o to +85 o Supply Voltage to Ground Potential (Vcc to GND) V to +6.5V D Input (ll Other Inputs except Vcc & GND) V to (V cc +0.3V) D Output Voltage (SD, /INT, /INTB pins) V to +6.5V Power Dissipation mW (Depend on package) Note: Stresses greater than those listed under MXIMUM RTINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating onditions Symbol Description Min. Typ. Max. Unit V Power voltage V IH Input high level 0.7 V - V +0.3 V V IL Input low level V T Operating temperature º ll trademarks are property of their respective owners. 11/10/2016 3

4 D Electrical haracteristics Unless otherwise specified, GND =0V, V = 1.3 ~ 5.5 V, T = -40 to +85, f OS = kHz. Sym. Description Pin onditions Min. Typ. Max. Unit V Supply voltage Supply voltage for clock data integrity I Supply current V Interface inactive. T = 25 1) Interface active. f SL = 400kHz, T = 25 1) V V Interface active Interface inactive (f SL = 0Hz), pin 7 disabled T =-40~85 Interface inactive (f SL = 0Hz), pin 7 enabled at 32kHz T =- 40~85 f SL = 400kHz f SL = 100kHz V = 5.0V V = 3.0V V = 5.0V V = 3.0V V IL1 Low-level input voltage SL V V IH1 High-level input voltage SL - 0.7V - V SD V OL = 0.4V, V = 5V I OL Low-level output voltage /INT, SQW V OL = 0.4V, V = 5V I IL Input leakage current SL I OZ Output current when OFF Note: 1) For reliable oscillator start-up at power-up: V (min)power-up = V (min) V. Electrical haracteristics V n n V m Sym Description Value Unit V HM Rising and falling threshold voltage high 0.8 V V V HL Rising and falling threshold voltage low 0.2 V V Signal V HM V LM t f t r ll trademarks are property of their respective owners. 11/10/2016 4

5 Over the operating range Symbol Item Min. Typ. Max. Unit f SL SL clock frequency khz t SU;ST STRT condition set-up time s t HD;ST STRT condition hold time s t SU;DT Data set-up time (RT read/write) ns t HD;DT1 Data hold time (RT write) ns t HD;DT2 Data hold time (RT read) s t SU;STO STOP condition setup time s t BUF Bus idle time between a STRT and STOP condition s t LOW When SL = "L" s t HIGH When SL = "H" s t r Rise time for SL and SD s t f Fall time for SL and SD s t SP * llowable spike time on bus ns B apacitance load for each bus line pf * Note: Only reference for design. S Sr P t SU;ST SL t LOW f SL t HIGH t HD;ST t SP t BUF SD t HD;ST t SU;DT t HD;DT t SU;ST t SU;STO t HD;ST S Start condition P Stop condition Sr Restart condition ll trademarks are property of their respective owners. 11/10/2016 5

6 Recommended Layout for rystal Note: The crystal, traces and crystal input pins should be isolated from RF generating signals. Built-in apacitors Specifications and Recommended External apacitors Parameter Symbol Typ Unit Build-in capacitors X1 to GND G 12 pf X2 to GND D 12 pf Recommended External capacitors for X1 to GND 1 10 pf crystal L =12.5pF X2 to GND 2 10 pf Recommended External capacitors for X1 to GND 1 0 pf crystal L =6pF X2 to GND 2 0 pf Note: The frequency of crystal can be optimized by external capacitor 1 and 2, for frequency=32.768hz, 1 and 2 should meet the equation as below: par + [( 1+ G)*( 2+ D)]/ [( 1+ G)+( 2+ D)] = L par is all parasitical capacitor between X1 and X2. L is crystal s load capacitance. rystal Specifications Parameter Symbol Min Typ Max Unit Nominal Frequency f O khz Series Resistance ESR k Load apacitance L - 6/ pf ll trademarks are property of their respective owners. 11/10/2016 6

7 Function Description Overview of Functions 1. lock function PU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. ny (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year larm function These devices have one alarm system that outputs interrupt signals from INT for PT74563 to PU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt signal separately at a specified time. The alarm may be selectable between on and off for matching alarm or repeating alarm. 3. Programmable square wave output square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 32, 1.024k, and k Hz. 4. Interface with PU Data is read and written via the I 2 bus interface using two signal lines: SL (clock) and SD (data). Since the output of the I/O pin SD is open drain, a pull-up resistor should be used on the circuit board if the PU output I/O is also open drain. The SL's maximum clock frequency is 400 khz, which supports the I 2 bus's high-speed mode. 5. Oscillator fail detect When oscillator fail, OSF bit will be set. ll trademarks are property of their respective owners. 11/10/2016 7

8 Registers 1. llocation of registers ddr. (hex) *1 Function (time range BD format) Register definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 ontrol/status 1 01 ontrol/status 2 F *2 IE *3 02 Seconds (00-59) OSF *4 S40 S20 S10 S8 S4 S2 S1 03 Minutes (00-59) M40 M20 M10 M8 M4 M2 M1 04 Hours (00-23) H20 H10 H8 H4 H2 H1 05 Dates (01-31) D20 D10 D8 D4 D2 D1 06 Days of the week (00-06) W4 W2 W1 07 Months (01-12) MO10 MO8 MO4 MO2 MO1 08 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 09 larm: Minutes (00-59) E *5 M40 M20 M10 M8 M4 M2 M1 0 larm: Hours (01-12) E *5 H20 H10 H8 H4 H2 H1 0B larm: Dates (01-31) E *5 D20 D10 D8 D4 D2 D1 0 larm: Weekday (00-06) E *5 W4 W2 W1 0D SQW control SQWE RS1 RS0 aution points: *1. PT74563 uses 8 bits for address. For excess 0FH address, PT74563 will not respond. *2. larm interrupt flag bits. *3. larm interrupt enable bits. *4. Oscillator fail indicates. Indicate clock integrity. *5. larm enable bit. larm will be active when related time is matching if E = 0. *6. ll bits marked with "" are not implemented. ll trademarks are property of their respective owners. 11/10/2016 8

9 2. ontrol and status register ddr. (hex) D Description D7 D6 D5 D4 D3 D2 D1 D0 ontrol/status 1 (default) 0 Undefined 0 Undefined 1 Undefined Undefined Undefined ontrol/status 2 F IE (default) Undefined Undefined Undefined 0 Undefined Undefined 0 0 SQW control SQWE RS1 RS0 (default) 1 Undefined Undefined Undefined Undefined Undefined 0 0 a) larm Interrupt IE: larm Interrupt Enable bit. IE Data Description Read / Write 0 larm interrupt disabled 1 larm interrupt enabled Default F: larm Flag F Data Description Read Write 0 larm flag inactive 1 larm flag active 0 larm flag is cleared 1 larm flag remains unchanged b) SQW control SQWE: SQW output clock enable bit. SQWE Data Description Read / Write 0 the SQW output is inhibited and SQW output is set to high-impedance 1 the SQW output is activated Default RS1, RS0: SQW output frequency select. RS1, RS0 Data SQW output freq. (Hz) k Default Read / Write k ll trademarks are property of their respective owners. 11/10/2016 9

10 3. Time ounter Time digit display (in BD code): Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. Hour digits: See description on the /12, 24 bit. arried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. ddr. Description D7 D6 D5 D4 D3 D2 D1 D0 (hex) Seconds OSF *1 S40 S20 S10 S8 S4 S2 S1 (default) 1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Minutes M40 M20 M10 M8 M4 M2 M1 (default) 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Hours H20 H10 H8 H4 H2 H1 (default) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined *1 Note: Indicate clock integrity. When the bit is 1, the clock integrity is no longer guaranteed and the time need be adjusted. 4. Days of the week ounter The day counter is a divide-by-7 counter that counts from 00 to 06 and up 06 before starting again from 00. Values that correspond to the day of week are user defined but must be sequential (i.e., if 0 equals Sunday, then 1 equals Monday, and so on). Illogical time and date entries result in undefined operation. ddr. (hex) 06 Description D7 D6 D5 D4 D3 D2 D1 D0 Days of the week W4 W2 W1 (default) Undefined Undefined Undefined 5. alendar ounter The data format is BD format. Day digits: Range from 1 to 31 (for January, March, May, July, ugust, October and December). Range from 1 to 30 (for pril, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). arried to month digits when cycled to 1. Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. Year digits: Range from 00 to 99 and 00, 04, 08,, 92 and 96 are counted as leap years. ddr. (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 Dates D20 D10 D8 D4 D2 D1 (default) 0 0 Undefined Undefined Undefined Undefined Undefined Undefined Months M10 M8 M4 M2 M1 (default) Undefined 0 0 Undefined Undefined Undefined Undefined Undefined Years Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined ll trademarks are property of their respective owners. 11/10/

11 6. larm Register PT74563: larm Register ddr. Description D7 D6 D5 D4 D3 D2 D1 D larm: Minutes E *1 M40 M20 M10 M8 M4 M2 M1 (default) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined larm: Hours E *2 H20 H10 H8 H4 H2 H1 (default) Undefined 0 Undefined Undefined Undefined Undefined Undefined Undefined 0B 0 larm: Dates E *3 D20 D10 D8 D4 D2 D1 (default) Undefined 0 Undefined Undefined Undefined Undefined Undefined Undefined larm: Weekday E *4 W4 W2 W1 *1 Note: Minute alarm enable bit. *2 Note: Hour alarm enable bit. *3 Note: Date alarm enable bit. *4 Note: Weekday alarm enable bit. (default) Undefined Undefined Undefined Undefined larm Function Related register Function Register definition Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01 ontrol/status 2 F IE 02 Seconds OSF S40 S20 S10 S8 S4 S2 S1 03 Minutes M40 M20 M10 M8 M4 M2 M1 04 Hours H20 H10 H8 H4 H2 H1 05 Dates D20 D10 D8 D4 D2 D1 06 Days of the week W4 W2 W1 09 larm: Minutes E M40 M20 M10 M8 M4 M2 M1 0 larm: Hours E H20 H10 H8 H4 H2 H1 0B larm: Dates E D20 D10 D8 D4 D2 D1 0 larm: Weekday E W4 W2 W1 When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit larm Enable (E) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled comparisons first match, the larm Flag (F) is set. F will remain set until cleared by software. Once F has been cleared it will only be set again when the time increments to match the alarm condition once more. larm registers which have their bit E at logic 1 will be ignored. ll trademarks are property of their respective owners. 11/10/

12 ommunication 1. I 2 Bus Interface a) Overview of I 2 -BUS The I 2 bus supports bi-directional communications via two signal lines: the SD (data) line and SL (clock) line. combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SL and SD signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SD while SL is at high level. During data transfers, data changes that occur on the SD line are performed while the SL line is at low level, and on the receiving side the data is captured while the SL line is at high level. In either case, the data is transferred via the SL line at a rate of one bit per clock pulse. The I 2 bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. b) System onfiguration ll ports connected to the I 2 bus must be either open drain or open collector ports in order to enable ND connections to multiple devices. SL and SD are both connected to the VDD line via a pull-up resistance. onsequently, SL and SD are both held at high level when the bus is released (when communication is not being performed). Vcc R P R P SD SL Master MU Slave RT Other Peripheral Device Note: When there is only one master, the MU is ready for driving SL to "H" and R P of SL may not required. Fig.1 System configuration ll trademarks are property of their respective owners. 11/10/

13 c) Starting and Stopping I 2 Bus ommunications Fig.2 Starting and stopping on I 2 bus STRT condition, repeated STRT condition, and STOP condition STRT condition SD level changes from high to low while SL is at high level STOP condition SD level changes from low to high while SL is at high level Repeated STRT condition (RESTRT condition) In some cases, the STRT condition occurs between a previous STRT condition and the next STOP condition, in which case the second STRT condition is distinguished as a RESTRT condition. Since the required status is the same as for the STRT condition, the SD level changes from high to low while SL is at high level. d) Data Transfers and cknowledge Responses during I 2 -BUS ommunication Data transfers Data transfers are performed in 8-bit (1 byte) units once the STRT condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the STRT condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SD line is performed while the SL line is at low level. The receiver (receiving side) captures data while the SL line is at high level. *Note with caution that if the SD data is changed while the SL line is at high level, it will be treated as a STRT, RESTRT, or STOP condition. ll trademarks are property of their respective owners. 11/10/

14 Data acknowledge response ( signal) When transferring data, the receiver generates a confirmation response ( signal, low active) each time an 8-bit data segment is received. If there is no signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SL line, the transmitter releases the SD line and the receiver sets the SD line to low (= acknowledge) level. SL from Master SD from transmitter (sending side) Release SD SD from receiver (receiving side) Low active signal fter transmitting the signal, if the Master remains the receiver for transfer of the next byte, the SD is released at the falling edge of the clock corresponding to the 9th bit of data on the SL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. t that point, the transmitter continues to release the SD and awaits a STOP condition from the Master. e) Slave ddress The I 2 bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. ll communications begin with transmitting the [STRT condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. n R/W bit is added to each 7-bit slave address during 8-bit transfers. Slave address Operation Transfer data R / W bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read 3 h 1 (= Read) Write 2 h 0 (= Write) 2. I 2 Bus s Basic Transfer Format S Start indication P Stop indication RT cknowledge Sr Restart indication Master cknowledge ll trademarks are property of their respective owners. 11/10/

15 a) Write via I 2 bus S Slave address (7 bits) write ddr. setting bit bit bit bit bit bit bit bit P Start Slave address + write specification ddress Specifies the write start address. Write data Stop b) Read via I 2 bus Standard read S Slave address (7 bits) write ddr. setting Start Slave address + write specification ddress Specifies the read start address. Sr Slave address (7 bits) Read bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit / P Restart Slave address + read specification Data read (1) Data is read from the specified start address and address auto increment. Data read (2) ddress auto increment to set the address for the next data to be read. N O Stop Simplified read S Slave address (7 bits) Read bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit / P Start Slave address + read specification Data read (1) Data is read from the address pointed by the internal address register and address auto increment. Data read (2) ddress register auto increment to set the address for the next data to be read. N O Stop Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications H, 4H are used as test mode address. ustomer should not use the addresses. ll trademarks are property of their respective owners. 11/10/

16 Mechanical Information W (SOI-8) ll trademarks are property of their respective owners. 11/10/

17 L (TSSOP-8) ll trademarks are property of their respective owners. 11/10/

18 U (MSOP-8) ll trademarks are property of their respective owners. 11/10/

19 ZE (Lead free and Green 8-Pin TDFN) Note: For latest package info, please check: Ordering Information Part Number Package ode Package PT74563WE W 8-Pin, 150mil Wide (SOI) PT74563WEX W 8-Pin, 150mil Wide (SOI), Tape/Reel PT74563UE U 8-Pin, Mini Small Outline Package (MSOP) PT74563UEX U 8-Pin, Mini Small Outline Package (MSOP), Tape/Reel PT74563LE L 8-Pin, 173mil Wide (TSSOP) PT74563LEX L 8-Pin, 173mil Wide (TSSOP), Tape/Reel PT74563ZEE ZE 8-Pin, 2x3 (TDFN) PT74563ZEEX ZE 8-Pin, 2x3 (TDFN), Tape/Reel Note: Thermal characteristics can be found on the company web site at E = Pb-free and Green dding X Suffix= Tape/Reel ll trademarks are property of their respective owners. 11/10/