WLCSP EEPROM BRCB032GWZ-3

Transcription

1 erial EEPOM eries tandard EEPOM WLP EEPOM BB32GWZ-3 General Description BB32GWZ-3 is a 32bit serial EEPOM of I 2 BU Interface Method Features ll ontrols vailable by 2 Ports of erial lock (L) and serial data (D) Other Devices than EEPOM can be onnected to the ame Port, aving Microcontroller Port 1.6V to 5.5V ingle Power ource Operation Most uitable for Battery Use 1MHz action is possible (1.7V to 5.5V) Up to 32 Byte in Page Write Mode Bit Format 4 x 8 elf-timed Programming ycle Low urrent onsumption Prevention of Write Mistake Write (Write Protect) Function dded Prevention of write mistake at low voltage More than 1 Million Write ycles More than 4 Years Data etention Noise Filter Built in L / D erminal Initial Delivery tate FFh Packages W(yp) x D(yp) x H(Max) UP3L1 1.45mm x.77mm x.33mm BB32GWZ-3 apacity Bit Format ype Power ource Voltage Package 32bit 4 8 BB32GWZ-3 1.6V to 5.5V UP3L1 Product structure:ilicon monolithic integrated circuit his product has no designed protection against radioactive rays 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

2 BB32GWZ-3 bsolute Maximum atings (a=25 ) Parameter ymbol ating Unit emark upply Voltage V -.3 to +6.5 V Power Dissipation Pd.22(UP3L1) W Derate by 2.2mW/ when operating above a=25 torage emperature stg -65 to +125 Operating emperature opr -4 to +85 Input Voltage/ Output Voltage to Vcc+1. V he Max value of Input Voltage/Output Voltage is not over 6.5V. When the pulse width is 5ns or less, the Min value of Input Voltage/Output Voltage is not below 1.V. Junction emperature jmax 15 Junction temperature at the storage condition Electrostatic discharge voltage (human body model) VED -4 to +4 V aution: Operating the I over the absolute maximum ratings may damage the I. he damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. herefore, it is important to consider circuit protection measures, such as adding a fuse, in case the I is operated over the absolute maximum ratings. Memory ell haracteristics (a=25, Vcc=1.6V to 5.5V) Parameter Limit Min yp Max Unit Write ycles (Note1) 1,, - - imes Data etention (Note1) Years (Note1) Not 1% EED ecommended Operating atings Parameter ymbol ating Unit Power ource Voltage Vcc 1.6 to 5.5 Input Voltage V IN to Vcc V D haracteristics (Unless otherwise specified, a=-4 to +85, Vcc=1.6V to 5.5V) Parameter ymbol Limit Min yp Max Unit onditions Input High Voltage1 V IH1.7Vcc - Vcc+1. V 1.7V Vcc 5.5V Input Low Voltage1 V IL1 -.3 (Note2) - +.3Vcc V 1.7V Vcc 5.5V Input High Voltage2 V IH2.8Vcc - Vcc+1. V 1.6V Vcc<1.7V Input Low Voltage2 V IL2 -.3 (Note2) - +.2Vcc V 1.6V Vcc<1.7V Output Low Voltage1 V OL V I OL =3.m, 2.5V Vcc 5.5V (D) Output Low Voltage2 V OL V I OL =.7m, 1.6V Vcc<2.5V (D) Input Leakage urrent I LI µ V IN = to Vcc Output Leakage urrent I LO µ V OU = to Vcc (D) upply urrent (Write) I m Vcc=5.5V, f L =1MHz, t W =5ms, Byte Write, Page Write upply urrent (ead) I m Vcc=5.5V, f L =1MHz andom ead, current ead, equential ead WP=GND or Vcc tandby urrent I B µ Vcc=5.5V, D L=Vcc WP=GND or Vcc, 2=GND or Vcc (Note2) When the pulse width is 5ns or less, it is -1.V. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

3 BB32GWZ-3 haracteristics (Unless otherwise specified, a=-4 to +85, Vcc=1.6V to 5.5V) Parameter ymbol Limits (1.6V Vcc<1.7V) Limits (1.7V Vcc 5.5V) Min. yp. Max. Min. yp. Max. lock Frequency fl khz Data lock HIGH Period thigh µs Data lock LOW Period tlow µs D, L (INPU) ise ime (Note1) t µs D, L (INPU) Fall ime (Note1) tf µs D (OUPU) Fall ime (Note1) tf µs tart ondition Hold ime thd: µs tart ondition etup ime tu: µs Input Data Hold ime thd:d ns Input Data etup ime tu:d ns Output Data Delay ime tpd µs Output Data Hold ime tdh µs top ondition etup ime tu:o µs Bus Free ime tbuf µs Write ycle ime tw ms Noise pike Width (D, L) ti µs WP Hold ime thd:wp µs WP etup ime tu:wp µs WP High Period thigh:wp µs (Note1) Not 1% EED. ondition Input Data Level: V IL =.2 Vcc V IH =.8 Vcc Input Data iming eference Level:.3 Vcc/.7 Vcc Output Data iming eference Level:.3 Vcc/.7 Vcc ise/fall ime : 2ns Unit erial Input / Output iming t tf1 thigh L 7% 7% 7% 7% 7% 7% D (INPU) ( 入力 ) 7% D (OUPU) ( 出力 ) tbuf thd: 7% 7% 3% 3% 3% 3% tlow tu:d Input read at the rise edge of L tf2 Data output in sync with the fall of L Figure 1.-(a). erial Input / Output iming tpd 7% 3% thd:d 7% 3% tdh 7% 3% 3% 3% D(1) D1 D 3% tu:wp D(n) tw Figure 1.-(d). WP iming at Write Execution 7% 3% thd:wp OP ONDIION 7% 7% 7% D(1) D(n) tu: thd: tu:o D1 D thigh:wp 7% tw 7% 3% 3% 7% 7% ONDIION OP ONDIION Figure 1.-(b) tart-top Bit iming Figure 1.-(e). WP iming at Write ancel D 7% 7% write data (n-th address) tw OP ONDIION ONDIION Figure 1.-(c). Write ycle iming 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

4 BB32GWZ-3 Block Diagram 64bit 32 EEPOM Y Vcc 13bit 12bit 8bit DDE DEODE 12bit 13bit LVE, WOD DDE EGIE D EGIE WP E 2 ONOL LOGI OP L GND HIGH VOLGE GEN. V LEVEL DEE D Figure 2. Block Diagram Pin onfiguration B B1 B2 B3 D GND L WP V Figure 3. Pin onfiguration (BOOM VIEW) Pin Descriptions Land No. erminal Name Input / Output Descriptions B3 2 Input lave address setting B2 GND - eference voltage of all input / output, V B1 D Input / Output lave and word address erial data input, serial data output 3 V - Power upply 2 WP Input Write protect terminal 1 L Input erial clock input *WP and 2 are not allowed to use as open. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

5 BB32GWZ-3 ypical Performance urves 6 6 Input High Voltage : V IH1,2(V) a=-4 a= 25 a= 85 Input Low Voltage1,2: V IL1,2 (V) a=-4 a= 25 a= upply Voltage: Vcc(v) upply Voltage: Vcc(v) Figure 4. Input High Voltage1,2, vs upply Voltage Figure 5. Input Low Voltage1,2 vs upply Voltage 1 1 Output Low Voltage1: V OL1 (V) a=-4 a= 25 a= 85 Output Low Voltage2: V OL2 (V) a=-4 a= 25 a= Output Low urrent: I OL (m) Output Low urrent: I OL (m) Figure 6. Output Low Voltage1 vs Output Low urrent (Vcc=2.5V) Figure 7. Output Low Voltage2 vs Output Low urrent (Vcc=1.6V) 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

6 BB32GWZ-3 ypical Performance urves continued Input Leakage urrent: I LI (μ) a=-4 a= 25 a= 85 Output Leakage urrent: I LO (µ) a=-4 a= 25 a= upply Voltage: Vcc(V) upply Voltage: Vcc(v) Figure 8. Input Leakage urrent vs upply Voltage (L, WP, 2) Figure 9. Output Leakage urrent vs upply Voltage (D) upply urrent (Write) : Icc1(m) a=-4 a= 25 a= 85 upply urrent (ead) : I2(m) a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage : Vcc(V) Figure 1. upply urrent (Write) vs upply Voltage (f L =1MHz) Figure 11. upply urrent (ead) vs upply Voltage (f L =1MHz) 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

7 BB32GWZ-3 ypical Performance urves continued tandby urrent: I B (µ) a=-4 a= 25 a= 85 lock Frequency: f L (khz) a=-4 a= 25 a= upply Voltage: Vcc(V) upply Voltage: Vcc(V) Figure 12. tandby urrent vs upply Voltage Figure 13. lock Frequency vs upply Voltage.4.6 Data lock High Period : thigh(µs) a=-4 a= 25 a= 85 Data lock Low Period : tlow(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage : Vcc(V) Figure 14. Data lock High Period vs upply Voltage Figure 15. Data lock Low Period vs upply Voltage 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

8 BB32GWZ-3 ypical Performance urves continued D (OUPU) Fall ime : tf2(µs) a=-4 a= 25 a= 85 tart ondition Hold ime : thd:(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) Figure 16. D (OUPU) Fall ime vs upply Voltage upply Voltage : Vcc(V) Figure 17. tart ondition Hold ime vs upply Voltage.14 5 tart ondition etup ime : t U: (µs) a=-4 a= 25 a= 85 Input Data Hold ime : thd:d (ns) -5-1 a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage: Vcc(V) Figure 18. tart ondition etup ime vs upply Voltage Figure 19. Input Data Hold ime vs upply Voltage (HIGH) 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

9 BB32GWZ-3 ypical Performance urves continued 5 6 Input Data Hold ime : thd:d(ns) -5-1 a=-4 a= 25 a= 85 Input Data etup ime : tu:d(ns) a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage : Vcc(V) Figure 2. Input Data Hold ime vs upply Voltage (LOW) Figure 21. Input Data etup ime vs upply Voltage (HIGH) Input Data etup ime : t U:D (ns) a=-4 a= 25 a= 85 Output Data Delay ime : tpd(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage : Vcc(V) Figure 22. Input Data etup ime vs upply Voltage (LOW) Figure 23. Output Data Delay ime vs upply Voltage (LOW) 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

10 BB32GWZ-3 ypical Performance urves continued.5.3 Output Data Delay ime : tpd1(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) top ondition etup ime : tu:o(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) Figure 24. Output Data Delay ime vs upply Voltage (HIGH) Figure 25. top ondition etup ime vs upply Voltage Bus Free ime : t BUF(µs) a=-4 a= 25 a= 85 Write ycle ime : t W (ms) a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage : Vcc(V) Figure 26. Bus Free ime vs upply Voltage Figure 27. Write ycle ime vs upply Voltage 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

11 BB32GWZ-3 ypical Performance urves continued.3.3 Noise pike Width(L HIGH) : ti(µs) a=-4 a= 25 a= 85 Noise pike Width(L LOW) : ti(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage : Vcc(V) Figure 28. Noise pike Width vs upply Voltage (L HIGH) Figure 29. Noise pike Width vs upply Voltage (L LOW).3.3 Noise pike Width(D HIGH) : (µs) I t a=-4 a= 25 a= 85 Noise pike WidthI(D LOW) : t(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) Figure 3. Noise pike Width vs upply Voltage (D HIGH) upply Voltage : Vcc(V) Figure 31. D Noise pike Width (LOW) vs upply Voltage (D LOW) 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

12 BB32GWZ-3 ypical Performance urves continued WP Hold ime : thd:wp(µs) a=-4 a= 25 a= 85 WP etup ime : tu:wp(µs) a=-4 a= 25 a= upply Voltage : Vcc(V) upply Voltage : Vcc(V) Figure 32. WP Hold ime vs upply Voltage Figure 33. WP etup ime vs upply Voltage 1.2 WP High Period : thigh:wp ( µs) a=-4 a= 25 a= upply Voltage : Vcc(V) Figure 34. WP High Period vs upply Voltage 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

13 BB32GWZ-3 iming hart 1. I 2 BU Data ommunication I 2 BU data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I 2 BU data communication with several devices is possible by connecting with 2 communication lines: serial data (D) and serial clock (L). mong the devices, there should be a master that generates clock and control communication start and end. he rest become slave which are controlled by an address peculiar to each device, like this EEPOM. he device that outputs data to the bus during data communication is called transmitter, and the device that receives data is called receiver. D L DDE /W D D condition Figure 35. Data ransfer iming P OP condition 2. tart ondition (tart Bit ecognition) (1) Before executing each command, start condition (start bit) where D goes from 'HIGH' down to 'LOW' when L is 'HIGH' is necessary. (2) his I always detects whether D and L are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command cannot be executed. 3. top ondition (top Bit ecognition) (1) Each command can be ended by a stop condition (stop bit) where D goes from 'LOW' to 'HIGH' while L is 'HIGH'. 4. cknowledge () ignal (1) he acknowledge () signal is a software rule to show whether data transfer has been made normally or not. In a master-slave communication, the device (Ex. µ-om sends slave address input for write or read command, to this I ) at the transmitter (sending) side releases the bus after output of 8bit data. (2) he device (Ex. his I receives the slave address input for write or read command from the µ-om) at the receiver (receiving) side sets D 'LOW' during the 9th clock cycle, and outputs acknowledge signal ( signal) showing that it has received the 8bit data. (3) his I, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( signal) 'LOW'. (4) fter receiving 8bit data (word address and write data) during each write operation, this I outputs acknowledge signal ( signal) 'LOW'.. (5) During read operation, this I outputs 8bit data (read data) and detects acknowledge signal ( signal) 'LOW'. When acknowledge signal ( signal) is detected, and stop condition is not sent from the master (µ-om) side, this I continues to output data. When acknowledge signal ( signal) is not detected, this I stops data transfer, recognizes stop condition (stop bit), and ends read operation. hen this I becomes ready for another transmission. 5. Device ddressing (1) lave address comes after start condition from master. (2) he significant 4 bits of slave address are used for recognizing a device type. he device code of this I is fixed to '11'. (3) Next slave addresses (2 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. (4) he most insignificant bit ( / W --- ED / WIE ) of slave address is used for designating write or read operation, and is as shown below. etting etting / W to write (setting to word address setting of random read) / W to read lave address Maximum number of onnected buses /W OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

14 BB32GWZ-3 Write ommand 1. Write ycle (1) rbitrary data can be written to this EEPOM. When writing only 1 byte, Byte Write is normally used, and when writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. Up to 32 arbitrary bytes can be written. LVE DDE W I E 1st WOD DDE 2nd WOD DDE D O P D LINE W W * * * * D7 D 11 *Don't are bit / W Figure 36. Byte Write ycle D LINE LVE DDE W I E 2nd WOD DDE(n) W W D7 D D 11 / W 1st WOD DDE(n) * * * * D(n) D(n+31) O P *Don't are bit Figure 37. Page Write ycle (2) During internal write execution, all input commands are ignored, therefore is not returned. (3) Data is written to the address designated by word address (n-th address) (4) By issuing stop bit after 8bit data input, internal write to memory cell starts. (5) When internal write is started, command is not accepted for t W (5ms at maximum). (6) Using page write cycle, writing in bulk is done as follows: When data of more than 32 bytes is sent, the bytes in excess overwrites the data already sent first. (efer to "Internal ddress Increment".) (7) s for page write cycle where 2 or more bytes of data is intended to be written, after the 8 significant bits of word address are designated arbitrarily, only the value of 5 least significant bits in the address is incremented internally, so that data up to 32 addresses of memory only can be written. 1 page=32bytes, but the page Write ycle ime is 5ms at maximum for 32byte bulk write. It does not stand 5ms at maximum 32byte=16ms(Max) 2. Internal ddress Increment Page Write Mode W7 W6 W5 W4 W3 W2 W1 W 1 1 Increment 1Eh ignificant bit is fixed. No digit up For example, when it is started from address 1Eh, then, increment is made as below, 1Eh 1Fh h 1h please take note. 1Eh 1E in hexadecimal, therefore, 1111 becomes a binary number. 3. Write Protect (WP) erminal Write Protect (WP) Function When WP terminal is set at Vcc (H level), data rewrite of all addresses is prohibited. When it is set at GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not leave it open. t extremely low voltage at power ON / OFF, by setting the WP terminal 'H', write error can be prevented. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

15 BB32GWZ-3 ead ommand 1. ead ycle ead cycle is when data of EEPOM is read. ead cycle could be random read cycle or current read cycle. andom read cycle is a command to read data by designating a specific address, and is used generally. urrent read cycle is a command to read data of internal address register without designating an address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in succession. D LINE LVE DDE W I E 1st WOD DDE ( ) 2nd WOD DDE(n) D(n) W W 1 1 * * * * D7 D LVE DDE E D O P *Don't are bit / W / W D LINE LVE DDE Figure 38. andom ead ycle E D D7 D(n) D O P / W Figure 39. urrent ead ycle LVE DDE E D D(n) D(n+x) O P D LINE D7 D D7 D / W Figure 4. equential ead ycle (in the case of urrent ead ycle) (1) In andom ead ycle, data of designated word address can be read. (2) When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address, is output. (3) When signal 'LOW' after D is detected, and stop condition is not sent from master (µ-om) side, the next address data can be read in succession. (4) ead cycle is ended by stop condition where 'H' is input to signal after D and D signal goes from L to H while L signal is 'H'. (5) When 'H' is not input to signal after D, sequential read gets in, and the next data is output. herefore, read command cycle cannot be ended. o end the read command cycle, be sure to input 'H' to signal after D, and the stop condition where D goes from L to H while L signal is 'H'. (6) equential read is ended by stop condition where 'H' is input to signal after arbitrary D and D is asserted from L to H while L signal is 'H'. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

16 BB32GWZ-3 oftware eset oftware reset is executed to avoid malfunction after power on and during command input. oftware reset has several kinds and 3 kinds of them are shown in the figure below. (efer to Figure 41.-(a), Figure 41.-(b), and Figure 41.-(c).) Within the dummy clock input area, the D bus is released ('H' by pull up) and output and read data '' (both 'L' level) may be output from EEPOM. herefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clock 14 tart 2 L D Normal command Normal command Figure 41.-(a) he case of dummy clock command input tart Dummy clock 9 tart L D Normal command Normal command Figure 41.-(b) he case of + dummy clock command input tart 9 L D D Figure 41.-(c) 9 + command input Normal command Normal command tart command from input. cknowledge Polling During internal write execution, all input commands are ignored, therefore is not returned. During internal automatic write execution after write cycle input, next command (slave address) is sent. If the first signal sends back 'L', then it means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge polling, next command can be executed without waiting for tw = 5ms. o write continuously, / W =, then to carry out current read cycle after write, slave address with / W = 1 is sent. If signal sends back 'L', then execute word address input and data output and so forth. First write command During internal write, = HIGH is returned. Write ommand O P lave ddress lave H ddress tw econd write command H lave ddress tw H lave ddress L Word ddress L Data L O P fter completion of internal write, =LOW is returned, so input next word address and data in succession. Figure 42. ase of continuous write by cknowledge Polling 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

17 BB32GWZ-3 WP Valid iming (Write ancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, pay attention to the following WP valid timing. During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D of data(in page write cycle, the first byte data) is the cancel invalid area. WP input in this area becomes Don't care. he area from the rise of L to take in D to the stop condition input is the cancel valid area. Furthermore, after the execution of forced end by WP, the I enters standby status. ise of D taken clock ise of D L L D D1 D D D Enlarged view Enlarged view D WP lave ddress L Word ddress L D7 D6 D5 D4 D3 D2 D1 D WP cancel invalid area L Data WP cancel valid area Data is not written. L O P t W WP cancel invalid area Figure 43. WP Valid iming ommand ancel by tart ondition and top ondition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure 44.) However, within output area and during data read, D bus may output 'L'. In this case, start condition and stop condition cannot be input, so reset is not available. herefore, execute software reset. When command is cancelled by start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined. herefore, it is not possible to carry out current read cycle in succession. o carry out read cycle in succession, carry out random read cycle. L D 1 1 tart condition top condition Figure 44. ase of cancel by start, stop condition during lave ddress Input 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

18 BB32GWZ-3 I/O Peripheral ircuit 1. Pull Up esistance of D erminal D is NMO open drain, so it requires a pull up resistor. s for this resistance value ( PU ), select an appropriate value from microcontroller V IL, I L, and V OL -I OL characteristics of this I. If PU is large, operating frequency is limited. he smaller the PU, the larger is the supply current (ead). 2. Maximum Value of PU he maximum value of PU is determined by the following factors: (1)D rise time to be determined by the capacitance ( BU ) of bus line and PU of D should be t or lower. Furthermore, timing should be satisfied even when D rise time is slow. (2)he bus electric potential to be determined by the input current leak total (I L ) of the device connected to the bus with output of 'H' to the D line and PU should sufficiently secure the input 'H' level (V IH ) of microcontroller and EEPOM including recommended noise margin of.2vcc. V - IL PU PU -.2V.8V I L -V IH V Ex.) Vcc =3V IL=1µ VIH=.7 Vcc from(2) PU IH [ k Ω] Microcontroller IL PU Figure 45. I/O ircuit Diagram IL Bus Line apacity BU EEPOM D terminal 3. Minimum Value of PU he minimum value of PU is determined by the following factors: (1)When I outputs LOW, it should be satisfied that V OLMX =.4V and I OLMX =3m. V -V PU OL PU V I OL -V IOL OL (2)VOLMX=.4V should secure the input 'L' level (V IL ) of microcontroller and EEPOM including the recommended noise margin of.1vcc. VOLMX VIL -. 1 V Ex.) V =3V, V OL =.4V, I OL =3m, microcontroller, EEPOM V IL =.3Vcc from (1) PU [ Ω] nd VOL =.4 [ V ] VIL =.3 3 =.9 [ V ] herefore, the condition (2) is satisfied. 4. Pull-up esistance of L erminal When L control is made at the MO output port, there is no need for a pull up resistor. But when there is a time where L becomes 'Hi-Z', add a pull up resistor. s for the pull up resistor value, one of several kω to several ten kω is recommended in consideration of drive performance of output port of microcontroller. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

19 BB32GWZ-3 autions on Microcontroller onnection 1. In I 2 BU, it is recommended that D port is of open drain input/output. However, when using MO input / output of tri state to D port, insert a series resistance between the pull up resistor PU and the D terminal of EEPOM. his is to control over current that may occur when PMO of the microcontroller and NMO of EEPOM are turned ON simultaneously. also plays the role of protecting the D terminal against surge. herefore, even when D port is open drain input/output, can be used. PU L D 'H' output of microcontroller 'L' output of EEPOM Microcontroller EEPOM Figure 46. I/O ircuit Diagram Over current flows to D line by 'H' output of microcontroller and 'L' output of EEPOM. Figure 47. Input / Output ollision iming 2. Maximum Value of he maximum value of is determined by the following relations: (1)D rise time to be determined by the capacitance ( BU ) of bus line and PU of D should be t or lower. Furthermore, timing should be satisfied even when D rise time is slow. (2)he bus electric potential to be determined by PU and the moment when EEPOM outputs 'L' to D bus should sufficiently secure the input 'L' level (V IL ) of microcontroller including recommended noise margin of.1vcc. V IL V Micro controller PU I OL Bus line capacity BU V OL EEPOM Figure 48. I/O ircuit Diagram ( V -VOL) + VOL +.1V PU + VIL -VOL -.1V 1.1V -VIL PU V Ex)V=3V V IL =.3V V OL =.4V PU =2kΩ [ k Ω] 3 IL 3. Minimum Value of he minimum value of is determined by over current at bus collision. When over current flows, noises in power source line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source line in set and so forth. et the over current to EEPOM at 1m or lower. PU 'L'output Over current I 'H' output Microcontroller EEPOM Figure 49. I/O circuit diagram V I V s I EX) V =3V I=1m 3 s [ Ω] 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

20 BB32GWZ-3 I/O Equivalence ircuit 1. Input (L, WP, 2) Figure 5. Input Pin ircuit Diagram 2. Input / Output (D) Figure 51. Input / Output Pin ircuit Diagram 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

21 BB32GWZ-3 Power-Up/Down onditions t power on, the I s internal circuits may go through unstable low voltage area as the Vcc rises, making the I s internal logic circuit not completely reset, hence, malfunction may occur. o prevent this, the I is equipped with PO circuit and LV circuit. o assure the operation, observe the following conditions at power on. 1. et D = 'H' and L ='L' or 'H 2. tart power source so as to satisfy the recommended conditions of t, t OFF, and V bot for operating PO circuit. V t ecommended conditions of t, t OFF,V bot t t OFF V bot toff Vbot 1ms or below 1ms or larger.3v or below 1ms or below 1ms or larger.2v or below Figure 52. ise Waveform Diagram 3. et D and L so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. (1) In the case when the above condition 1 cannot be observed such that D becomes 'L' at power on. ontrol L and D as shown below, to make L and D, 'H' and 'H'. V t LOW L D fter Vcc becomes stable fter Vcc becomes stable t DH t U:D t U:D Figure 53. When L= 'H' and D= 'L' Figure 54. When L='L' and D='L' (2) In the case when the above condition 2 cannot be observed. fter power source becomes stable, execute software reset(page 16). (3) In the case when the above conditions 1 and 2 cannot be observed. arry out (1), and then carry out (2). Low Voltage Malfunction Prevention Function LV circuit prevents data rewrite operation at low power and prevents write error. t LV voltage (yp =1.2V) or below, data rewrite is prevented. Noise ountermeasures 1. Bypass apacitor When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a bypass capacitor (.1µF) between the I s Vcc and GND pins. onnect the capacitor as close to the I as possible. In addition, it is also recommended to attach a bypass capacitor between the board s Vcc and GND. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

22 BB32GWZ-3 Operational Notes 1. everse onnection of Power upply onnecting the power supply in reverse polarity can damage the I. ake precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the I s power supply pins. 2. Power upply Lines Design the PB layout pattern to provide low impedance supply lines. eparate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to ground at all power supply pins. onsider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. lso ensure that the ground traces of external components do not cause variations on the ground voltage. he ground lines must be as short and thick as possible to reduce line impedance. 5. hermal onsideration hould by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. he absolute maximum rating of the Pd stated in this specification is when the I is mounted on a 7mm x 7mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the Pd rating. 6. ecommended Operating onditions hese conditions represent a range within which the expected characteristics of the I can be approximately obtained. he electrical characteristics are guaranteed under the conditions of each parameter. 7. Inrush urrent When power is first supplied to the I, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the I has more than one power supply. herefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under trong Electromagnetic Field Operating the I in the presence of a strong electromagnetic field may cause the I to malfunction. 9. esting on pplication Boards When testing the I on an application board, connecting a capacitor directly to a low-impedance output pin may subject the I to stress. lways discharge capacitors completely after each process or step. he I s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. o prevent damage from static discharge, ground the I during assembly and use similar precautions during transport and storage. 1. Inter-pin hort and Mounting Errors Ensure that the direction and position are correct when mounting the I on the PB. Incorrect mounting may result in damaging the I. void nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

23 BB32GWZ-3 Operational Notes continued 11. Unused Input Pins Input pins of an I are often connected to the gate of a MO transistor. he gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. he small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the I. o unless otherwise specified, unused input pins should be connected to the power supply or ground line. 12. egarding the Input Pin of the I In the construction of this I, P-N junctions are inevitably formed creating parasitic diodes or transistors. he operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage. herefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power supply voltage is applied to the I. Even if the power supply voltage is applied, make sure that the input pins have voltages within the values specified in the electrical characteristics of this I. 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

24 BB32GWZ-3 Part Numbering B B 3 2 G W Z - 3 E 2 BU type :I 2 evision apacity 32=32 Package GWZ:UP3L1 Process ode Packaging and forming specification E2:: Embossed tape and reel 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

25 BB32GWZ-3 Physical Dimension ape and eel Information Package Name UP3L1(BB32GWZ-3) 1PIN M Lot No. DG 1.45±.5.77± MX.6 6-φ.2±.5.5 B.185±.5 B B ±.5 P=.4 2 (Unit : mm) < ape and eel Information > ape Embossed carrier tape Quantity 3pcs Direction of feed E2 he direction is the pin 1 of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand eel 1pin Direction of feed 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

26 BB32GWZ-3 Marking Diagram UP3L1(BB32GWZ-3) (OP VIEW) 1PIN M Part Number Marking DG LO Number evision History Date evision hanges 18.Mar New elease 214 OHM o., Ltd. ll rights reserved. Z /26 Z221-2G Mar.214 ev.1

27 Notice Precaution on using OHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as V equipment, O equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ( pecific pplications ), please consult with the OHM sales representative in advance. Unless otherwise agreed in writing by OHM in advance, OHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any OHM s Products for pecific pplications. (Note1) Medical Equipment lassification of the pecific pplications JPN U EU HIN LⅢ LⅡb LⅢ LⅢ LⅣ LⅢ 2. OHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. he following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below. ccordingly, OHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any OHM s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including l2, H2, NH3, O2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] ealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. he Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. void applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation (Pd) depending on mbient temperature (a). When used in sealed area, confirm the actual ambient temperature. 8. onfirm that operation temperature is within the specified range described in the product specification. 9. OHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / ircuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the OHM representative in advance. For details, please refer to OHM Mounting specification Notice GE 213 OHM o., Ltd. ll rights reserved. ev.2

28 Precautions egarding pplication Examples and External ircuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. herefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. OHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic his Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for torage / ransportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including l2, H2, NH3, O2, and NO2 [b] the temperature or humidity exceeds those recommended by OHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under OHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. tore / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label Q code printed on OHM Products label is for OHM s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign rade act ince our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with OHM representative in case of export. Precaution egarding Intellectual Property ights 1. ll information and data including but not limited to application example contained in this document is for reference only. OHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. OHM shall not be in any way responsible or liable for infringement of any intellectual property rights or other damages arising from use of such information or data.: 2. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of OHM or any third parties with respect to the information contained in this document. Other Precaution 1. his document may not be reprinted or reproduced, in whole or in part, without prior written consent of OHM. 2. he Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of OHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. he proper names of companies or products described in this document are trademarks or registered trademarks of OHM, its affiliated companies or third parties. Notice GE 213 OHM o., Ltd. ll rights reserved. ev.2

29 General Precaution 1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents. OHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny OHM s Products against warning, caution or note contained in this document. 2. ll information contained in this docume nt is current as of the issuing date and subj ect to change without any prior notice. Before purchasing or using OHM s Products, please confirm the la test information with a OHM sale s representative. 3. he information contained in this doc ument is provi ded on an as is basis and OHM does not warrant that all information contained in this document is accurate an d/or error-free. OHM shall not be in an y way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such information. Notice WE 214 OHM o., Ltd. ll rights reserved. ev.1