TSZ R2R0G

Transcription

1 erial EEPROM eries tandard EEPROM I 2 BU EEPROM (2-Wire) General Description is an 8bit serial EEPROM of I 2 BU interface. Features Packages W (yp) x D(yp) x H(Max) ompletely conforming to the world standard I 2 BU. ll controls available by 2 ports of serial clock (L) and serial data () Other devices than EEPROM can be connected to the same port, saving microcontroller port.6v to 5.5V ingle Power ource Operation most suitable for battery use.6v to 5.5V wide limit of operating voltage, possible F MODE 4Hz operation Up to 6Byte in Page Write Mode Bit Format x 8 elf-timed Programming ycle Low urrent onsumption Prevention of Write Mistake Write (Write Protect) Function dded Prevention of Write Mistake at Low Voltage More than million write cycles More than 4 years data retention Noise Filter Built in L / erminal Initial delivery state FFh DIP-8 9.3mm x 6.5mm x 7.mm OP8 5.mm x 6.2mm x.7mm OP- J8M 4.9mm x 6.mm x.8mm OP-B8 3.mm x 6.4mm x.2mm OP-B8M 3.mm x 6.4mm x.mm OP-B8J 3.mm x 4.9mm x.mm OP- J8 4.9mm x 6.mm x.65mm MOP8 2.9mm x 4.mm x.9mm OP-B8 3.mm x 6.4mm x.35mm VON8X23 2.mm x 3.mm x.6mm Figure. Product structure:ilicon monolithic integrated circuit his product has not designed protection against radioactive rays Z22 4 /36

2 bsolute Maximum Ratings (a=25 ) Parameter ymbol Rating Unit Remark upply Voltage V -.3 to +6.5 V Power Dissipation Pd.45 (OP8) torage emperature stg -65 to +5 Operating emperature opr -4 to +85 Input Voltage / Output Voltage Junction emperature Electrostatic discharge voltage (human body model) Derate by 4.5mW/ when operating above a=25.45 (OP-J8M) Derate by 4.5mW/ when operating above a=25.45 (OP-J8) Derate by 4.5mW/ when operating above a=25.3 (OP-B8) Derate by 3.mW/ when operating above a=25.33 (OP-B8) Derate by 3.3mW/ when operating above a=25 W.33 (OP-B8M) Derate by 3.3mW/ when operating above a=25.3 (OP-B8J) Derate by 3.mW/ when operating above a=25.3 (MOP8) Derate by 3.mW/ when operating above a=25.3 (VON8X23) Derate by 3.mW/ when operating above a=25.8 (DIP-8) Derate by 8.mW/ when operating above a= to V+. V he Max value of Input voltage/ Output voltage is not over 6.5V. When the pulse width is 5ns or less the Min value of Input voltage/output voltage is not below -.8V. jmax 5 Junction temperature at the storage condition VED -4 to +4 V Memory ell haracteristics (a=25, V=.6V to 5.5V) Parameter Limit Min yp Max Unit Write ycles (),, - - imes Data Retention () Years ()Not % EED Recommended Operating Ratings Parameter ymbol Rating Unit Power ource Voltage V.6 to 5.5 V Input Voltage VIN to V D haracteristics (Unless otherwise specified, to +85, V=.6V to 5.5V) Parameter ymbol Limit Min yp Max Input High Voltage VIH.7V - V+. V.7V V 5.5V Input Low Voltage VIL -.3 (2) - +.3V V.7V V 5.5V Input High Voltage2 VIH2.8V - V+. V.6V V<.7V Input Low Voltage2 VIL2 -.3 (2) -.2V V.6V V<.7V Unit onditions Output Low Voltage VOL V IOL=3.m, 2.5V V 5.5V () Output Low Voltage2 VOL V IOL=.7m,.6V V<2.5V () Input Leakage urrent ILI - - µ VIN= to V Output Leakage urrent ILO - - µ VOU= to V () upply urrent (Write) I m V=5.5V, fl=4khz, twr=5ms, Byte write, Page write upply urrent (Read) I m V=5.5V, fl=4khz Random read, current read, sequential read tandby urrent IB µ V=5.5V, L=V,,2=GND,WP=GND (2) When the pulse width is 5ns or less, it is -.8V. 2/36

3 haracteristics (Unless otherwise specified, to +85, V=.6V to 5.5V) Parameter ymbol Limit Min yp Max lock Frequency fl khz Data lock High Period thigh µs Data lock Low Period tlow µs, L (INPU) Rise ime () tr - -. µs, L (INPU) Fall ime () tf - -. µs (OUPU) Fall ime () tf µs tart ondition Hold ime thd: µs tart ondition etup ime tu: µs Input Data Hold ime thd:d - - ns Input Data etup ime tu:d - - ns Output Data Delay ime tpd. -.9 µs Output Data Hold ime tdh. - - µs top ondition etup ime tu:o µs Bus Free ime tbuf µs Write ycle ime twr ms Noise pike Width ( and L) ti - -. µs WP Hold ime thd:wp. - - µs WP etup ime tu:wp. - - µs WP High Period thigh:wp. - - µs () Not % EED. ondition Input data level:vil=.2 Vcc VIH=.8 Vcc Input data timing reference level:.3 Vcc/.7 Vcc Output data timing reference level:.3 Vcc/.7 Vcc Rise/Fall time : 2ns Unit erial Input / Output iming tr tf thigh L 7% 7% 7% 7% 7% 7% (INPU) ( 入力 ) 3% 3% 3% thd: tlow tu:d 7% 7% 3% tbuf tpd 3% thd:d 7% 3% tdh D 7% D() D D(n) 7% twr (OUPU) ( 出力 ) (output) Input read at the rise edge of L Data output in sync with the fall 3% of L 7% 7% Figure 2-(a). erial Input / Output iming 7% 3% 7% 3% 3% 3% tf2 3% 3% tu:wp thd:wp OP ONDIION Figure 2-(d). WP iming at Write Execution 7% 7% tu: thd: 7% 3% 7% tu:o 3% D() D(n) D D thigh:wp 7% 7% Fig-(4) Write 7% cycle timing 7% 7% 7% twr 3% R ONDIION OP ONDIION Figure 2-(b). tart-top Bit iming R ONDIION 3% OP ONDIION Fig-(5) WP timing at write execution Fig-(6) WP timing at write cancel Figure 2-(e). WP iming at Write ancel D 7% 7% write data (n-th address) twr OP ONDIION R ONDIION Figure 2-(c). Write ycle iming Fig-(5) WP timing at write execution Fig-(6) WP timing at write cancel 3/36

4 Block Diagram 8bit EEPROM rray 8 V 8bit 2 ddress Decoder bit Word ddress Register Data Register 7 WP 2 3 R ontrol ircuit OP 6 L GND 4 High Voltage Generating circuit Power ource Voltage Detection 5 Figure 3. Block Diagram Pin onfiguration (OP VIEW) 8 V WP L GND 4 5 Pin Descriptions erminal Name Input/ Output - Don t use () - Don t use () 2 Input lave address setting (2) Descriptions GND - Reference voltage of all input / output, V Input/ Output erial data input serial data output L Input erial clock input WP Input Write protect terminal V - onnect the power source. () Pins not used as device address may be set to any of High, Low, and High-Z states (2) 2 is not allowed to use as open. 4/36

5 ypical Performance urves 6 6 Input High Voltage,2: VIH,2(V) Input Low Voltage,2: VIL,2(V) PIN MR Figure 4. Input High Voltage,2 vs. upply Voltage (2, L,, WP) Figure 5. Input Low Voltage,2 vs. upply Voltage (2, L,, WP) Output Low Voltage: VOL(V) Output Low Voltage2: VOL2(V) Output Low urrent: I OL (m) Output Low urrent: I OL (m) Figure 6. Output Low Voltage vs. Output Low urrent (V=2.5V) Figure 7. Output Low Voltage2 vs. Output Low urrent (V=.6V) 5/36

6 ypical Performance urves ontinued.2.2 Input Leakage urrent: I LI (µ) Output Leakage urrent: I LO(µ) Figure 8. Input Leakage urrent vs. upply Voltage (2, L, WP) Figure 9. Output Leakage urrent vs. upply Voltage () 3.6 upply urrent (Write) : Icc(m) upply urrent (Read) : I2(m) upply Voltage: Vcc(V) Figure. upply urrent (Write) vs. upply Voltage (fl=4khz) Figure. upply urrent (Read) vs. upply Voltage (fl=4khz) 6/36

7 ypical Performance urves ontinued 2.5 tandby urrent: I B (µ) lock Frequency: fl(khz) Figure 2. tandby urrent vs. upply Voltage Figure 3. lock Frequency vs. upply Voltage.5 Data lock High Period : t HIGH(µs) Data lock Low Period : t LOW(µs) upply Voltage: Vcc(V) Figure 4. Data lock High Period vs upply Voltage Figure 5. Data lock Low Period vs. upply Voltage 7/36

8 ypical Performance urves ontinued tart ondition Hold ime: t HD:(µs) tart ondition etup ime: t U: (µs) upply Voltage: Vcc(V) Figure 6. tart ondition Hold ime vs. upply Voltage Figure 7. tart ondition etup ime vs. upply Voltage 5 5 Input Data Hold ime: t HD:D (ns) Input Data Hold ime: t HD:D(ns) Figure 8. Input Data Hold ime vs. upply Voltage (HIGH) Figure 9. Input Data Hold ime vs. upply Voltage (LOW) 8/36

9 ypical Performance urves ontinued 3 3 Input Data etup ime: t U:D(ns) 2 - Input Data etup ime: t U:D(ns) Figure 2. Input Data etup ime vs. upply Voltage (HIGH) Figure 2. Input Data etup ime vs. upply Voltage (LOW) 2 2 Output Data Delay ime: t PD(µs).5.5 Output Data Delay ime: t PD (µs) Figure 22. Output Data Delay ime vs. upply Voltage (LOW) Figure 23. Output Data Delay ime vs. upply Voltage (HIGH) 9/36

10 ypical Performance urves ontinued 2 2 top ondition etup ime: t U:O(µs).5.5 Bus Free ime : t BUF(µs) Figure 24. top ondition etup ime vs. upply Voltage Figure 25. Bus Free ime vs. upply Voltage 6.6 Write ycle ime: t WR(ms) Noise pike Width(L HIGH):tI(µs) Figure 26. Write ycle ime vs. upply Voltage Figure 27. Noise pike Width vs. upply Voltage (L HIGH) /36

11 ypical Performance urves ontinued.6.6 Noise pike Width(L LOW): ti(µs) Noise pike Width( HIGH): ti(µs) upply Voltage: Vcc(V) Figure 28. Noise pike Width vs. upply Voltage (L LOW) Figure 29. Noise pike Width vs. upply Voltage ( HIGH).6.2 Noise pike Width( LOW): ti(µs) WP Hold ime: t HD:WP(µs) Figure 3. Noise pike Width vs. upply Voltage ( LOW) Figure 3. WP Hold ime vs. upply Voltage /36

12 ypical Performance urves ontinued.2.2. WP etup ime: t U:WP(µs) WP High Period: t HIGH:WP ( µs) Figure 32. WP etup ime vs. upply Voltage Figure 33. WP High Period vs. upply Voltage 2/36

13 iming hart. I 2 BU Data ommunication I 2 BU data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I 2 BU carries out data transmission with several devices is possible by connecting with 2 communication lines: serial data () and serial clock (L). mong the devices, there should be a master that generates clock and control communication start and end. he rest become slave which are controlled by an address peculiar to each device like this EEPROM. he device that outputs data to the bus during data communication is called transmitter, and the device that receives data is called receiver. L Figure 34. Data ransfer iming 2. tart ondition (tart Bit Recognition) () Before executing each command, start condition (start bit) where goes from 'HIGH' down to 'LOW' when L is 'HIGH' is necessary. (2) his I always detects whether and L are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command cannot be executed. 3. top ondition (top Bit Recongnition) () Each command can be ended by a stop condition (stop bit) where goes from Low to High while L is High. 4. cknowledge () ignal () he acknowledge () signal is a software rule to show whether data transfer has been made normally or not. In master-slave communication, the device (Ex.µ-OM sends slave address input for write or read command to this I) at the transmitter (sending) side releases the bus after output of 8bit data. (2) he device (Ex. his I receives the slave address input of write or read command from the µ-om) at the receiver (receiving) side sets 'LOW' during the 9th clock cycle, and outputs acknowledge signal ( signal) showing that it has received the 8bit data. (3) his I, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( signal) 'LOW'. (4) fter receiving 8bit data (word address and write data) during each write operation, this I outputs acknowledge signal ( signal) LOW. (5) During read operation, this I outputs 8bit data (read data), and detects acknowledge signal ( signal) 'LOW'. When acknowledge signal ( signal) is detected, and stop condition is not sent from the master (µ-om) side, this I continues to output data. When acknowledge signal ( signal) is not detected, this I stops data transfer, recognizes stop cindition (stop bit), and ends read operation. hen this I becomes ready for another transmission. 5. Device ddressing () lave address comes after start condition from master. (2) he significant 4 bits of slave address are used for recognizing a device type. he device code of this I is fixed to ''. (3) Next slave addresses (2 --- device address) are for selecting devices, and multiple devices can be used on a same bus according to the number of device addresses. (4) he most insignificant bit ( R / W --- RED / WRIE ) of slave address is used for designating write or read operation, and is as shown below. etting etting R / W to write (setting to word address setting of random read) R / W to read lave address Maximum number of onnected buses 2 P P R/W 2 P and P are page select bits. R DDRE R/W condition D D P OP condition 3/36

14 Write ommand. Write ycle () rbitrary data can be written to this EEPROM. When writing only byte. Byte Write is normally used, and when writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. he maximum number of bytes is specified per device of each capacity. Up to 6 arbitrary bytes can be written. R LVE DDRE W R I E WORD DDRE D O P LINE 2 P P W 7 W D7 D R / W Figure 35. Byte Write ycle R LVE DDRE W R I E WORD DDRE(n) D(n) D(n+5) O P LINE 2 P P W W D7 D 7 D R / W Figure 36. Page Write ycle (2) During internal write execution, all input commands are ignored, therefore is not returned. (3) Data is written to the address designated by word address (n-th address) (4) By issuing stop bit after 8bit data input, internal write to memory cell starts. (5) When internal write is started, command is not accepted for twr (5ms at maximum). (6) Using page write cycle, writing in bulk is done as follows: When data or more than 6Byte is sent, the bytes in excess overwrites the data already sent first.(refer to "Internal address increment") (7) s for page write cycle of where 2 or more bytes of data are intended to be written, after page select bit P,P of slave address are designated arbitrarily, only the 4 least significant bits in the address are incremented internally, so that data up to 6 bytes of memory only can be written. In the case, page=6bytes, but the page write cycle time is 5ms at maximum for 6byte bulk write. It does not stand 5ms at maximum 6byte=8ms(Max) 2. Internal ddress Increment Page write mode (in the case of ) W7 W4 W3 W2 W W Increment Eh ignificant bit is fixed. No digit up For example, when it is started from address Eh, then, increment is made as below, Eh Fh h h please take note. Eh E in hexadecimal, therefore, becomes a binary number. 3. Write Protect (WP) erminal Write Protect (WP) Function When WP terminal is set at V (H level), data rewrite of all addresses is prohibited. When it is set at GND (L level), data rewrite of all addresses is enabled. Be sure to connect this terminal to V or GND, or control it to H level or L level. Do not leave it open. In case using of it as ROM, it is recommended to connect it to pull up or V. t extremely low voltage at power ON / OFF, by setting the WP terminal 'H', write error can be prevented. 4/36

15 Read ommand. Read ycle Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random read cycle is a command to read data by designating a specific address, and is used generally. urrent read cycle is a command to read data of internal address register without designating an address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in succession. LINE R LVE DDRE 2 P P W R I E R / W W 7 WORD DDRE(n) W Figure 37. Random Read ycle R LVE DDRE 2 R E D R / W D7 D(n) D O P R LVE DDRE R E D D(n) O P LINE 2 P P D7 D R / W Figure 38. urrent Read ycle R LVE DDRE R E D D(n) D(n+x) O P LINE 2 P P D7 D D7 D R / W Figure 39. equential Read ycle (in the case of current read cycle) () In random read cycle, data of designated word address can be read. (2) When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+)-th address is output. (3) When signal 'LOW' after D is detected, and stop condition is not sent from master (µ-om) side, the next address data can be read in succession. (4) Read cycle is ended by stop condition where 'H' is input to signal after D and signal goes from L to H while L signal is 'H'. (5) When 'H' is not input to signal after D, sequential read gets in, and the next data is output. herefore, read command cycle cannot be ended. o end read command cycle, be sure to input H to signal after D, and the stop condition where goes from L to H while L signal is 'H'. (6) equential read is ended by stop condition where 'H' is input to signal after arbitrary D and is asserted from L to H while L signal is 'H'. 5/36

16 oftware Reset oftware reset is executed to avoid malfunction after power on, and during command input. oftware reset has several kinds and 3 kinds of them are shown in the figure below. (Refer to Figure 4-(a), Figure 4-(b), Figure 4-(c).) Within dummy clock input area, the bus is released ('H' by pull up) and output and read data '' (both 'L' level) may be output from EEPROM. herefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clock 4 tart 2 L Normal command Normal command Figure 4-(a). he ase of Dummy lock 4 + R+R+ ommand Input tart Dummy clock 9 tart L Normal command Normal command Figure 4-(b). he ase of R + Dummy clock 9 + R + ommand Input tart 9 L D Figure 4-(c). R 9 + ommand Input Normal command Normal command tart command from R input. cknowledge Polling During internal write execution, all input commands are ignored, therefore is not returned. During internal automatic write execution after write cycle input, next command (slave address) is sent. If the first signal sends back 'L', then it means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge polling, next command can be executed without waiting for twr = 5ms. o write continuously, R / W =, then to carry out current read cycle after write, slave address R / W = is sent. If signal sends back 'L', and then execute word address input and data output and so forth. First write command During internal write, = HIGH is sent back. R Write command O P R lave address H R lave address H t WR econd write command R lave address H R lave address L Word address L Data L O P t WR fter completion of internal write, =LOW is sent back, so input next word address and data in succession. Figure 4. ase of ontinuously Write by cknowledge Polling 6/36

17 WP Valid iming (Write ancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, pay attention to the following WP valid timing. During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D of data(in page write cycle, the first byte data) is the cancel invalid area. WP input in this area becomes Don't care. he area from the rise of L to take in D to the stop condition input is the cancel valid area. Furthermore, after the execution of forced end by WP, the I enters standby status. Rise of D taken clock Rise of L L D D Enlarged view D Enlarged view WP R lave address L Word address L D7 D6 D5 D4 D3 D2 D D WP cancel invalid area L Data WP cancel valid area Data is not written. L O P t WR WP cancel invalid area Figure 42. WP Valid iming ommand ancel by tart ondition and top ondition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure 43.) However, within output area and during data read, bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. herefore, execute software reset. When command is cancelled by start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined. herefore, it is not possible to carry out current read cycle in succession. o carry out read cycle in succession, carry out random read cycle. L tart condition top condition Figure 43. ase of ancel by tart, top ondition during lave ddress Input 7/36

18 I/O Peripheral ircuit. Pull Up Resistance of erminal is NMO open drain, so it requires a pull up resistor. s for this resistance value (RPU), select an appropriate value from microcontroller VIL, IL, and VOL-IOL characteristics of this I. If RPU is large, operating frequency is limited. he smaller the RPU, the larger is the supply current (Read). 2. Maximum Value of RPU he maximum value of RPU is determined by the following factors. () rise time to be determined by the capacitance (BU) of bus line of RPU and should be tr or lower. Furthermore, timing should be satisfied even when rise time is slow. (2) he bus electric potential to be determined by the input leak total (IL) of the device connected to the bus with output of 'H' to line and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin of.2vcc. V-ILRPU-.2 V VIH RPU.8Vcc-VIH IL Microcontroller BR24GXX Ex.) Vcc =3V IL=µ VIH=.7 Vcc From (2) RPU -6 IL RPU IL terminal 3 [kω] Bus line capacity BU Figure 44. I/O ircuit Diagram 3. Minimum Value of RPU he minimum value of RPU is determined by the following factors. () When I outputs LOW, it should be satisfied that VOLMX=.4V and IOLMX=3m. Vcc-VOL RPU RPU IOL Vcc-VOL IOL (2) VOLMX=.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin.vcc. VOLMX VIL-. V Ex.) V =3V, VOL=.4V, IOL=3m, microcontroller, EEPROM VIL=.3Vcc from() 3-.4 RPU [Ω] nd VOL=.4[V] VIL=.3 3 =.9[V] herefore, the condition (2) is satisfied. 4. Pull Up Resistance of L erminal When L control is made at the MO output port, there is no need for a pull up resistor. But when there is a time where L becomes 'Hi-Z', add a pull up resistor. s for the pull up resistor value, one of several kω to several ten kω is recommended in consideration of drive performance of output port of microcontroller. 8/36

19 autions on Microcontroller onnection. R In I 2 BU, it is recommended that port is of open drain input/output. However, when using MO input / output of tri state to port, insert a series resistance R between the pull up resistance RPU and the terminal of EEPROM. his is to control over current that may occur when PMO of the microcontroller and NMO of EEPROM are turned ON simultaneously. R also plays the role of protecting the terminal against surge. herefore, even when port is open drain input/output, R can be used. RPU R L 'H' output of microcontroller 'L' output of EEPROM Microcontroller EEPROM Figure 45. I/O circuit diagram Over current flows to line by 'H' output of microcontroller and 'L' output of EEPROM. Figure 46. Input / output collision timing 2. Maximum Value of Rs he maximum value of Rs is determined by the following relations. () rise time to be determined by the capacitance (BU) of bus line of RPU and should be tr or lower. Furthermore, timing should be satisfied even when rise time is low. (2) he bus electric potential to be determined by RPU and R the moment when EEPROM outputs 'L' to bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin.vcc. V RPU R VOL (Vcc-VOL) R RPU+R R +VOL+.Vcc VIL VIL-VOL-.Vcc.Vcc-VIL RPU VIL Micro controller IOL Bus line capacity BU EEPROM Figure 47. I/O ircuit Diagram Ex)V=3V VIL=.3V VOL=.4V RPU=2kΩ R [kΩ] 3. Minimum Value of Rs he minimum value of R is determined by over current at bus collision. When over current flows, noises in power source line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source line in set and so forth. et the over current to EEPROM at m or lower. 'H' output R PU R Over current I 'L'output Vcc R I R Vcc I EX) V=3V I=m R 3-3 Microcontroller EEPROM 3[Ω] Figure 48. I/O ircuit Diagram 9/36

20 I/O Equivalence ircuit. Input (2, L, WP) Figure 49. Input Pin ircuit Diagram 2. Input / Output () Figure 5. Input / Output Pin ircuit Diagram 2/36

21 Power Up/Down onditions t power on, the I s internal circuits may go through unstable low voltage area as the V rises, making the I s internal logic circuit not completely reset, hence, malfunction may occur. o prevent this, the I is equipped with POR circuit and LV circuit. o assure the operation, observe the following conditions at power on.. et = 'H' and L ='L' or 'H 2. tart power source so as to satisfy the recommended conditions of tr, toff, and Vbot for operating POR circuit. V tr toff Vbot Figure 5. Rise Waveform Diagram Recommended conditions of tr, toff,vbot tr toff Vbot ms or below ms or larger.3v or below ms or below ms or larger.2v or below 3. et and L so as not to become 'Hi-Z'. When the above conditions and 2 cannot be observed, take the following countermeasures. () In the case when the above condition cannot be observed such that becomes 'L' at power on. ontrol L and as shown below, to make L and, 'H' and 'H'. V tlow L fter Vcc becomes stable fter Vcc becomes stable tdh tu:d tu:d Figure 52. When L= 'H' and = 'L' Figure 53. When L='L' and ='L' (2) In the case when the above condition 2 cannot be observed. fter power source becomes stable, execute software reset(page6). (3) In the case when the above conditions and 2 cannot be observed. arry out (), and then carry out (2). Low Voltage Malfunction Prevention Function LV circuit prevents data rewrite operation at low power and prevents write error. t LV voltage (yp =.2V) or below, data rewrite is prevented. Noise ountermeasures. Bypass apacitor When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a bypass capacitor (.µf) between I s V and GND pins. onnect the capacitor as close to the I as possible. In addition, it is also recommended to connect a bypass capacitor between the board s V and GND. 2/36

22 Operational Notes. Reverse onnection of Power upply onnecting the power supply in reverse polarity can damage the I. ake precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the I s power supply pins. 2. Power upply Lines Design the PB layout pattern to provide low impedance supply lines. eparate the ground and supply lines of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog block. Furthermore, connect a capacitor to ground at all power supply pins. onsider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. lso ensure that the ground traces of external components do not cause variations on the ground voltage. he ground lines must be as short and thick as possible to reduce line impedance. 5. hermal onsideration hould by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. he absolute maximum rating of the Pd stated in this specification is when the I is mounted on a 7mm x 7mm x.6mm glass epoxy board. In case of exceeding this absolute maximum rating, increase the board size and copper area to prevent exceeding the Pd rating. 6. Recommended Operating onditions hese conditions represent a range within which the expected characteristics of the I can be approximately obtained. he electrical characteristics are guaranteed under the conditions of each parameter. 7. Inrush urrent When power is first supplied to the I, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the I has more than one power supply. herefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. Operation Under trong Electromagnetic Field Operating the I in the presence of a strong electromagnetic field may cause the I to malfunction. 9. esting on pplication Boards When testing the I on an application board, connecting a capacitor directly to a low-impedance output pin may subject the I to stress. lways discharge capacitors completely after each process or step. he I s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. o prevent damage from static discharge, ground the I during assembly and use similar precautions during transport and storage.. Inter-pin hort and Mounting Errors Ensure that the direction and position are correct when mounting the I on the PB. Incorrect mounting may result in damaging the I. void nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 22/36

23 Operational Notes continued. Unused Input Pins Input pins of an I are often connected to the gate of a MO transistor. he gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. he small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the I. o unless otherwise specified, unused input pins should be connected to the power supply or ground line. 2. Regarding the Input Pin of the I In the construction of this I, P-N junctions are inevitably formed creating parasitic diodes or transistors. he operation of these parasitic elements can result in mutual interference among circuits, operational faults, or physical damage. herefore, conditions which cause these parasitic elements to operate, such as applying a voltage to an input pin lower than the ground voltage should be avoided. Furthermore, do not apply a voltage to the input pins when no power supply voltage is applied to the I. Even if the power supply voltage is applied, make sure that the input pins have voltages within the values specified in the electrical characteristics of this I. 23/36

24 Part Numbering B R 2 4 G 8 x x x - 3 x x x x x BU type 24:I 2 Operating temperature/ Operating Voltage -4 to +85 /.6V to 5.5V apacity 8=8 Package Blank : DIP-8 F : OP8 FV : OP-B8 FVJ : OP-B8J NUX : VON8X23 Process ode N Blank G : Halogen free Blank : Not Halogen free s an exception, OP-J8M, OP-B8M, VON8X23 package will be Halogen free with Blank Blank : % n : % n FJ FV FVM : OP-J8M/OP-J8 : OP-B8/OP-B8M : MOP8 : OP-J8M, OP-B8M : DIP-8, OP8, OP-J8, OP-B8, OP-B8, OP-B8J, MOP8, VON8X23 Packaging and Forming pecification E2 : Embossed tape and reel (OP8, OP-J8M, OP-J8, OP-B8, OP-B8, OP-B8M, OP-B8J) R : Embossed tape and reel (MOP8, VON8X23) None : ube (DIP-8) Lineup apacity 8 Package ype Quantity Orderable Part Number Remark DIP-8 ube of 2 BR24G8-3 Not Halogen free % n OP8 Reel of 25 BR24G8F -3GE2 Halogen free % n OP-J8M Reel of 25 BR24G8FJ -3NE2 Halogen free % n OP-J8 Reel of 25 BR24G8FJ -3GE2 Halogen free % n OP-B8 Reel of 25 BR24G8FV -3GE2 Halogen free % n OP-B8 Reel of 3 BR24G8FV -3GE2 Halogen free % n OP-B8M Reel of 3 BR24G8FV -3NE2 Halogen free % n OP-B8J Reel of 25 BR24G8FVJ -3GE2 Halogen free % n MOP8 Reel of 3 BR24G8FVM -3GR Halogen free % n VON8X23 Reel of 4 BR24G8NUX -3R Halogen free % n 24/36

25 Physical Dimension, ape and Reel Information Package Name DIP-8 25/36

26 Physical Dimension, ape and Reel Information Package Name OP8 (Max 5.35 (include.burr)) (UNI : mm) PG : OP8 Drawing No. : EX /36

27 Physical Dimension, ape and Reel Information Package Name OP-J8M 27/36

28 Physical Dimension, ape and Reel Information Package Name OP-J8 28/36

29 Physical Dimension, ape and Reel Information Package Name OP-B8 29/36

30 Physical Dimension, ape and Reel Information Package Name OP-B8 3/36

31 Physical Dimension, ape and Reel Information Package Name OP-B8M 3/36

32 Physical Dimension, ape and Reel Information Package Name OP-B8J 32/36

33 Physical Dimension, ape and Reel Information Package Name MOP8 33/36

34 Physical Dimension ape and Reel Information Package Name VON8X23 34/36

35 Marking Diagrams (OP VIEW) DIP-8 (OP VIEW) OP8 (OP VIEW) Part Number Marking BR24G8 4 G 8 LO Number Part Number Marking LO Number PIN MR OP-J8M (OP VIEW) Part Number Marking OP-J8 (OP VIEW) Part Number Marking 4 G 8 LO Number 4 G 8 LO Number PIN MR PIN MR OP-B8 (OP VIEW) Part Number Marking 4 G D LO Number OP-B8 (OP VIEW) Part Number Marking 4 G 8 LO Number PIN MR PIN MR OP-B8M (OP VIEW) Part Number Marking 4 G 8 LO Number OP-B8J (OP VIEW) Part Number Marking 4 G 8 3 LO Number PIN MR PIN MR 35/36

36 Marking Diagrams (OP VIEW) MOP8 (OP VIEW) VON8X23 (OP VIEW) 4 G D Part Number Marking LO Number 4 G 8 3 Part Number Marking LO Number PIN MR PIN MR Revision History Date Revision hanges 5.Jun.22 New Release 9.Mar.23 2 Update some English words, sentences descriptions, grammar and formatting. dd tf2 in haracteristic and erial Input / Output iming Update Fig. to Fig.4 3.May.23 3 P hange format of package line-up table. P.2 dd VED in bsolute Maximum Ratings P.4 dd directions in Pin Descriptions 27.Oct.24 4 dd OP-J8M,OP-B8M Package P.dd 8bit to a General Description P.dd Up to 6 Byte in Page Write Mode P.dd Bit Format x 8 P. List of models deletion P2. hange the unit of Power Dissipation to W P22. hange the Operational Notes hange notice to Rev3 36/36

37 Notice Precaution on using ROHM Products. Our Products are designed and manufactured for application in ordinary electronic equipments (such as V equipment, O equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note ), transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ( pecific pplications ), please consult with the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM s Products for pecific pplications. (Note) Medical Equipment lassification of the pecific pplications JPN U EU HIN LⅢ LⅡb LⅢ LⅢ LⅣ LⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. he following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below. ccordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM s Products under any special or extraordinary environments or conditions. If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including l2, H2, NH3, O2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] ealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. he Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mounting is strongly recommended. void applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation (Pd) depending on mbient temperature (a). When used in sealed area, confirm the actual ambient temperature. 8. onfirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / ircuit board design. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification Notice-GE 23 ROHM o., Ltd. ll rights reserved. Rev.3

38 Precautions Regarding pplication Examples and External ircuits. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. herefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic his Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for torage / ransportation. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including l2, H2, NH3, O2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. tore / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label QR code printed on ROHM Products label is for ROHM s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign rade act ince our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act, please consult with ROHM representative in case of export. Precaution Regarding Intellectual Property Rights. ll information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable for infringement of any intellectual property rights or other damages arising from use of such information or data.: 2. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the information contained in this document. Other Precaution. his document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. he Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. he proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice-GE 23 ROHM o., Ltd. ll rights reserved. Rev.3

39 General Precaution. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents. ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny ROHM s Products against warning, caution or note contained in this document. 2. ll information contained in this docume nt is current as of the issuing date and subj ect to change without any prior notice. Before purchasing or using ROHM s Products, please confirm the la test information with a ROHM sale s representative. 3. he information contained in this doc ument is provi ded on an as is basis and ROHM does not warrant that all information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such information. Notice WE 24 ROHM o., Ltd. ll rights reserved. Rev.