I 2 C BUS BR24 family

Transcription

1 High eliability erial EEOMs I 2 BU B24 family B24 eries No.E2 Description B24 -W series is a serial EEOM of I 2 BU interface method Features ) ompletely conforming to the world standard I 2 BU. ll controls available by 2 ports of serial clock (L) and serial data(d) 2) Other devices than EEOM can be connected to the same port, saving microcontroller port 3).7V~5.5V single power source action most suitable for battery use 4).7V~5.5Vwide limit of action voltage, possible F MODE 4Hz action 5) age write mode useful for initial value write at factory shipment 6) uto erase and auto end function at data write 7) Low current consumption 8) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage 9) DI-8/O8/O-J8/O-B8/O-B8/O-B8J/MO8/VON8X23 various packages ) Data rewrite up to,, times ) Data kept for 4 years 2) Noise filter built in L / D terminal 3) hipment data all address FFh B24 series apacity Bit format ype ower source Voltage DI-8 O8 O-J8 O-B8 O-B8 O-B8J MO8 bit 28 8 B24-W.7~5.5V 2bit B242-W.7~5.5V 4bit 52 8 B244-W.7~5.5V 8bit 8 B248-W.7~5.5V 6bit 2 8 B246-W.7~5.5V 32bit 4 8 B2432-W.7~5.5V 64bit 8 8 B2464-W.7~5.5V 28bit 6 8 B2428-W.7~5.5V 256bit 32 8 B24256-W.7~5.5V 52bit 64 8 B2452-W.7~5.5V 24bit 28 8 B24M-W.7~5.5V :Developing VON8 X23 2 OHM o., Ltd. ll rights reserved. / ev.

2 B24 eries echnical Note bsolute maximum ratings (a=25 ) arameter ymbol atings Unit Impressed voltage V -.3~+6.5 V ermissible dissipation torage temperature range ction temperature range d 45 (O8) * 45 (O-J8) *2 3 (O-B8) *3 33 (O-B8) *4 3 (O-B8J) *5 3 (MO8) *6 3 (VON8X23) *7 8 (DI-8) *8 mw stg -65~+5 opr -4~+85 erminal voltage -.3~Vcc+. *9 V Junction * temperature jmax 5 *,*2 When using at a=25 or higher 4.5mW to be reduced per. *3,*7 When using at a=25 or higher 3.mW to be reduced per. *4 When using at a=25 or higher 3.3mW to be reduced per. *5, *6 When using at a=25 or higher 3.mW to be reduced per. *8 When using at a=25 or higher 8.mW to be reduced per. *9 he Max value of erminal Voltage is not over 6.5V. When the pulse width is 5ns or less, the Min value of erminal Voltage is not under -.V. (B246/32/64/28/256/52/M-W) the Min value of erminal Voltage is not under -.8V. (B24/2/4/8-W) * Junction temperature at the storage condition. Memory cell characteristics (a=25, Vcc=.7~ 5.5V) Limits arameter Unit Min. yp. Max Number of data *,, - - imes rewrite times Data hold years * Years *Not % EED ecommended operating conditions arameter ymbol atings Unit ower source voltage Electrical characteristics (Unless otherwise specified, a=-4~+85, V=.7~5.5V) arameter ymbol Limits Min. yp. Max. H input voltage V IH.7Vcc - Vcc+. V L input voltage V IL -.3 *2 -.3Vcc V Vcc.7~5.5 Input voltage V IN ~Vcc Unit onditions L output voltage V OL V I OL =3.m, 2.5V Vcc 5.5V (D) L output voltage 2 V OL V I OL =.7m,.7V Vcc<2.5V (D) Input leak current I LI - - µ V IN =~Vcc Output leak current I LO - - µ V OU =~Vcc (D) Vcc=5.5V,f L =4kHz, t W =5ms, Byte write, age write B24/2/4/8/6/32/64-W I m Vcc=5.5V,f L =4kHz, t W =5ms, Byte write, age write B2428/256-W Vcc=5.5V,f urrent consumption L =4kHz, t W =5ms, Byte write, age write at action B2452/M-W Vcc=5.5V,f L =4kHz andom read, current read, sequential read I 2 m B24/2/4/8/6/32/64/28/256-W Vcc=5.5V,f L =4kHz andom read, current read, sequential read B2452/M-W Vcc=5.5V, D L=Vcc,,2=GND,W=GND tandby current I B µ B24/2/4/8/6/32/64/28/256-W Vcc=5.5V, D L=Vcc ,, 2=GND, W=GND B2452/M-W adiation resistance design is not made. * B2452/M-W is a target value because it is developing. *2 When the pulse width is 5ns or less, it is -.V. (B246/32/64/28/256/52/M-W) When the pulse width is 5ns or less, it is -.8V. (B24/2/4/8-W) V 2 OHM o., Ltd. ll rights reserved. 2/ ev.

3 B24 eries echnical Note ction timing characteristics (Unless otherwise specified, a=-4~+85, V=.7~5.5V) arameter ymbol Limits Min. yp. Max. L frequency fl khz Data clock HIGH time thigh µs Data clock LOW time tlow µs D, L rise time * t - -. µs D, L fall time * tf - -. µs tart condition hold time thd: µs tart condition setup time tu: µs Input data hold time thd:d - - ns Input data setup time tu:d - - ns Output data delay time td. -.9 µs Output data hold time tdh. - - µs top condition setup time tu:o µs Bus release time before transfer start tbuf µs Internal write cycle time tw ms Noise removal valid period (D, L terminal) ti - -. µs W hold time thd:w. - - µs W setup time tu:w. - - µs W valid time thigh:w. - - µs * Not % EED. ondition Input data level:vil=.2 Vcc VIH=.8 Vcc Input data timing refarence level:.3 Vcc/.7 Vcc Output data timing refarence level:.3 Vcc/.7 Vcc ise/fall time : 2ns Unit ync data input / output timing t tf thigh L 7% 7% 7% 7% 7% 3% 3% 3% 3% D (input) 7% tu:d 7% 7% tbuf tlow td thd:d 7% 3% tdh D D() D D(n) 7% tw D (output) Input read at the rise edge of L Data output in sync with the fall of L Fig.-(a) ync data input / output timing 7% 3% 7% 3% 3% tu:w Fig.-(d) W timing at write execution 3% thd:w O ONDIION 7% 7% 7% D() D(n) tu: thd: tu:o D D thigh:w 7% tw 7% 3% 3% 7% 7% ONDIION O ONDIION Fig.-(b) tart-stop bit timing Fig.-(e) W timing at write cancel D 7% 7% write data (n-th address) tw O ONDIION ONDIION Fig.-(c) Write cycle timing 2 OHM o., Ltd. ll rights reserved. 3/ ev.

4 B24 eries echnical Note Block diagram *2 *2 * * ddress decoder bit~24bit EEOM array *7bit 3bit 8bit 4bit 9bit 5bit bit 6bit bit 7bit 2bit ontrol circuit Word address register O 8bit Data register Vcc W L 2 GND B24-W B242-W B244-W B248-W B246-W B2432-W B2464-W B2428-W B24256-W B2452-W B24M-W Vcc W L D GND 4 High voltage generating circuit ower source voltage detection 5 D * 7bit: B24-W 8bit: B242-W 9bit: B244-W bit: B248-W bit: B246-W 2bit: B2432-W 3bit: B2464-W 4bit: B2428-W 5bit: B24256-W 6bit: B2452-W 7bit: B24M-W *2 = Don't use : B244-W, B24M-W, =Don't use: B248-W,, 2=Don't use: B246-W Fig.2 Block diagram in assignment and description erminal Input/ B24-W B242-W B244-W B248-W B246-W Name Output Input lave address setting Don t use* B2432/64/ 28/256/52-W lave address setting B24M-W Don t use* Input lave address setting Don t use* lave address setting 2 Input lave address setting Don t use* lave address setting GND - eference voltage of all input / output, V D Input/ output erial data input serial data output L Input erial clock input W Input Write protect terminal Vcc - onnect the power source. *ins not used as device address may be set to any of H, 'L', and 'Hi-Z'. haracteristic data (he following values are yp. ones.) H INU VOLGE : V IH(V) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) L INU VOLGE : V IL (V) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) L OUU VOLGE : V OL (V) a=-4 a=25 a=85 E L OUU UEN : I OL (m) L OUU VOLGE : V OL2(V) Fig.3 'H' input voltage V IH (,,2,L,D,W) a=-4 a=25 a=85 E L OUU UEN : I OL (m) INU LE UEN : I LI(u) a=-4 a=25 a=85 Fig.4 'L' input voltage V IL (,,2,L,D,W) E ULYVOLGE : Vcc(V) OUU LE UEN : I LO (u) Fig.5 'L' output voltage V OL -I OL (Vcc=.7V) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) Fig.6 'L' output voltage V OL2 -I OL (Vcc=2.5V) Fig.7 Input leak current I LI (,,2,L,W) Fig.8 Output leak current I LO (D) 2 OHM o., Ltd. ll rights reserved. 4/ ev.

5 B24 eries echnical Note haracteristic data (he following values are yp. ones.) UEN ONUMION WIING : Icc(m) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) Fig.9 urrent consumption at WIE operation I (fscl=4khz B24/2/4/8/6/32/64-W) UEN ONUMION WIING : Icc(m) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) Fig. urrent consumption at WIE operation Icc (fscl=4khz B2428/256-W) UEN ONUMION WIING : Icc(m) he plan for inserting data. (B2452/M-W) ULY VOLGE : Vcc(V) Fig. urrent consumption at WIE operation Icc (fscl=4khz B2452/M-W) UEN ONUMION EDING : Icc2(m) ULY VOLGE : Vcc(V) Fig.2 urrent consumption at ED operation I 2 (fscl=4khz B24/2/4/8/6/32/64/28/256-W) 2.5 a=-4 a=25 a=85 E UEN ONUMION EDING : Icc2(m) he plan for inserting data. (B2452/M-W) ULY VOLGE : Vcc(V) Fig.3 urrent consumption at ED operation I 2 (fscl=4khz B2452/M-W) NBY UEN : I B (u) ULY VOLGE : Vcc(V) Fig.4 tanby operation I B (fscl=4khz B24/2/4/8/6/32/64/28/256-W) E a=-4 a=25 a=85 NBY UEN : I B (u) he plan for inserting data. (B2452/M-W) L FEQUENY : fscl(kh Z ) a=-4 a=25 a=85 E D L H IME : t HIGH (us) a=-4 a=25 a=85 E D L L IME : t LOW (us) ULY VOLGE : Vcc(V) Fig.5 tanby operation I B (fscl=4khz B2452/M-W) a=-4 a=25 a=85 E ONDIION HOLD IME : t HD : (us). ULY VOLGE : Vcc(V) Fig.6 L frequency f L a=-4 a=25 a=85 E ONDIION E U IME : tu:(us) ULY VOLGE : Vcc(V) Fig.7 Data clock High eriod t HIGH a=-4 a=25 a=85 E -. ULY VOLGE : Vcc(V) ULY VOLGE : Vcc(V) ULY VOLGE : Vcc(V) Fig.8 Data clock Low eriod t LOW Fig.9 tart ondition Hold ime t HD : Fig.2 tart ondition etup ime t U : INU D HOLD IME : t HD: (ns) a=-4 a=25 a=85 E -2 INU D HOLD IME : t HD :D (ns) a=-4 a=25 a=85 E -2-2 ULY VOLGE : Vcc(V) ULY VOLGE : Vcc(V) ULY VOLGE : Vcc(V) Fig.2 Input Data Hold ime t HD : D (HIGH) Fig.22 Input Data Hold ime t HD : D (LOW) Fig.23 Input Data etup ime t U: D (HIGH) INU D E U IME : t U: D(ns) a=-4 a=25 a=85 E 2 OHM o., Ltd. ll rights reserved. 5/ ev.

6 B24 eries echnical Note haracteristic data (he following values are yp. ones.) INU D E U IME : t U : D (ns) 3 2 E a=-4 - a=25 a=85-2 OUU D DELY IME : t D (us) a=-4 a=25 a=85 E E OUU D DELY IME : t D (us) a=-4 a=25 a=85 E E ULY VOLGE : Vcc(V) Fig.24 Input Data setup time t U : D (LOW) ULY VOLGE : Vcc(V) ULY VOLGE : Vcc(V) Fig.25 'L' Data output delay time t D Fig.26 'H' Data output delay time t D O ONDIION EU IME : t su:o(us) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) BU OEN IME BEFOE NMIION : t BUF (us) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) INENL WIING YLE IME : t W (ms) E 2 a=-4 a=25 a=85 ULY VOLGE : Vcc(V) Fig.27 top condition setup time t U :O Fig.28 BU open time before transmission t BUF Fig.29 Internal writing cycle time t W NOIE EDUION EFEIVE IME : t l (L H) (us) a=-4 a=25 a=85 NOIE EDUION EFEIVE IME : t l (L L)(us) a=-4 a=25 a=85... E E E NOIE EDUION EFEIVE IME : t l (D H)(us) a=-4 a=25 a=85 ULY VOLGE : Vcc(V) ULY VOLGE : Vcc(V) Fig.3 Noise reduction efection time t l (L H) Fig.3 Noise reduction efective time t l (L L) ULY VOLGE : Vcc(V) Fig.32 Noise resuction efecctive time t l (D H) NOIE EDUION EFFEIVE IME : t l (D L)(us) a=-4 a=25 a=85 E W D HOLD IME : t HD : W (us) a=-4 a=25 a=85 E W E U IME : t U : W (us) a=-4 a=25 a=85 E ULY VOLGE : Vcc(V) Fig.33 Noise reduction efective time t l (D L) ULYVOLGE : Vcc(V) Fig.34 W data hold time thd:w ULY VOLGE : Vcc(V) Fig.35 W setup time t U : W W EFFEIVE IME : t HIGH : W (us) a=-4 a=25 a=85 E ULYVOLGE : Vcc(V) Fig.36 W efective time t HIGH : W 2 OHM o., Ltd. ll rights reserved. 6/ ev.

7 B24 eries echnical Note I 2 BU communication I 2 BU data communication I 2 BU data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I 2 BU carries out data transmission with plural devices connected by 2 communication lines of serial data (D) and serial clock (L). mong devices, there are master that generates clock and control communication start and end, and slave that is controlled by address peculiar to devices. EEOM becomes slave. nd the device that outputs data to bus during data communication is called transmitter, and the device that receives data is called receiver. D L Fig.37 Data transfer timing tart condition (tart bit recognition) Before executing each command, start condition (start bit) where D goes from 'HIGH' down to 'LOW' when L is 'HIGH' is necessary. his I always detects whether D and L are in start condition (start bit) or not, therefore, unless this confdition is satisfied, any command is executed. top condition (stop bit recongnition) Each command can be ended by D rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, L is 'HIGH' cknowledge () signal his acknowledge () signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (µ-om at slave address input of write command, read command, and this I at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. he device (this I at slave address input of write command, read command, and µ-om at data output of read command) at the receiver (receiving) side sets D 'LOW' during 9 clock cycles, and outputs acknowledge signal ( signal) showing that it has received the 8bit data. his I, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( signal) 'LOW'. Each write action outputs acknowledge signal ( signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal ( signal) 'LOW'. When acknowledge signal ( signal) is detected, and stop condition is not sent from the master (µ-om) side, this I continues data output. When acknowledge signal ( signal) is not detected, this I stops data transfer, and recognizes stop cindition (stop bit), and ends read action. nd this I gets in status. Device addressing Output slave address after start condition from master. he significant 4 bits of slave address are used for recognizing a device type. he device code of this I is fixed to ''. Next slave addresses (2 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. he most insignificant bit (/W --- ED / WIE ) of slave address is used for designating write or read action, and is as shown below. etting etting / W to write (setting to word address setting of random read) / W to read ype lave address Maximum number of onnected buses B24-W,B242-W 2 /W 8 B244-W 2 /W 4 B248-W 2 /W 2 B246-W 2 /W B2432-W,B2464-W,B2428-W, B24256-W,B2452-W 2 /W 8 B24M-W 2 /W 4 ~2 are page select bits. DDE /W condition D D O condition 2 OHM o., Ltd. ll rights reserved. 7/ ev.

8 B24 eries echnical Note Write ommand Write cycle rbitrary data is written to EEOM. When to write only byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. he maximum number of write bytes is specified per device of each capacity. Up to 256 arbitrary bytes can be written.(in the case of B24M-W) D LINE LVE DDE 2 W I E W 7 WOD DDE W D7 D D O s for W7, B24-W becomes Don't care. Note) / W Fig.38 Byte write cycle (B24/2/4/8/6-W) D LINE LVE DDE 2 Note) W I E / W st WOD DDE W W W W W * 2nd WOD DDE W D7 D D O * s for W2, B2432-W becomes Don't care. s for W3, B2432/64-W becomes Don't care. s for W4, B2432/64/28-W becomes Don't care. s for W5, B2432/64/28/256-W becomes Don't care. Fig.39 Byte write cycle (B2432/64/28/256/52/M-W) LVE DDE W I E WOD DDE(n) D(n) *2 D(n+5) O D LINE 2 W 7 W D7 D D * s for W7, B24-W becomes Don't care. *2 s for B24/2-W becomes (n+7) 注 ) / W * Fig.4 age write cycle (B24/2/4/8/6-W) D LINE LVE DDE 2 W I E st WOD DDE(n) 注 ) / * W 2nd WOD DDE(n) D(n) *2 D(n+3) W W W W W W D7 D D O * s for W2, B2432-W becomes Don't care. s for W3, B2432/64-W becomes Don't care. s for W4, B2432/64/28-W becomes Don't care. s for W5, B2432/64/28/256-W becomes Don't care. *2 s for B2428/256-W becomes (n+63) s for B2452-W becomes (n+27) s for B24M-W becomes (n+255) Fig.4 age write cycle (B2432/64/28/256/52/M-W) Note) * *2 *3 2 * In B246-W, 2 becomes 2. *2 In B248/6-W, becomes. *3 In B244/8/6/M-W becomes. Fig.42 Difference of slave address of each type 2 OHM o., Ltd. ll rights reserved. 8/ ev.

9 B24 eries echnical Note During internal write execution, all input commands are ignored, therefore is not sent back. Data is written to the address designated by word address (n-th address) By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tw (5ms at maximum). By page write cycle, the following can be written in bulk : Up to 8Byte (B24-W, B242-W) Up to 6Byte (B244-W, B248-W, B246-W) Up to 32Byte (B2432-W, B2464-W) Up to 64Byte (B2428-W, B24256-W) Up to 28Byte (B2452-W) Up to 256Byte (B24M-W) nd when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (efer to "Internal address increment" of "Notes on page write cycle" in.) s for page write cycle of B24-W and B242-W, after the significant 4 bits (in the case of B24-W) of word address, or the significant 5 bits (in the case of B242-W) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be written. s for page write command of B244-W, B248-W and B246-W, after page select bit (in the case of B244-W), after page select bit, (in the case of B248-W), after page select bit,,2 (in the case of B246-W) of slave address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 6 bytes can be written. s for page write cycle of B2432-W and B2464-W, after the significant 7 bits (in the case of B2432-W) of word address, or the significant 8 bits (in the case of B2464-W) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. s for page write cycle of B2428-W and B24256-W, after the significant 8 bits (in the case of B2428-W) of word address, or the significant 9 bits (in the case of B24256-W) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 6 bits is incremented internally, and data up to 64 bytes can be written. s for page write cycle of B2452-W after the significant 9 bits of word address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 7 bits is incremented internally, and data up to 28 bytes can be written. s for page write cycle of B24M-W after page select bit and the significant 8 bit of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and data up to 256 bytes can be written. 2 OHM o., Ltd. ll rights reserved. 9/ ev.

10 B24 eries echnical Note Notes on page write cycle List of numbers of page write Number of ages 8Byte 6Byte 32Byte 64Byte 28Byte 256Byte roduct number B24-W B242-W B244-W B248-W B246-W he above numbers are maximum bytes for respective types. ny bytes below these can be written. In the case B24256-W, page=64bytes, but the page write cycle time is 5ms at maximum for 64byte bulk write. It does not stand 5ms at maximum 64byte=32ms(Max.) B2432-W B2464-W B2428-W B24256-W B2452-W B24M-W Internal address increment age write mode (in the case of B246-W) W7 W4 W3 W2 W W Increment Eh ignificant bit is fixed. No digit up For example, when it is started from address Eh, therefore, increment is made as below, Eh Fh h h which please note. Eh E in hexadecimal, therefore, becomes a binary number. Write protect (W) terminal Write protect (W) function When W terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. In the case of use it as an OM, it is recommended to connect it to pull up or Vcc. t extremely low voltage at power ON / OFF, by setting the W terminal 'H', mistake write can be prevented. 2 OHM o., Ltd. ll rights reserved. / ev.

11 B24 eries echnical Note ead ommand ead cycle Data of EEOM is read. In read cycle, there are random read cycle and current read cycle. andom read cycle is a command to read data by designating address, and is used generally. urrent read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession. D LINE LVE DDE 2 Note) W I E W 7 * / W WOD DDE(n) Fig.43 andom read cycle (B24/2/4/8/6-W) W LVE DDE 2 E D / W D7 D(n) D O * s for W7,B24-W become Don t care. D LINE LVE DDE W I E st WOD DDE ( ) W W W W W W D7 D 2 Note) / W * 2nd WOD DDE(n) Fig.44 andom read cycle (B2432/64/28/256/52/M-W) LVE DDE E D / W D(n) O * s for W2, B2432-W become Don t care. s for W3, B2432/64-W become Don t care. s for W4, B2432/64/28-W become Don t care. s for W5, B2432/64/28/256-W become Don t care. D LINE LVE DDE 2 E D D7 D(n) D O * s for W7, B24-W becomes Don't care. *2 s for B24/2-W becomes (n+7) Note) / W Fig.45 urrent read cycle D LINE LVE DDE 2 Note) E D / W D7 D(n) D Fig.46 equential read cycle (in the case of current read cycle) D7 D(n+x) D O * s for W2, B2432-W becomes Don't care. s for W3, B2432/64-W becomes Don't care. s for W4, B2432/64/28-W becomes Don't care. s for W5, B2432/64/28/256-W becomes Don't care. *2 s for B2428/256-W becomes (n+63) s for B2452-W becomes (n+27) s for B24M-W becomes (n+255) In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+)-th address is output. When signal 'LOW' after D is detected, and stop condition is not sent from master (µ-om) side, the next address data can be read in succession. ead cycle is ended by stop condition where 'H' is input to signal after D and D signal is started at L signal 'H'. When 'H' is not input to signal after D, sequential read gets in, and the next data is output. herefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to signal after D, and to start D at L signal 'H'. equential read is ended by stop condition where 'H' is input to signal after arbitrary D and D is started at L signal 'H'. Note) * *2 *3 2 * In B246-W, 2 becomes 2. *2 In B248/6-W, becomes. *3 In B248/6/M-W, becomes. Fig.47 Difference of slave address of each type 2 OHM o., Ltd. ll rights reserved. / ev.

12 B24 eries echnical Note oftware reset oftware reset is executed when to avoid malfunction after power on, and to reset during command input. oftware reset has several kinds, and 3 kinds of them are shown in the figure below. (efer to Fig.48-(a), Fig.48-(b), Fig.48-(c).) In dummy clock input area, release the D bus ('H' by pull up). In dummy clock area, output and read data '' (both 'L' level) may be output from EEOM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clock 4 tart 2 L D Normal command Normal command Fig.48-(a) he case of dummy clock +++ command input tart Dummy clock 9 tart L D Normal command Normal command Fig.48-(b) he case of +9 dummy clocks ++ command input tart 9 L D D Fig.48-(c) 9+ command input Normal command Normal command tart command from input. cknowledge polling During internal write execution, all input commands are ignored, therefore is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tw = 5ms. When to write continuously, / W =, when to carry out current read cycle after write, slave address / W = is sent, and if signal sends back 'L', then execute word address input and data output and so forth. First write command During internal write, = HIGH is sent back. Write command O lave address H tw lave address econd write command H lave address tw H lave address L Word address L Data L O fter completion of internal write, =LOW is sent back, so input next word address and data in succession. Fig.49 ase to continuously write by acknowledge polling 2 OHM o., Ltd. ll rights reserved. 2/ ev.

13 B24 eries echnical Note W valid timing (write cancel) W is usually fixed to 'H' or 'L', but when W is used to cancel write cycle and so forth, pay attention to the following W valid timing. During write cycle execution, in cancel valid area, by setting W='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D of data(in page write cycle, the first byte data) is cancel invalid area. W input in this area becomes Don't care. he area from the rise of L to take in D to input the stop condition is cancel valid area. nd, after execution of forced end by W, standby status gets in. ise of D taken clock ise of D L L D D D D D Enlarged view Enlarged view D W lave address L Word address L D7 D6 D5 D4 D3 D2 D D W cancel invalid area L Data W cancel valid area Data is not written. L O tw W cancel invalid area Fig.5 W valid timing ommand cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.5) However, in output area and during data read, D bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. herefore, execute software reset. nd when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle. L D tart condition top condition Fig.5 ase of cancel by start, stop condition during slave address input 2 OHM o., Ltd. ll rights reserved. 3/ ev.

14 B24 eries echnical Note I/O peripheral circuit ull up resistance of D terminal D is NMO open drain, so requires pull up resistance. s for this resistance value ( U ), select an appropriate value to this resistance value from microcontroller V IL, I L, and V OL -I OL characteristics of this I. If U is large, action frequency is limited. he smaller the U, the larger the consumption current at action. Maximum value of U he maximum value of U is determined by the following factors. D rise time to be determined by the capacitance (BU) of bus line of U and D should be t or below. nd timing should be satisfied even when D rise time is late. 2he bus electric potential to be determined by input leak total (I L ) of device connected to bus at output of 'H' to D bus and U should sufficiently secure the input 'H' level (V IH ) of microcontroller and EEOM including recommended noise margin.2vcc. V-ILU-.2 V VIH.8V VIH U IL Ex.) V =3V IL=µ VIH=.7 V from U 6 Microcontroller IL U IL B24XX D terminal 3 [kω] Bus line capacity BU Fig.52 I/O circuit diagram Minimum value of U he minimum value of U is determined by the following factors. When I outputs LOW, it should be satisfied that V OLMX =.4V and I OLMX =3m. V VOL IOL U V VOL U IOL 2VOLMX= should secure the input 'L' level (V IL ) of microcontroller and EEOM including recommended noise margin.vcc. VOLMX VIL-. V Ex.) V =3V, VOL=.4V, IOL=3m, microcontroller, EEOM V IL =.3Vcc 3.4 from U [Ω] nd VOL=.4[V] VIL=.3 3 =.9[V] herefore, the condition 2 is satisfied. ull up resistance of L terminal When L control is made at MO output port, there is no need, but in the case there is timing where L becomes 'Hi-Z', add a pull up resistance. s for the pull up resistance, one of several kω ~ several ten kω is recommended in consideration of drive performance of output port of microcontroller. 2 OHM o., Ltd. ll rights reserved. 4/ ev.

15 B24 eries echnical Note autions on microcontroller connection In I 2 BU, it is recommended that D port is of open drain input/output. However, when to use MO input / output of tri state to D port, insert a series resistance s between the pull up resistance pu and the D terminal of EEOM. his is controls over current that occurs when MO of the microcontroller and NMO of EEOM are turned ON simultaneously. s also plays the role of protection of D terminal against surge. herefore, even when D port is open drain input/output, s can be used. U L D 'H' output of microcontroller 'L' output of EEOM Microcontroller EEOM Fig.53 I/O circuit diagram Over current flows to D line by 'H' output of microcontroller and 'L' output of EEOM. Fig.54 Input / output collision timing Maximum value of s he maximum value of s is determined by the following relations. D rise time to be determined by the capacity (BU) of bus line of pu and D should be t or below. nd timing should be satisfied even when D rise time is late. 2he bus electric potential to be determined by pu and s the moment when EEOM outputs 'L' to D bus sufficiently secure the input 'L' level (V IL ) of microcontroller including recommended noise margin.vcc. V VIL Micro controller U IOL Bus line capacity BU Fig.55 I/O ircuit Diagram VOL EEOM V VOL U VOL.V VIL V VOL U.V VIL Ex)V=3V VIL=.3V VOL=.4V U=2kΩ [kΩ] Minimum value of s he minimum value of s is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. et the over current to EEOM m or below. U 'L'output Over current I 'H' output Microcontroller EEOM Fig.56 I/O circuit diagram V I V I EX) V =3V I=m [ Ω] 2 OHM o., Ltd. ll rights reserved. 5/ ev.

16 B24 eries echnical Note I 2 BU input / output circuit Input (,, 2, L, W) Fig.57 Input pin circuit diagram Input / output (D) Fig.58 Input / output pin circuit diagram 2 OHM o., Ltd. ll rights reserved. 6/ ev.

17 B24 eries echnical Note Notes on power ON t power on, in I internal circuit and set, Vcc rises through unstable low voltage area, and I inside is not completely reset, and malfunction may occur. o prevent this, functions of O circuit and LV circuit are equipped. o assure the action, observe the following conditions at power on.. et D = 'H' and L ='L' or 'H 2. tart power source so as to satisfy the recommended conditions of t, t OFF, and Vbot for operating O circuit. V t ecommended conditions of t, toff,vbot t toff Vbot toff Vbot ms or below ms or larger.3v or below msor below msor larger.2v or below Fig.59 ise waveform diagram 3. et D and L so as not to become 'Hi-Z'. When the above conditions and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition cannot be observed. When D becomes 'L' at power on. ontrol L and D as shown below, to make L and D, 'H' and 'H'. V tlow L D fter Vcc becomes stable tdh tu:d Fig.6 When L= 'H' and D= 'L' fter Vcc becomes stable tu:d Fig.6 When L='L' and D='L' b) In the case when the above condition 2 cannot be observed. fter power source becomes stable, execute software reset(2). c) In the case when the above conditions and 2 cannot be observed. arry out a), and then carry out b). Low voltage malfunction prevention function LV circuit prevents data rewrite action at low power, and prevents wrong write. t LV voltage (yp. =.2V) or below, it prevent data rewrite. Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (.µf) between I Vcc and GND. t that moment, attach it as close to I as possible. nd, it is also recommended to attach a bypass capacitor between board Vcc and GND. 2 OHM o., Ltd. ll rights reserved. 7/ ev.

18 B24 eries echnical Note Notes for use () Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LI. (3) bsolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LI. (4) GND electric potential et the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) erminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6) erminal to terminal shortcircuit and wrong packaging When to package LI onto a board, pay sufficient attention to LI direction and displacement. Wrong packaging may destruct LI. nd in the case of shortcircuit between LI terminals and terminals and power source, terminal and GND owing to foreign matter, LI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. 2 OHM o., Ltd. ll rights reserved. 8/ ev.

19 B24 eries echnical Note Order part number B F V - W G E 2 art No. BU type 24:I 2 Operating temperature/ ower source Voltage -4 ~+85.7V~5.5V apacity = 64=64 2=2 28=28 4=4 256=256 8=8 52=52 6=6 M=24 32=32 ackage Blank :DI-8 F :O8 FJ :O-J8 FV : O-B8 FV : O-B8 FVJ : O-B8J FVM : MO8 NUX :VON8X23 Double ell Halogen Free ackaging and forming specification E2: Embossed tape and reel (O8, O8-J8, O-B8, O-B8, O-B8J) : Embossed tape and reel (MO8, VON8X23) None: ube (DI-8) DI-8 <ape and eel information> 9.3± ±.3 ontainer Quantity Direction of feed ube 2pcs Direction of products is fixed in a container tube 4.5Min. 3.4± ± ±. 5.3±. (Unit : mm) Order quantity needs to be multiple of the minimum quantity. O8 5.±.2 (MX 5.35 include BU) <ape and eel information> ape Quantity Embossed carrier tape 25pcs 6.2±.3 4.4± MIN.9±.5 Direction of feed E2 he direction is the pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand ( ).5± ±. (Unit : mm) eel Direction of feed pin Order quantity needs to be multiple of the minimum quantity. O-J8 6.±.3 3.9±.2 4.9±.2 (MX 5.25 include BU) ±..45MIN <ape and eel information> ape Embossed carrier tape Quantity 25pcs Direction of feed E2 he direction is the pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand ( ).375± ±.. (Unit : mm) eel Direction of feed pin Order quantity needs to be multiple of the minimum quantity. 2 OHM o., Ltd. ll rights reserved. 9/ ev.

20 B24 eries echnical Note O-B8.2MX.±.5 3.±. (MX 3.35 include BU) 6.4±.2 4.4±..± IN M ± 4.5±.5.± M (Unit : mm) <ape and eel information> ape Embossed carrier tape Quantity 3pcs Direction of feed E2 he direction is the pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand ( ) eel pin Direction of feed Order quantity needs to be multiple of the minimum quantity. O-B8J 4.9±.2 3.±..MX.85±.5.±.5 3.±. (MX 3.35 include BU) IN M ± 4.45±.5.95± M (Unit : mm) <ape and eel information> ape Quantity Direction of feed Embossed carrier tape 25pcs E2 he direction is the pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand ( ) eel pin Direction of feed Order quantity needs to be multiple of the minimum quantity. MO8 4.±.2 2.9±. (MX 3.25 include BU) 2.8± ±.5.6±.2 <ape and eel information> ape Quantity Direction of feed Embossed carrier tape 3pcs he direction is the pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand ( ).9MX.75±.5.8± IN M (Unit : mm) eel pin Direction of feed Order quantity needs to be multiple of the minimum quantity. 2 OHM o., Ltd. ll rights reserved. 2/ ev.

21 B24 -W eries echnical Note VON8X23.6MX.8 2.±..5± ±. IN M (.2) <ape and eel information> ape Embossed carrier tape Quantity 4pcs Direction of feed he direction is the pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand ( ) ± ± (Unit : mm) eel pin Direction of feed Order quantity needs to be multiple of the minimum quantity. 2 OHM o., Ltd. ll rights reserved. 2/ ev.

22 Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of OHM o.,ltd. he content specified herein is subject to change for improvement without notice. he content specified herein is for the purpose of introducing OHM's products (hereinafter "roducts"). If you wish to use any such roduct, please be sure to refer to the specifications, which can be obtained from OHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the roducts. he peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, OHM shall bear no responsibility for such damage. he technical information specified herein is intended only to show the typical functions of and examples of application circuits for the roducts. OHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by OHM and other parties. OHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. he roducts specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). he roducts specified in this document are not designed to be radiation tolerant. While OHM always makes efforts to enhance the quality and reliability of its roducts, a roduct may fail or malfunction for a variety of reasons. lease be sure to implement in your equipment using the roducts safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any roduct, such as derating, redundancy, fire control and fail-safe designs. OHM shall bear no responsibility whatsoever for your use of any roduct outside of the prescribed scope or not in accordance with the instruction manual. he roducts are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). OHM shall bear no responsibility in any way for use of any of the roducts for the above special purposes. If a roduct is intended to be used for any such special purpose, please contact a OHM sales representative before purchasing. If you intend to export or ship overseas any roduct or technology specified herein that may be controlled under the Foreign Exchange and the Foreign rade Law, you will be required to obtain a license or permit under the Law. hank you for your accessing to OHM product informations. More detail product informations and catalogs are available, please contact us. OHM ustomer upport ystem 2 OHM o., Ltd. ll rights reserved. 2