VDD LASER MODULATION DRIVER IMOD MODSET BIASN SML2108 DETECT VSS

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1 UMMI MIELENI, Inc. Laser iode daptive ower ontroller FEUE! Integrated Bias urrent Monitor " Monitors & Measures Laser emperature irectly " Eliminates Need for Eternal hermistor & hermal oupling Issues " larm utput on ver-temperature ondition! daptive Modulation ontrol (M) " djusts Modulation urrent as a Function of the Laser emperature " 8 8 rogrammable ompensation able " 256 Independent ompensation Values " Integrated 8-Bit Modulation ontrol! Fleible Biasing rchitecture " Bias ontrol and Modulation ontrol: to m / to m ource, to m ink! utomatic ower ontrol () with Integrated -Bit rogrammable ffset " utomatic Initial Bias ptimization! Electronic alibration hrough 2-wire Interface! 3V or 5V peration EIIN he is an adaptive power controller for laser diodes. It is the industry's first integrated device that can directly monitor and measure a laser diode's temperature, and provide a variable modulation current. he 's integrated active feedback loop is used to calibrate and control the mean and modulation power of high speed, high power laser diodes. Inherent manufacturing tolerances introduce variations of performance in laser diodes. hese variations, combined with parametric changes over the laser s etreme temperature range and laser ageing, call for an efficient temperature compensation scheme. Using an internal digital control loop and a programmable nonvolatile compensation lookup table, the provides the most optimum adaptive power control with a minimum number of eternal components. he removes the need for any manual calibration of the laser control circuit, which is currently the industry standard practice. ll calibration values are programmed through the 2-wire communication interface, which can be controlled by most production E equipment. rogramming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from ummit Microelectronics. he is available in 48 lead QF. IMLIFIE LIIN IGM V IN+ IN LE MULIN IVE IM LE IE MNI IE ME V Interface V MN UMN V BIN EE 253. UMMI MIELENI, Inc., 2 3 rchard ity r., uite 3 ampbell, 958 hone FX haracteristics subject to change without notice //

2 FUNINL BL IGM EE 2 2 V V Bit NV eg -Bit eg -Bit + 5 BI EX EM BI N Bit (ll s kω) UMN 6 3 V E# 48 onfig NV caling & ffset 4 V Y ead & larm eg 8 LE# NV Look-up able M NV eg 8-Bit M N V 253 B // UMMI MIELENI, Inc.

3 IN NFIGUIN 48-in QF 2 UMN Y# LE# EX EM 2 EE MN MN BIN BIN V V V V BIN BIN MN MN V V V V BI BI M M V V V V E# V V BI BI M M V V V V on 2. IN EIIN EE (2) his is the analog input from the laser monitor photodiode for the integrator circuit. here is an on-board resistance of 2MΩ between the EE input and pin. and 2 ( & ) apacitor inputs for an eternal capacitor in the feedback loop of the Mean ower ontrol Integrator. here is an onboard capacitance of 5pF. UMN (6) ctive high input used to enable the internal auto-monitor function, which provides automatic adjustments to the modulation output currents (M and MN) based on the internal / output and the values stored in the nonvolatile lookup table. his pin has an internal kω pullup. LE# (8) ctive low, open-drain output. his pin is driven low whenever the bias current increases beyond a predefined nonvolatile threshold. his can be used to predict laser failure., (4 & 5) ata and lock lines, respectively, whose function and use are based on the industry standard I 2 interface. Lookup table values, configuration data, and / and / registers may all be accessed via these two pins of the. hese pins have internal kω pullups.,, 2 (, 2, & 3) ddress ins for the interface provided to allow multiple devices on a single bus. hese pins have internal kω pullups. Y# () ctive low, open-drain output. his pin is driven low whenever the internal / is performing a conversion, or while the on-board EEM is being programmed. EX EM (9) emperature input (or no connection). his pin can be programmed as an input to the and can interface a temperature sensor. he EX EM pin is multipleed with the bias current to provide a means of configuring the input to the. When EX EM is programmed as the UMMI MIELENI, Inc // 3

4 input to the using bit 5 of egister, the converted value of the current entering this pin is used as the address of the EEM lookup table. In this configuration the modulation current can be controlled by temperature rather than the bias current. efer to the application eample on using the EX EM pin. If this option is not used the pin should be left floating. V, V (3 & 4) nalog and digital low-side supplies for on-board circuitry. Must be at same potential as all other V pins. V (5, 6, 2, 22, 39, 4, 45, 46, & 4) High-side supply for the Bias and Modulation currents and power supply input for the chip. E# (48) he chip enable input is active low and provides an additional method of enabling the serial interface. he state of this pin has no effect on the auto-monitor function. his pin has an internal kω pullup. BI (, 8, 43, & 44) High-side mean bias control current. urrent source output range is programmable, with the optional ranges of to m or to m. BIN (2, 28, 33, & 34) Low-side mean bias control current. urrent sink input range is to m. M (9, 2, 4, &42) High-side modulation control current. urrent source output range is programmable, with optional ranges of to m or to m. MN (25, 26, 35, &36) Low-side modulation control current. urrent sink input range is to m // UMMI MIELENI, Inc.

5 BLUE MXIMUM ING* emperature Under Bias to 25 torage emperature to 5 Lead older emperature ( secs)... 3 *MMEN tresses listed under bsolute Maimum atings may cause permanent damage to the device. hese are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Eposure to any absolute maimum rating for etended periods may affect device performance and reliability. ELEIL BLE (ver ecommended perating onditions; Voltages are relative to GN) ymbol /N H ypical erformance ccuracy aramete r onditions M in. yp. Ma. Units ignal to Noise ratio = 25º º db otal harmonic distortion 8 db eak harmonic intermodulation distortion 2nd rder 8 db 3rd rder 8 db esolution 8 Bits eolution for which no missing codes are guaranteed elative accuracy 8 Bits ± ½ LB NL ± LB ositive full scale error ± 2 LB Unipolar offset error V V 3.6V = 5V ± 2 LB = 2.V to ± 2 LB 253 Elect able UMMI MIELENI, Inc // 5

6 ymbol V I I L I LI V L V H V IL V IH fin t U arameter upply voltage upply current Maimum bias current onditions M in. yp. Ma. and modulation Bias and modulation current out- puts open Units V 2 m Input leakage current V IN = V to V µ utput leakage current V U = V to V µ utput low voltage = 2m. 4 V I L utput high voltage V = 5V, I = 4µ 2. 4 V L V < 4.5V, I = µ V L. 2 V Input low voltage.. 3 V V Input high voltage. V. 5 V Integrator loop frequency khz ower time nalog Inputs EE I I EX EM MN I M IB IB V IN I up stabilization Integrator time constant is less than ms ms EE input to. 5 V Full scale current input µ nalog utputs N-channel current -channel current modulation modulation m m N-channel bias current m -channel bias current m -Bit output. 5 V igital utputs LE LE output pen drain LE output active is 5 m 253 Elect able B // UMMI MIELENI, Inc.

7 EVIE EIN General escription he is an adaptive power controller for laser diodes with an active feedback loop used to calibrate and control the mean and modulation power of high speed, high power laser diodes. Inherent manufacturing tolerances introduce variations of performance in laser diodes. hese variations, combined with parametric changes over the laser s etreme temperature range and laser ageing, call for an efficient compensation solution. he, with a minimum number of eternal components, is designed to compensate for these tolerances using a digital control loop and a programmable nonvolatile calibration lookup table. Figure illustrates the usefulness of the. he figure shows the output light power of a laser diode versus its operating current. epicted in the graph are typical laser diode characteristics at two different temperatures. t the first temperature ( ), the laser requires an average bias current of IBI. he modulation current needed to switch the laser between its on and off state is labeled IM. he ratio of light power of its on state divided by the light power of its off state is referred to as the etinction ratio. Ideally the laser will maintain a constant etinction ratio over its entire operating temperature range, as the receiver module is calibrated to this level. unning the laser driver at a higher etinction ratio indicates that power is being wasted, whereas operating at a lower etinction ratio indicates that data may possibly be lost. When the laser is operated at a second temperature ( 2 ) the required bias current is shown as IBI 2. o maintain a constant etinction ratio as in the curve the laser requires a modulation of IM 2. he is the industry s first integrated device capable of providing a variable modulation current based on a function of either the bias current or an eternal temperature. his ability to be able to compensate the modulation output current enables the system designer to optimize the etinction ratio of the laser driver module. he has been specified to remove the need for any manual calibration of the laser control circuit. ll calibration values are programmed through an industry standard 2-wire communication interface, whose protocol and function can be controlled by most production E equipment. Bias urrent Mean ower ontrol he bias current outputs (BI and BIN) establish the average power being delivered to an eternal laser diode. he output of the laser diode is separately monitored using a local back-face diode, the output of which is tied to the EE pin of the. When coupled with the on-board integrator this feedback loop becomes the mean power control for the laser diode. he output block of the mean power control is shown in Figure 2. Light ower (n) 2 IBI IBI2 (ff) otal I IM2 IM 253 Fig Figure. Laser urrent Increase aused by emperature Increase, onstant Light ower ut UMMI MIELENI, Inc //

8 he built-in integration time constant is nominally ms. his is accomplished by using an internal 2MΩ resistor and 5pF capacitor. he time constant can be modified by adding eternal capacitance between the and 2 terminals, and/or by adding eternal resistance between the EE and terminals. For stability reasons it is not recommended that the time constant be decreased to less than us. he output of an internal -Bit biases the positive terminal of the integrating amplifier. his provides an analog reference to the integrator which is useful for initial calibration of the laser module. he full-scale value of the output is.5v. -Bit Bias ontrol / he -Bit / determines the reference voltage of the non-inverting terminal of the integrating amplifier in the mean power control loop. ssociated with this are a -Bit volatile register and a -Bit nonvolatile (NV) register. he content of the volatile register determines the output voltage. he output voltage is given by the following relation: X V =.5V 24 where X = the decimal equivalent of the -Bit data stored in the volatile register. Note that the output voltage is not directly accessible eternal to the chip. However, when the is placed in a typical application circuit, the mean power control feedback loop forces the voltage at the EE pin to be the same as the output. n device power-up the volatile register may be loaded with all zeroes, or it may be loaded from the contents of the - Bit nonvolatile register. ccess to the -Bit volatile register is obtained via the 2- wire interface at slave address BIN, word address. efer to Figures 9,, 2, and 3 for details on programming and reading data from the -Bit register. When writing to the volatile register the new output will become valid immediately at the end of the write command. eading the volatile register has no effect on the output. eading or writing the volatile register has no effect on the contents of the nonvolatile register. he -Bit NV register can only be accessed indirectly through the volatile register. he command sequence to communicate with the NV register is the same as that of Input From M Integrator Figure 2. utput Block : Mean ower ontrol From I M M NL BI NL V V Figure 3. utput Block 2: I M I BI ource to m or to m BI BIN I BI ink to m 253 Fig2 I M ource to m or to m M MN I M ink to m 253 Fig3 the volatile register, ecept word address 2 is used instead of. When reading the NV register, the data is first transferred into the volatile register where it may be accessed by the serial interface. Note that upon this transfer the output will change immediately to reflect the new data. imilarly, when writing to the NV register, // UMMI MIELENI, Inc.

9 the data is first placed in the volatile register. t the conclusion of the write command an internal nonvolatile write sequence initiates the storage of the volatile contents into the NV register. Note that when modifying the -Bit output, the mean power control loop will become temporarily disrupted. It may be several milliseconds before the bias current has settled to its steady state value. Until then its value will be undefined. Modulation urrent uto-monitor ontrol he laser bias current, which relates directly to laser temperature, can be monitored using an on-board, current-sensing / converter. In the auto-monitor mode the 8-Bit output of the converter is used as an address to the EEM lookup table. he subsequent 8-Bit data output from the lookup table becomes the input for the compensation. he 8-Bit compensation output is a current in the range of to m and is used to control the modulation current M and MN. he output block of the modulation current control is shown in Figure 3. he lookup table provides an arbitrary mapping from bias current to modulation current. he input range to the may be scaled and/or offset to provide maimum resolution within the appropriate conversion space. he sample interval is programmable from µs to s. efer to the section for further details about configuring the /. he interface is used to program the configuration registers as well as lookup table values. Lookup able 2k-Bit (256 8) memory array of on-board EEM comprises the internal lookup table. his array is accessed via the 2-wire serial interface using a slave address of BIN. (Note: BIN is the default, however this may be set to BIN, depending upon the contents of onfiguration egister 2.) efer to the Bus Interface section for details on programming and reading data from the device. In the auto-monitor mode the content of the array represents the transfer function between the / output and the final value of modulation current. Using a lookup table to implement this function allows arbitrary functions, and even nonlinear relations, to be easily realized. lso, the use of a lookup table allows each device to be customized to normalize overall module operation. lthough the memory may normally be read and written as a standard memory, a security feature eists in the configuration settings that will prevent any eternal access to the array. dditionally, if the auto-monitor feature is not used, then the modulation output current may be programmed to a fied value, and the array may be used as a standard memory to store device settings, board identification values, production dates, etc. 8-Bit urrent utput / he 8-Bit / defines the modulation output current. ssociated with this are an 8-Bit volatile register and an 8-Bit nonvolatile (NV) register. he content of the volatile register determines the output current. he output current is given by the following relation: X = m 256 where X = the 8-Bit data stored in the volatile register. n device power-up the volatile register may be loaded with all zeroes or it may be loaded from the contents of the 8- Bit nonvolatile register. ccess to the 8-Bit volatile register is obtained via the 2- wire interface at slave address BIN, word address 4. efer to Figures 8 and for details on programming and reading data from the 8-Bit register. When writing to the volatile register, the new output will become valid immediately at the end of the write command. eading the volatile register has no effect on the output. eading or writing the volatile register has no effect on the contents of the nonvolatile register. he 8-Bit NV register can only be accessed indirectly through the volatile register. he command sequence to communicate with the NV register is the same as that of the volatile register, ecept word address 6 is used instead of 4. When reading the NV register the data is first transferred into the volatile register where it may be accessed by the serial interface. Note that upon this transfer the output will change immediately to reflect the new data. imilarly, when writing to the NV register, the data is first placed in the volatile register. t the conclusion of the write command, an internal nonvolatile write sequence initiates the storage of the volatile contents into the NV register. UMMI MIELENI, Inc // 9

10 LING N FFE he can be customized to monitor a particular range of bias current by programming egister. Bits 3 and 2 control the scaling of the while bits and control the offset. he four graphs (Figures 4, 5, 6, & ) illustrate the scale values, according to the two bit code. In each Graph the curves are differentiated by the offset values. Note: if using I BI with the maimum current option set to m, divide the -ais value by (i.e., 5 =.5, etc.). hese combinations of scales and offsets allow the resolution to be maimized over a given range of current. For eample, if the bias current is known to be in the range of 3m to m the choice would be the Half scale graph (code BIN ) and the ¼ offset curve (code BIN ) to maimize the resolution of the. Note that these graphs assume a full scale bias current of m. When the is configured to receive input from the EX EM pin full scale current becomes 39.6µ, which limits the internal /256 scale factor between bias current and the input current UU ffset UU ffset I BI (m) 253 Fig I BI (m) 253 Fig5 Figure 4. Full cale (code BIN ) with ffset Figure 5. Half cale (code BIN ) with ffset UU ffset UU ffset I BI (m) 253 Fig I BI (m) 253 Fig Figure 6. Quarter cale (code BIN ) with ffset Figure. enth cale (code BIN ) with ffset // UMMI MIELENI, Inc.

11 EGIE EGIE BI M he has three user programmable, nonvolatile configuration registers. egister his register is used to configure the 8-Bit that monitors the bias current. Bit enables the alert to be latched, which will hold the LE pin low until the alert is reset. Bits 6, 5, and 4 are used to set the sample interval of the. he input to the can be scaled and offset to provide maimum resolution over the bias current. Bits 3 and 2 are used to set the full scale range of the, while bits and are used to set the offset. ee the able. egister his register controls multiple functions. Bit disables the alert during a manual analog-to-digital conversion of the bias current. Bit 6 selects the action that will reset an alert from the. When this bit is set to a any device read or write will reset the alert. When set to a the alert will be reset by a low UMN signal. Bit 5 is used to toggle the source of the input between the I BI current and the EX EM signal. Bit 2 initializes the input of the bit to either zero or a stored value from a nonvolatile register when the device is powered up. Bit initializes the input of the 8 bit to either zero or a stored value from a nonvolatile register when the device is powered up. Bit sets the maimum -channel bias current (I BI ) and modulation current (I M ) to either m or m. egister 2 his register controls several functions related to the bus interface. Bits and 6 control the read and write access to the configuration registers. It is imperative that register 2 be programmed properly to prevent an inadvertent lockout. Bit 5 determines whether the memory array is available or locked. Bit 4 selects the device type address for accessing the memory array, while bit 3 determines whether the device must receive a bus address that corresponds to the biasing of the address pins. Bit 2 is used to enable an alert condition on the to shut down the bias current. Bits & are unused lert ample UMMI MIELENI, Inc. Interval ange egister // ffset lert not latched lert latched Function 5µs sample interval 2µ s " " 6µ s " ".28ms " " 6.25ms " " 25ms " " 2ms " ".6s " " / full scale bias current /4 full scale bias current /2 full scale bias current Full scale bias current No offset /4 of full scale bias current offset /2 of full scale bias current offset 3/4 of full scale bias current offset 253 eg.

12 lert lert eset Input Unused -Bit 8-Bit I BI egister Function lert not allowed during manual conversion lert allowed during manual conversio n lert reset by ead or Write lert reset by Low on UMN pin I or I current input to BIN BI EX EM pin input to Input to is zero on power up Input to is from nonvolatile register on power up Input to is zero on power up Input to is from nonvolatile register on power up Ma current is m: I, I BI M Ma current is m: I I B I, M 253 eg egister ccess Memory ccess evice ddress in ddress lert ction egister 2 Unused Function ll egisters locked; no ead or Write ead all egisters; no Write Write all egisters; no ead ead and Write all egisters EEM available EEM locked evice ype dress is BIN evice ype dress is BIN esponds to address pin biased address only esponds to any bus address Bias current unaffected by alert condition lert condition shuts down bias current 253 eg // UMMI MIELENI, Inc.

13 BU INEFE GENEL EIIN he I 2 bus is a two-way, two-line serial communication between different integrated circuits. he two lines are: a serial ata line () and a serial lock line (). ll ummit Microelectronics parts support a khz clock rate, and some support the alternative 4kHz clock. heck the Electrical able for the value of f. he line must be connected to a positive supply by a pullup resistor located on the bus. ummit parts have a chmitt input on both lines. ee Figure X and able X for waveforms and timing on the bus. ne bit of ata is transferred during each lock pulse. he ata must remain stable when the lock is high. t t F t HIGH t LW t U: t H: t H: t U: t U: tbuf In t t H ut 253 Fig8 ymbol f tl W t t t t t H B IGH UF U: H : U: t t H t t F t t U: H I : t W UMMI MIELENI, Inc. aramete r Figure 8. I 2 ata iming onditions M in. Ma. able. I 2 ata iming // Units clock frequency khz lock low period 4. µ s lock high period 4. µ s Bus free time Before new transmissio n 4. µ s tart condition setup time 4. µ s tart condition hold time 4. µ s top condition setup time 4. µ s lock edge to valid output low to valid (cycle n) µ s ata ut hold time low (cycle n+) to change. 3 µ s and rise time ns and fall time 3 ns ata In setup time 25 ns ata In hold time ns Noise filter and Noise suppressio n ns Write cycle time 5 ms 253 able. 3

14 tart and top onditions Both ata and lock lines remain high when the bus is not busy. ata transfer between devices may be initiated with a tart condition only when and are high. highto-low transition of the ata line while the lock line is high is defined as a tart condition. low-to-high transition of the ata line while the lock line is high is defined as a top condition. ee Figure 9. rans ec Fig Figure. cknowledge iming ondition ondition In the case of a ead from a ummit part, when the last byte has been transferred to the, the will leave the ata line high for a N. his will cause the ummit part to stop sending data, and the will issue a top on the clock pulse following the N. In 253 Fig9 Figure 9. I 2 tart and top iming rotocol he protocol defines any device that sends data onto the bus as a ransmitter, and any device that receives data as a eceiver. he device controlling data transmission is called the, and the controlled device is called the lave. In all cases the ummit Microelectronic devices are slave devices, since they never initiate any data transfers. cknowledge ata is always transferred in 8-Bit bytes. cknowledge () is used to indicate a successful data transfer. he ransmitting device will release the bus after transmitting eight bits. uring the ninth clock cycle the eceiver will pull the line low to cknowledge that it received the eight bits of data (ee Figure ). he termination of a ead sequence is indicated by a non-cknowledge (N), where the will leave the ata line high. In the case of a Write to a ummit part the will send a top on the clock pulse after the last cknowledge. his will indicate to the ummit part that it should begin its internal non-volatile write cycle. ead and Write he first byte from a is always made up of a seven bit lave address and the ead/write bit. he /W bit tells the lave whether the is reading ata from the bus or writing ata to the bus ( = read, = write). he first four of the seven address bits are called the evice ype Identifier (I). he I for the is. he net three bits are not used in the (ee Figure ). he will issue an cknowledge after recognizing a tart condition and its I. In the read mode the transmits eight bits of data, then releases the line, and monitors the line for an cknowledge signal. If an cknowledge is detected, and no top condition is generated by the, the will continue to transmit data. If an cknowledge is not detected (N) the will terminate further data transmission. ee Figure /W 253 Fig Figure. ypical ddress Byte ransmission // UMMI MIELENI, Inc.

15 / W N ptional lave Figure 2. ead 253 Fig2 / W W lave 253 Fig3 Figure 3. Write In the write mode the receives eight bits of data, then generates an cknowledge signal. It will continue to generate s until a top condition is generated by the. ee Figure 3. andom ddress ead andom address ead operations allow the to access any memory location in a random fashion. his operation involves a two-step process. First, the master issues a write command which includes the start condition and the lave address field (with the /W bit set to Write) followed by the address of the word it is to read. his procedure sets the internal address counter of the to the desired address. fter the word address acknowledge is received by the, it immediately reissues a start condition followed by another lave address field with the /W bit set to ead. he will respond with an cknowledge and then transmit the 8 data bits stored at the addressed location. t this point, the does not acknowledge the transmission, but does generate a top condition. he discontinues data transmission. equential E equential eads can be initiated as either a current address ead or a random access ead. he first word is transmitted as with the other byte read modes (current address byte ead or random address byte ead). However, the now responds with an cknowledge, indicating that it requires additional data. he continues to output data for each cknowledge received. he terminates the sequential ead operation by not responding with an cknowledge, and issues a top condition. uring a sequential read operation the internal address counter is automatically incremented with each cknowledge signal. For ead operations all address bits are incremented, allowing the entire array to be read using a single ead command. fter a count of the last memory address the address counter will roll-over and the memory will continue to output data. he protocol for reading and writing to the registers and the lookup table are illustrated in Figures 4 through 24. UMMI MIELENI, Inc // 5

16 IMING IGM evice / ddress W ata Byte n ata Byte n+ ata Byte n+5 Word ddress lave 253 Fig4 Figure 4. Look-up able age/byte Write evice / ddress W evice ddress / W N Word ddress ata Byte lave 253 Fig5 Figure 5. Look-up able andom ddress ead with ummy Write evice / ddress W evice / ddress W First ata Byte Last ata Byte N Word ddress lave 253 Fig6 Figure 6. Look-up able equential ead with ummy Write // UMMI MIELENI, Inc.

17 evice / ddress W Location ddress lave 253 Fig Figure. 8-Bit Volatile egister Write evice / ddress W Location ddress evice / ddress W N lave 253 Fig8 Figure 8. 8-Bit Volatile egister ead with ummy Write evice / ddress W Location ddress lave 253 Fig9 Figure 9. 8-Bit Non-volatile egister Write evice / ddress W Location ddress evice / ddress W N lave 253 Fig2 UMMI MIELENI, Inc. Figure 2. 8-Bit Non-volatile egister ead with ummy Write //

18 evice / ddress W Location ddress lave 253 Fig2 Figure 2. -Bit Volatile egister Write evice / ddress W Location ddress lave 253 Fig22 Figure 22. -Bit Nonvolatile egister Write evice / ddress W Location ddress evice / ddress W N lave 253 Fig23 Figure 23. -Bit Volatile egister ead with ummy Write evice / ddress W Location ddress evice / ddress W N lave 253 Fig24 Figure 24. -Bit Nonvolatile egister ead with ummy Write // UMMI MIELENI, Inc.

19 LIIN LIIN EXMLE UING EXENL EM- EUE INU he EX EM pin of the allows the input of the internal to be driven from an eternal device, rather than a mirrored version of the bias current. Figure 25 shows an eample using a National emiconductor LM334 to deliver a current into the that is proportional to absolute temperature. he scale and offset features of the input can be used to center this current and maimize the full range of the look-up table. For this application the current I E coming out of the LM334 and into the EX EM pin of the is given by the following equation: I E = 22µV / o / E For eample, using a value of 2Ω for E yields a current of 295µ at o and 38µ at 85 o. Net select scale and offset values of the input that will optimize the current range of the LM334. Nominal fullscale input current of the is 39.6µ (= m/256). By setting the input offset to ¾ scale (293µ) and the fullscale range to ¼ scale (9.6µ), then the zero scale of the internal becomes 293µ, and the full-scale is 39.6µ. his represents a temperature range of approimately 2 o to 88 o using a 2Ω resistor in the configuration shown. (hese settings correspond to configuration egister, Bits 3 - set to HEX.) 5V + LM334 E 2Ω ±% I E 253 Fig25 EX EM Figure 25. Eample of an Eternal emperature ensing evice UMMI MIELENI, Inc // 9

20 GE 48 IN QF GE B EIL "".3.6 ref in B mm. in ma EIL "B" ckg. EING INFMIN F Base art Number ackage F = 48 in QF // UMMI MIELENI, Inc.

21 NIE UMMI Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. UMMI Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. harts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user s specific application. While the information in this publication has been carefully checked, UMMI Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. UMMI Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be epected to cause any failure of either system or to significantly affect their safety or effectiveness. roducts are not authorized for use in such applications unless UMMI Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of UMMI Microelectronics, Inc. is adequately protected under the circumstances. opyright 2 UMMI Microelectronics, Inc. I 2 is a trademark of hilips orporation. UMMI MIELENI, Inc // 2