O.13f-Lm 1.OV-l.5V Supply Digital Blocks for 40-Gb/s Optical Communication Systems

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1 O.13f-Lm 1.OV-l.5V Supply Digital Blocks for 40-Gb/s Optical Communication Systems Bangli Liang, Tad Kwasniewski Department of Electronics Carleton University Ottawa, Ontario, Canada Zhigong Wang Department of Radio Engineering Southeast University Nanjing, Jiangsu, China Dianyong Chen, Bo Wang, Dezhong Cheng Department of Electronics Carleton University Ottawa, Ontario, Canada Abstract-Low supply digital blocks for OC-768/STM-256 optical communication systems such as 1:2 demultiplexer (DE MUX), 2:1 multiplexer (MUX), 2:1 frequency divider and data decision circuit in 0.13fLm CMOS are presented. All proposed blocks are based on fully differential MOS current-mode logic (CML). Multi-stage output buffers are used to drive the external son loads. On-chip shunt peaking (SP) inductors and split resistor (SR) loads are used to boost the bandwidth. High output resistance current sources are employed to achieve flat current source characteristic and allow the designed ICs to operate stably with wide process, voltage and temperature (PVT) variations. The main contribution of this work is that four proposed circuits can work at 40-Gb/s and beyond under a IV supply and consume low currents. I. INTRODUCTION Current serial data communication systems operate at bit rates between 10- and 40-Gb/s and communication ICs are mainly implemented in compound semiconductor processes. Several high-speed chips in standard CMOS technologies are reported in [1]-[9], which confirm CMOS to be a viable economical alternative for broadband circuit design. Blocks in optical communication systems such as CMOS MUXs, DE MUXs, data decision circuits and frequency dividers already achieve bitrates higher than 20-Gb/s or operating frequency higher than 20GHz [1 ]-[9]. In this work, a 50-Gb/s 1:2 DEMUX, a 50-Gb/s 2: 1 MUX, a 42-Gb/s decision circuit and a 43GHz 2: 1 frequency divider in 0.13j.Lm CMOS and some important circuit techniques are presented. II. CIRCUIT TECHNIQUES AND DEVICE CHARACTERISTIC The critical components in a 40-Gb/s transceiver are: the buffer amplifiers for the 20GHz clock and 40-Gb/s random bit stream, the 2: 1 MUX for serializing the 40-Gb/s bit stream, the full rate VCO and the clock divider operating at 40GHz. It is still very challengeable to implement digital blocks in low supply CMOS for 40-Gb/s transceiver. Since such a high speed is well beyond the reach of conventional CMOS designs, some circuit techniques such as inductive peaking, split resistor load must be introduced to achieve the bandwidth and timing required for transmitting a 40-Gb/s NRZ bit stream. A. Differential MOS CML Since differential signals provide sufficient noise margin even with reduced voltage swings, fully differential CML principle which decreases the internal voltage swing and therefore guarantees high operation frequencies is used for 40-Gb/s operation [10]. B. Split Poly-Silicon Resistor Load Poly-silicon resistors with SR topology (R 1 and R 2 are separated by output node) shown in Fig.1 are used as loads, which is the fastest non-enhanced amplifier. The advantages of this amplifier can be seen that: Unsilicided poly is a pretty efficient current provider (i.e., has a good current to capacitance ratio); Output swing can go all the way up to Vdd; Allows following stage to achieve high it; Linear settling behavior (in contrast to NMOS load). On the other hand, the bandwidth and gain limitations can be estimated below: c'-r1 You! Vdd I Vdd did 2Id gm == - == (1) dv gs Vcs - VT A v == gmrl == 2IdRl _ 2VR 1 (2). Vcs - VT Vcs - VT 1 i -3dB == (3) 27rR 1 C tot Ctot = Cdb, + C;, + C gs2 + KC OV2 + Cjixed (4) Where, gm is the transconductance of the transistor; A v is the DC gain; f -3dB is the -3dB bandwidth; C tot is the total capacitance at the output node; K is Miller multiplication factor which can be adjusted by optimizing the ratio of R 1 /R 2 for given constant load resistance R == R 1 + R 2. Based on above equations, poly-silicon resistors with SR topology can Fig. 1. Common source amplifiers with Split resistor, Shunt peaking, and Split resistor, shunt peaking and series peaking /08/$ IEEE 1255

2 1500, ,-,-,,-==_=_----, ,, L=128pH 'I'... L=210pH...::: ;;::...:...tt To l._; 10 :::::::::. ':;'-:;'r "::::: ,5 E_5,0 11RVT'NMOS C;;-rrent S;rce I 2 LVT NMOS Current Source 3Cascode Current Source 4 Stacked Current Source Fig. 2. Thick metal inductor. Q vs. frequency. L vs. frequency. Fig. 3. Current sources. Schematic. ID vs. VDS' be used as low capacitive loads to reduce parasite capacitances and Miller Effect further, which is a compromise between high internal signal swing (DC gain) and small RC time constant. It is important for high speed digital circuits to introduce such an additional design parameter, the ratio of R 1 IR 2. C. Shunt and Series Peaking Inductors The maximum speed of the flip-flop is limited mainly by the parasitic capacitances of the transistors and the layout. Therefore, spiral inductors are connected in series with the load resistors as shown in Fig.l. This inductive peaking enhances the operating bandwidth without deteriorating the low-frequency response. Although on-chip inductors have low factors due to the limited conductivity of the metal, substrate loss, and parasitic capacitance, a high quality factor Q of the spiral inductors is not required because the effective Q is determined by the poly-silicon load resistors that are connected in series to the inductors. However, it is important that the inductors have high self-resonant frequency. This is achieved by using only the two topmost metal layers to reduce capacitance to the substrate. Spacing between adjacent turns of the inductor is made wider than required by the design rules to reduce tum-to-turn capacitance. As shown in Fig.2, the used inductors have both sufficiently high self-resonant frequency and high quality factor Q at operating frequency, which is a guarantee for high speed operation. Both spiral inductors and bonding wire inductors are often used as shunt peaking inductors. However, additional pads and poor accuracy control for bond inductors is hardly acceptable for the required chip area and integration density. For 40-Gb/s operation, it makes sense to use inductive peaking inductors only at the fastest part of the system. Shunt peaking can improve the bandwidth by approximately 500/0, assuming the use of on-chip inductors. Another technique to enhance the bandwidth of CML circuits is series peaking. An inductance is connected in series to the output of the CML circuit as shown in Fig.l. The output network acts as a filter which consists of various parasitic capacitances, load resistors, bond inductances, and on-chip inductors. Series peaking can additionally improve the bandwidth by approximately 45% when combined with shunt peaking. Series peaking makes sense if it is used in combination with shunt peaking. If only series peaking is used, then the enhancement in bandwidth is low. Using series peaking and shunt peaking can nearly double the bandwidth of a CML circuit. However, series peaking is seldom used in compact chips for low cost applications. D. Stacked Current Source In Fig.3, the proposed current source 4 consists of two stacked NMOS transistors. The upper transistor is a low-vi (LVT) device (Vi 260mV) and the bottom is a regular Vi (RVT) (Vi 350mV) device, and they are connected in series. This configuration increases the output resistance of the current source. Ignoring the body effect, the output resistance of the stacked current source approximately is: Rout == ro + ro (1 + gmro) == 2ro + grnr gmr (5) Where, r 0 is output resistance of LVT and RVT devices, assuming that they have the same output resistance. This results in a flat current source characteristic as shown in Fig.3. Even though the stacked current source is just a little bit better than the conventional cascode current source, the number of used transistors is reduced and no additional DC bias is required. The main disadvantage of stacked current sources is higher operating voltage to keep the devices in saturation. However, the minimum operating voltages of four current sources are almost same as 250mV based on Fig.3. In addition, stacked LVT and RVT NMOS transistors with a channel length of 180nm are used as current source to reduce short channel effects and geometric mismatches. Both latches and buffers in this design use stacked current sources to achieve excellent immunity against PVT variations. E. Device Aspect Ratio Optimization For high speed switch circuits, there is a basic trade-off between high input sensitivity and high switch speed limited by output capacitance and outside loading capacitance. Transistors in data path of latches have much smaller width than that of transistors in clock path. Larger clock devices are used to increase the input sensitivity while the relatively larger input capacitances are partly canceled by input matching network. LVT NMOS devices are used in high frequency parts, because of their higher speed compared to RVT NMOS transistors under same gate-source voltage Vcs as shown in Fig.4. As to DEMUX, decision circuit and frequency divider, the crosscoupled transistor pair used in the latch is one of the largest 1256

3 N I c V Gs ( mv) 1500 N I ::: 50.,..."..." oj V Ds=1.5V o V Ds=1.2V * V Ds=09V IV VQ=05V V Gs ( mv) 1500 Fig. 5. Broadband output buffers. For DEMUX. For decision circuit. For frequency divider. Fig. 4. it VS. VCS curves of 0.13j.Lrn NMOS. (2j.Lrnx IO)/O.12j.Lrn LVT and RVT devices. (5j.Lrnx IO)/0.12j.Lrn LVT device under various VDs. contributors to the output capacitance. In other words, smaller size in hold branch than that in sampling branches would help to reduce parasitic capacitance further. However, the device size in hold branch should be large enough to maintain a particular logic state at the appropriate clock phase and to avoid large duty cycle distortion. For MUX, there is no crosscoupled transistor pair in the latch, so the devices in data path should have the same size. Finally, the optimized aspect ratio of W Data/WClock are achieved as: TVData/WClock=3/5 for DEMUX to offer enough voltage gain for 20-Gb/s output signal; 1VData/TVClock=1/3 for MUX to provide an intermediate gain and sufficient bandwidth for 40-Gb/s serialized data stream; W Data/TVClock=2/15 for frequency divider and decision circuit to increase the input sensitivity for 40GHz input clock. F. Broadband Input Matching On-chip broadband input matching for clock path is realized with low resistance (50n to 250n) poly-silicon resistors (some buffers also employ low inductance inductors to cancel large input capacitances in clock path) shown in Fig.6, which also acts as a DC level shifter and ESD protection to allow accoupling of the clock input. This input DC level was optimized for fast switching. The used DC level shifters provide a DC level of 0.5Vdd for MUX, DEMUX, decision circuit but a 0.6Vdd for clock divider. G. Multiple-Stage Output Buffer Limited bandwidth is a big challenge for high speed buffer design, which can be relaxed by the inductor-peaking network. Large input/output swing requirement is another challenge in designing such a buffer. The required large voltage swing causes the input transistor pair to operate partially in the triode region, introducing non-linearity. Therefore, the waveforms on the two output nodes become asymmetric. The frequency response for both the rising-step output and the falling-step output had to be optimized. This problem can be partly relieved by optimizing the ratio of R 1 / R 2 in split resistor topology mentioned above. The proposed buffers in Fig.5 consist of multiple-stage differential amplifiers in series which are not for voltage gain, but are required for driving the external 50n load. In each stage the tail current is twice the current of the previous stage. The first stage offers a high-voltage swing, which drives the second stage. For Fig.5 and, the second stage works as a limiting amplifier to provides appropriate amplitude, proper common-mode level. The last differential amplifier is designed to provide enough driving capability and good matching to external 50n loads. H. it Maxinlization and DC Bias Optilnization Peak it values have been stuck at around 100GHz for the most advanced Si technologies. In fact, a 100GHz it is not enough for 40-Gb/s digital circuits with a supply of 1.2V and below because there is no device in latches operating under Vcs > O.6V and VDS > O.8V. From Fig.4, it is necessary to keep Vcs 2: O.45V and VDS 2: O.25V for devices in data and clock paths so as to maximize the effective it. From Fig.4, using LVT devices in both data and clock paths would be much better than employing RVT transistors for low supply (1 V to 1.5V)operations. Therefore, the common mode DC level of data and clock transistor pairs should be optimized by corresponding requirements. In this design, Vcs O.5V and VDS O.5V is chosen for devices in data path to achieve enough transconductance, Vcs O.5V and V DS O.25V is selected for clock pair to achieve enough switching speed and to save voltage headroom for other transistors, Vcs=O.45V O.8V and VDs=O.25V-O.8V are adopted for differential pairs in output buffers. I. Layout Techniques Since a differential design is applied, the layout is devised to be maximally symmetrical to keep the circuit as balance as possible for high immunity against common-mode disturbances. Furthermore, all interconnects are kept as short as possible. Especially the lines between slave outputs and master inputs of clock divider are affecting the maximum operation frequency, because of their propagation delay and capacitive load. Input signal pads and output signal pads are placed perpendicularly to minimize possible crosstalk. Data path and clock path are separated as far as possible to lower possible interference. Additionally, "SGS" and "PSGSP" pad patterns are used for high symmetry, low disturbance and easy on-chip test, where "P", "G", "S" represent "power supply", "ground" and "signal" terminals, respectively. The layout of the proposed DEMUX is shown in Fig.7 as an example to illustrate the layout tricks mentioned above. 1257

4 Iv1 r;plrl ct ----"'1! g Fig. 7. Layout of 1:2 DEMUX. Fig. 6. Proposed circuits. Latch in DEMUX. Decision circuit core. MUX with a buffer. (d) Frequency divider core. (d) III. PROPOSED DIGITAL BLOCKS In this section, four key building blocks in a 0.13/-Lm CMOS process are described. Since such a high speed is well beyond the reach of conventional CMOS designs, circuit techniques discussed in Section II are adopted to achieve the bandwidth and timing required for transmitting a 40-Gb/s NRZ bit stream. The schematic of proposed circuits are shown Fig.6. The 1:2 DEMUX consists of two MS-FFs and output buffers. Each MS-FF includes two latches connected in series. When a 40-Gb/s data stream is applied, the MS-FFs are clocked at 20GHz. To sample every bit of the 40-Gb/s input data, the clock of one MS-FF is in phase while the other one is inverted. A separate buffer for each output decouples the MS FFs from the 50-f2 environment. All transistors in the core are LVT 120nm NMOS devices for low supply (1.2V or less) operation. The latches showed in Fig.6 use series gating between clock and data inputs. Poly-silicon resistors are used as loads which is a compromise between high voltage swing and reasonable RC time constant. Clock input matching is realized with 50n on-chip resistors, which are connected to a DC level shifter (Vdd/2). The tail current of all latches is set to 7mA. The MUX in Fig.6 uses low resistance poly-silicon resistors with SP inductors in series as loads to achieve enough bandwidth. The tail current of all latches is set to 10mA. Due to the small load resistors and large tail current, only a single-stage output buffer is employed. To achieve sufficient voltage gain, both devices in data path and the differential pair of buffer amplifier use large size. The adopted 10mA tail current and SP inductors will compensate the excessive parasitic capacitance. The decision circuit consists of a MS-FF in Fig.6 and a 3-stage output buffer in Fig.5. The MS-FF is clocked at 40 GHz. The tail current of both latches is set to 6mA. To achieve full voltage swing, at least 20-GHz bandwidth is needed for the latches and output buffer. To enhance the bandwidth, SP and SR are implemented using on-chip spiral inductors and polysilicon resistors with an optimal resistance ratio of R 1 / R 2 == 3/2, respectively. The internal dividing function of this divider is based on a MS-FF by connecting the inverted slave outputs to the master inputs. The tail current of both latches is set to 7mA. To achieve very high operating frequency and low clock jitter, SR with a ratio of R 1 / R 2 == 1/1 as shown in Fig.6(d) is used and SP are implemented using on-chip spiral inductors with high Q-value as shown in Fig.2. Conventional static divider topology rather than power-economical resonance techniques is used here to achieve wider frequency range and better immunity against PYT fluctuations. IV. CIRCUIT SIMULATIONS To verify the proposed digital blocks, circuit simulations are carried out using the simulator, Cadence Spectre, and BSIM4 model based on IBM 0.13/-Lm CMOS technology. Differential pseudo-random bit sequences (PRBS) of is used as data signal and differential sinusoidal waveform is employed as clock signal for transient analyses. Fig.8 shows the simulated eye-diagrams of the 20-Gb/s differential output signal from the DEMUX. Based on simulated data, the used SP inductors along with the output buffers greatly boosted the bandwidth, which resulted in an effective signal amplitude from up to 2 x 400mV pp and a peak to peak (PP) jitter of 7.2ps. Post-layout simulations are done for higher data rates and PVT (process, voltage and temperature) variations, respectively and it turned out that the proposed DEMUX can operate up to 50-Gb/s under a supply voltage of 1.2V and can operate well at 40-Gb/s under various PVT conditions. As illustrated in Fig.8, the MUX can achieve a bit rate of 40Gb/s with an output amplitude of 2 x 500mV pp and a PP jitter of 3.8ps. Fig.8 shows the 40-Gb/s output eye-diagrams of the data decision circuit. The effective signal amplitude can go up to 2 x 550mV pp and the peak-to-peak (PP) jitter can be reduced 1.7ps simultaneously using SP, SR bandwidth 1258

5 .. : FF 1.5V -55DEG TABLE II PERFORMANCE COMPARISON OF CMOS MUX Reference Bitrate Ratio Ptotal Supply Technology (Gb/s) (mw) (V) CMOS [1] 40 4: nm [2] 40 2 : nm This work 50 2 : J.Lm > > j 0.8 Ql 0.4 ::J 0.0 * *', ** \.. I..... *,I' '** ",./:' **.- V3 ** ' l' I j* /' : -. -V2" I\. *-V TABLE III PERFORMANCE COMPARISON OF CMOS DECISION CIRCUIT Reference Bitrate Platch Ptotal Supply Technology (Gb/s) (mw) (mw) (V) CMOS [4] nm This work O.l3J.Lm TABLE IV PERFORMANCE COMPARISON OF CMOS FREQUENCY DIVIDER Fig. 8. Simulated data. DEMUX 20-Gb/s output. MUX 40 Gb/s output. Decision circuits 40-Gb/s output. (d) Input sensitivity of frequency dividers. VI-Conventional topology. V2-With SP inductors. V3 With SP inductors and SR load resistors. TABLE I (d) PERFORMANCE COMPARISON OF CMOS DEMUX Reference Bitrate Ratio Ptotal Supply Technology (Gb/s) (mw) (V) CMOS [1] 40 1: nm [2] 40 1 : nm This work 50 1 : J.Lm boosting techniques and the output buffer in Fig.5. The resistance ratio R 1 / R 2 of the used SR loads was optimized. Post-layout simulations are done for higher data rates and PVT variations. The proposed decision circuit can operate up to 42 Gb/s under supply voltages from 1.0V to 1.5V. Simulated input sensitivity curves of three frequency divider topologies operating under 1.2V supply are given in Fig.8(d). The frequency divider (V3) with SP and SR can operate up to 44 GHz, which confirms that the elnployed on-chip spiral SP inductors and SR loads can improve the operating speed of CML circuits up to 50%. Simulation summary and the comparison to previous works are given in TABLE I-IV. According to the simulation and post-layout simulation data, the designed circuits can operate at 40-Gb/s and beyond under lower supply and consume lesser power. It can be seen that the employed stacked current sources offer very good immunity to PVT fluctuations and the circuit bandwidth has been greatly improved by the used on-chip inductors. V. CONCLUSION Low supply ICs in 0.13JLm CMOS for OC-768 communication systems are proposed and verified. All blocks use fully balanced CML topologies for 40G/s operation. SP coils and SR loads are the major contributors of circuit bandwidth extension, which is confirmed by simulation data. Stacked Reference Supply frnax 7N Power Technology (V) (GHz) (mw) CMOS [5] nm [6] J.Lm [7] O.l3J.Lm [8] nm [9] J.Lm This work O.l3J.Lm current sources are used to ensure that the designed circuits can operate stably in a wide supply range(1v-i.5v) and have high manufactureability. Compared with previously reported circuits, all the proposed circuits can work well under a lower supply (I V). REFERENCES [1] K. Kanda and et al. "40Gb/s 4: 1 MUX/l:4 DEMUX in 90nm Standard CMOS". In IEEE Int. Solid State Circuits Conf Dig. Tech. Papers, pages , February [2] D. Kehrer, H.-D. Wohlmuth, H. Knapp, M. Wurzer, and A. L. Scholtz. "40Gb/s 2: 1 Multiplexer and 1:2 Demultiplexer in 120-nm Standard CMOS". In IEEE J. Solid-State Circuits, 38(11): , [3] A. Rylyakov, S. Rylov, H. Ainspan, and S. Gowda. "A 30Gb/s 1:4 Demultiplexer in O.l2J.Lm CMOS". In IEEE Int. Solid State Circuits Conf Dig. Tech. Papers, pages , February [4] T. Chalvatzis, K. H. K. Yau, P. Schvan, M. T. Yang, and S. P. Voinigescu. "A 40Gb/s Decision Circuit in 90-nm CMOS". In Pmc. Eur. Solid State Circuits Conf, pages , September [5] G. von BUren, C. Kromer, F. Ellinger, A. Huber, M. Schmatz, and H. Jackel. "A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS". In IEEE Int. Solid State Circuits Conf Dig. Tech. Papers, pages , February [6] J. Lee and B. Razavi. "A 40GHz Frequency Divider in 0.18J.Lm CMOS Technology". In IEEE J. Solid-State Circuits, 39(4): , [7] U. Singh and M. M. Green. "High-Frequency CML Clock Dividers in 0.13J.Lm CMOS Operating Up to 38GHz". In IEEE J. Solid-State Circuits, 40(8): ,2005. [8] H.-D. Wohlmuth and D. Kehrer. "A High Sensitivity Static 2: 1 Frequency Divider Up to 27 GHz in 120 nm CMOS". In Proc. Eur. Solid State Circuits Conf, pages , September [9] H. Knapp, H.-D. Wohlmuth, M. Wurzer, and M. Rest. "25GHz Static Frequency Divider and 25Gb/s Multiplexer in O.l2J.Lm CMOS". In IEEE Int. Solid State Circuits Conf Dig. Tech. Papers, pages , February [10] M. M. Green and U. Singh. "Design of CMOS CML Circuits for High Speed Broadband Communications". In Proc. IEEE Int. Symp. Circuits and Systems" volume II, pages , May