CHAPTER 3 VLSI IMPLEMENTATION OF DIP-BASED ADULTERATION IDENTIFICATION IN FOOD SAMPLES

Transcription

1 42 CHAPTER 3 VLSI IMPLEMENTATION OF DIP-BASED ADULTERATION IDENTIFICATION 3.1 INTRODUTION IN FOOD SAMPLES The deliberate contamination of food materials with low quality, cheap, non-edible or toxic substances is called food adulteration. The substance, which degrades (lowers) the quality of a food is called an adulterant [17]. Adulteration results in two disadvantages for the consumer 1. Overpaying for substandard food stuff. 2. Some adulterants are injurious to health and can even result in death. The main motive of adulteration is to gain undue profits. Chemicals which cause harmful reaction when consumed by animals or humans are said to be toxic [22]. It turns out that almost everything is a toxicant or poison if consumed at a high enough level. The use of chemicals in the production and processing of food and food products not only affects the quality, but also disguises the deterioration and constitutes deliberate adulteration which is potentially very harmful to health. It is advised that food additives like coloring matter, preservatives, artificial sweetening agents, antioxidants, emulsifiers/stabilizer, flavors/flavor enhancers etc., if used, should be of approved quality and processed under good manufacturing practices [26], [44]. In this chapter, different types of food samples are selected and the images are acquired and calibrated. This is kept as a reference image. Then the sample which is to be tested (whether it is adulterated or not) is checked by comparing it with the reference image [27], [48]. The color variation in the process shows the adulteration. Digital Image

2 43 Processing (DIP) is versatile, reliable and a low-cost tool for color based classification of fresh produce, with the potential to replace other more costly techniques [50]. This chapter discusses the VLSI implementation of DIP-based adulteration identification in food samples. Section 3.2 discusses chemical reaction-based adulteration detection. In Section 3.3, the VLSI-based proposed system is discussed. Section 3.4 deals with results and discussions. Finally conclusion is drawn in Section CHEMICAL REACTION-BASED ADULTERATION DETECTION METHOD The chemical reaction-based adulteration detection test is done by taking 2 gm of the sample in a test tube, adding a little solvent ether. Ether layer is placed into a test-tube containing 2 ml of dilute HCl acid and is shaken. The result is a pink to red color red lower acid layer in chilly powder and the remark is 8.69 percent or the respondents used subbranded Apex chilly powder. These dyes are toxic and intake of excess could lead to abnormalities of eyes, bone, skin, lungs etc. The inclusion of undeclared or unapproved color additives renders a spice adulterated, and if the color is undeclared, the spice is also misbranded [32]. Recent examples include turmeric and other color additives in paprika, Sudan Red I in chilly powder, and various color additives in saffron. Such instances may present a public health risk [33]. 3.3 PROPOSED VLSI-BASED SYSTEM The general block diagram of the proposed system is shown in Figure 3.1. Camera is placed at 20 cm altitude from the bottom of the stand. The intensity of light source is 10 candelas and the room temperature is maintained. The bottom surface color is white. The samples are placed on the white surface.

3 44 This chapter proposes to replace the existing methods with VLSI implementation. In the VLSI implementation, the images are compared with standard image stored inside the FPGA with DVM algorithm. By using this system the adulteration can be identified. It is helpful for high-speed comparison of images according to the pixel intensity value. The design is implemented using VHDL. FPGA Virtex-4 has been used for the hardware implementation. The proposed method is an improvement over traditional software package-based approaches. First, the image of chilly powder sample is taken by camera and converted into bit file format and then stored in FPGA. Next, various levels of Brick Powder adulterant added to chilly powder sample are taken by camera and converted into bit file format and fed into FPGA. Finally, chilly powder sample is compared to brick powder adulterant added to chilly powder samples by using distance vector matrix algorithm. This algorithm execution is based on pixel by pixel comparison in FPGA. On comparing two images, if difference occurs it is concluded that the sample is adulterated otherwise it is not adulterated. A Region of Interest (ROI) is a portion of an image that one wants to filter or perform some other operation on. An ROI can be defined by creating a binary mask, which is a binary image that is of the same size as the image one wants to process with pixels that define the ROI set to 1 and all other pixels set to 0. The regions can be geographic in nature, such as point, line, circle, polygon, or simply as a list of virtex positions polygons that encompass contiguous pixels, or they can be defined by a range of intensities. Here, the ROI is defined by the intensity range, where the pixels are not necessarily contiguous.

4 45 FPGA (high speed image comparison algorithm implementation) RS-232 Cable Image taken from food sample adulteration using CCD camera Camera Difference=0(Food sample not adulterated) Difference=1 (Food sample is adulterated) Figure 3.1 General block diagram of food adulteration detection unit Figure 3.1 shows the general block diagram of food adulteration identification unit, which consists of high resolution CCD camera, RS-232 cable and FPGA unit. Here, CCD camera is working as an image acquisition unit. RS-232 cable connects the FPGA system and camera Distance Vector Matrix Algorithm where δ=difference, =Standard Image, =Field Image Distance Measure The distance between any two pixels in a given image can be given by three different types of measures and they are 1. Euclidian Distance The Euclidian distance between p and q is defined as where (x 1, y 1 ) and (x 2, y 2 ) are the coordinates of the pixel p and q, respectively.

5 46 2. Distance The distance also called as city-blocking distance between p and q is defined as 3. Distance The distance also called chessboard distance between p and q is defined as Steps for DVM Algorithm Get the reference and sample images Resize the reference and sample images Convert the images into bit file format Choose the region of interest Set a threshold value Find the pixel by pixel difference between the two images Square the difference Sum up all the squared differences If the difference is zero, the food sample is declared as not adulterated else it is declared as adulterated

6 Simulation environment Family Device Synthesis Tool Package Simulator : Virtex4 : XC4VLX15 : XST (Verilog/VHDL) : SF363 : Modelsim SE-VHDL Image Size : 256*256 RAM size Processor : 2 GB : Core2Duo Software : Cadence Electronic Design Automation (EDA) Tool, Matlab 6.1, Xilinx ISE 8.2i Programming Language : VHDL, Verilog Hardware Description Language (HDL) Table 3.1 gives the camera property of food adultration detection unit which involves dimension, width, height, resolution, speed, focal length and model. Camera acts as an image aquisition unit. It is an important input to the system because images play a vital role in adulteration identification unit.

7 48 Table 3.1 Camera properties of food adulteration image capturing unit Property Value Dimension 4000 X 3000 Width Height Horizontal Resolution Vertical Resolution 4000 pixels 3000 pixels 300dpi 300dpi Bit Depth 24 Compression Resolution Unit 2 Color Representation Compressed bit/pixel Camera Maker srgb Nokia Camera Model N8-00 F-stop Exposure-time ISO-Speed Exposure bias Focal length f/2.8 1/8 sec ISO-494 6mm 3.4 RESULTS AND DISCUSSIONS Reference image and the sample image which are to be tested are taken as input. Chilly powder is taken and 5gm, 10gm, 15gm and 20gm of brick powder is added to the chilly powder in the consecutive stages, and the photographs are taken in each step. Colour variation clearly shows the adulteration in the successive steps. Finally, it creates a database for training purpose.

8 49 Figure 3.2 Image of chilly powder Figure 3.3 Image of brick powder adulterant added chilly powder Figure 3.3 shows the image of adulterated chilly powder. 50 gm of chilly powder is taken as sample. This is shown in Figure 3.2. The two images are compared using DVM algorithm. During the training phase at FPGA, each and every time adulterated chilly powder is compared with the reference image. The comparison takes place pixel by pixel based on Distance Vector Matrix algorithm. Figure 3.4 Image of milk powder Figure 3.5 Image of whey powder adulterant added milk powder In the same way milk power is adulterated with whey powder and the images are photographed, processed and are shown in Figure 3.4 and Figure 3.5.

9 50 Figure 3.6 Image of coffee powder Figure 3.7 Image of chicory powder adulterant added coffee powder Figure 3.6 and Figure 3.7 show that the pixel intensity varies from coffee powder to chicory powder adulterant added coffee powder. The adulterated coffee powder sample image appearance is darker compared to the sample image. The comparison takes place pixel by pixel of the image based on distance vector matrix algorithm. The VLSI implementation of adulteration identification unit consists of the following steps involving logical simulation, register transfer level (RTL) simulation, technology simulation, Input/output (I/O) pin assignment, placement of I/O pins, floor planning, routing, layout and FPGA implementation.

10 51 Figure 3.8 VHDL output of the proposed system Figure 3.8 shows the simulation output of Arithmetic Logic Unit (ALU), in the Distance Vector Matrix (DVM) algorithm where the arithmetic operation alone is executed. The image bit file acts as input of the simulation. Addition, subtraction and multiplication operations are frequently executed. Logical operation consists of AND, OR, NOT, XOR, rotate left and right. Logic simulation may be used as part of the verification process in designing hardware. Simulations have the advantage of providing familiarity to the user in that it is constructed from the same language and symbols used in design. By allowing the user to interact directly with the design, simulation is a natural way for the designer to get feedback on their design.

11 52 Figure 3.9 RTL schemata of food adulteration identification IC unit Figure 3.9 shows the second step of VLSI implementation. It represents the register transfer level, which is involved in combination of register for corresponding VHDL program of food adulteration identification unit. Registers act as a temporary storage element. In digital circuit design, RTL is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. RTL abstraction is used in HDLs like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.

12 53 Figure 3.10 Technology schemata of food adulteration identification IC unit Figure 3.10 shows the technology schematic of food adulteration identification unit. It shows the number of logical register blocks present in the food adulteration identification unit, which is helpful for calculating the available registers at VLSI. Using an EDA tool for synthesis, this description can usually be directly translated to an equivalent hardware implementation file for an ASIC or an FPGA. The synthesis tool also performs logic optimization. The larger the number of registers, the greater the power consumption and area and lesser the speed. Registers are used for storing all the processing data.

13 54 Figure 3.11 I/O pin assignment of food adulteration identification IC unit Figure 3.11 shows the possible combination of I/O pins for DVM algorithm in the adulteration identification unit, which is helpful to apply the input image bits via input pin and receives the output image bits via output pin. Hence the I/O pins are declared for VLSI implementation purpose for image bits transformation. For interfacing and VLSI implementation purpose, I/O pins declaration is necessary.

14 55 Figure 3.12 Placement of I/O pins of food adulteration identification IC unit Figure 3.12 shows the representation of the I/O pins assignment, which is helpful for identifying the location of the I/O pins and the register. Placement of I/O pins is helpful for verifying adulteration identification components. In some approaches, the floor plan may be a partition of the whole chip area into axis aligned rectangles to be occupied by IC blocks. This partition is subject to various constraints and requirements of optimization: block area, aspect ratios, estimated total measure of interconnects etc.

15 56 Figure 3.13 Floor planning of food adulteration identification IC unit Figure 3.13 shows the floor planning arrangement of the adulteration identification unit components for optimizing the area. For floor planning the netlist describing circuit blocks, the logic cells within the blocks and their connections are noted initially. Floor planning is a mapping between the logical description and physical description. In floor planning the sizes of blocks are estimated and the initial relative locations of various blocks are set. At the same time the space for clock, input, output and power is also allocated. Highly connected blocks are kept physically close to each other. Floor planning allows to estimate the interconnect delay by estimating inter connect length.

16 57 Figure 3.14 Routing of food adulteration Identification IC unit Figure 3.14 shows the routing which is helpful for connecting all the input and output block through wire. It is helpful for data exchange from one block to another. The communication between one block and the other is performed in the routing step. In addition, to correctly connect the nets, routers may also be expected to make sure the design meets timing, has no crosstalk problems, meets any metal density requirements, does not suffer from antenna effects, and so on. Global routing determines the location of all interconnects and minimizes the total interconnect area used.

17 58 Figure 3.15 Layout of food adulteration identification IC unit Figure 3.15 shows the layout of the food adulteration identification unit, represents the blocks and their interconnection view, which is helpful to analyze the area, speed and power of the unit. This is the earlier step for the implementation of any unit in VLSI. Cadence EDA software is helpful for the layout. Cadence EDA software is working on the platform of Redhat Linux operating systems. The entire VLSI implementation flow is displayed in the layout. This is the last step of software; the next step of this layout is FPGA or VLSI hardware implementation.

18 59 Figure 3.16 Power consumption report of food adulteration IC unit in Xilinx software Figure 3.16 shows the power consumption report for adulteration identification IC unit milliwatts(mw) power is consumed by the unit under the ambient temperature of 25 degree celcious. The power report analysis is done in the tool of Xilinx ISE 6.1 Xpower software tool. Table 3.2 Power consumtion report of food adulteration identification IC unit S.No Particulares Voltage (V) Current (ma) Power (mw) 1 Quiecient V cc int Quiecient V cc out The power comsuption is based on the number of blocks available in the units. Table 3.2 lists the power consumtion.

19 60 Figure 3.17 Design summary of food adulteration IC unit in Xilinx software Figure 3.17 shows the design summary of food adulteration identification unit in Xilinx software. It gives the number of Look Up Tables (LUTs) and number of gates used for the design. Table 3.3 Design summary of food adulteration identification IC unit S.No Particulars Available Used Utilization 1 Number of 4 input LUTs 7, % 2 Number of occupied slices 3, % 3 Number of bonded I/Os % 4 Number of Multi I/Os % 5 Number of Global clocks % Table 3.3 shows the device utilization. It is clear that the utilization is very less. This reduces the power and time consumption.

20 61 Figure 3.18 VLSI implementation of food adulteration detection unit FPGA based image comparison is fast in speed compared to traditional software based approach. Figure 3.18 shows FPGA implementation of food adulteration detection units. The basic Virtex-4 building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. Virtex-4 devices are produced on a state-of-the-art 90-nm copper process, using 300 mm (12 inch) wafer technology. Combining a wide variety of flexible features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC technology. Table 3.4 represents the image comparison speed with different platforms.

21 62 Table 3.4 Processing speed of food adulteration detection unit in different platforms S.No Platform Image Comparison Speed (ns) 1 C 25 2 Matlab 16 3 VHDL with FPGA Implementation (Proposed System) 05 Image comparison speed in different platforms is tabulated in Table 3.4. It is clear that the proposed system is faster than the other techniques. 3.5 CONCLUSION It is important to create awareness among people about adulteration. Even though people are aware of adulteration, they cannot avoid it and cannot make themselves safe, as there are no user-friendly techniques to find out adulteration. But the proposed VLSIbased method is an easy and time-saving process to find out adulteration. The government can use it at the final stage of every product and avoid adulteration in food materials. Thus the public health is preserved better. Though some identification methods are presented previously, they consume more time. But this hardware implementation method is approximately three times faster than the existing methods. This system is based on digital image processing technique, so it can replace the analog sensors and makes the process very easy for the user. VLSI implementation is helpful for faster way of identifying the adulteration. Even though comparison algorithms are successful at software level, better results can be achieved by implementing them in VLSI-based hardware.