EMC Simulation Signal Integrity Simulation in Automotive Design

Transcription

1 Bitte decken Sie die schraffierte Fläche mit einem Bild ab. Please cover the shaded area with a picture. (24,4 x 11,0 cm) EMC Simulation Signal Integrity Simulation in Automotive Design Stefanie Schatt / EMC Validation Engineering / Simulation QL CBS2 Qualification Laboratory Regensburg

2 EMC Simulation Capabilities EMC Simulation during Development IC / Component Schematic / PCB ECU System Level Analog simulation Analog simulation 3D simulation PCB Signal integrity 3D simulation PCB Housing 3D simulation PCB Housing Cable harness Development Process Innovation and Roadmap Quotation Concept Refinement Development Product Validation Series Production 2

3 Agenda Agenda Introduction: High speed design in automotive components? IBIS - files Layer Stack Prelayout simulations Postlayout simulation Corner simulations, second/third source SI results Example for complex SI simulation Outlook Ibis 6.0 and future developments 3

4 High speed design in automotive components 4

5 IBIS files text file; contains parameters, static and dynamic curves describing the electrical behaviour of the digital I/O used for fast extraction of basic parameters (tr/tf, output impedance) common model for signal integrity simulations model quality: there is a wide range... IBIS File Stimulus Rising Waveforms Pullup Power Clamp Package package Falling Waveforms Pulldown Gnd Clamp Ccomp 5

6 layer stack signal signal signal GND plane PWR signal signal GND plane signal PWR / signal GND plane signal define: dielectric thickness signal, power, gnd planes trace width & distance get: defined impedances (same on all sig layers) low crosscoupling (xtalk) between traces on same layers AND between layers good for SI and EMC 6

7 Prelayout simulations Define trace topology Define/optimize terminations Choose optimal driver strength 7

8 Prelayout simulations - Example 8

9 Postlayout simulation Import PCB 9

10 PCB: layer stack definition Define layer stack as finally manufactured Values below are fictitious values 10

11 Example: SI simulation of DDR3 interfaces FPGA CONFIDENTIAL CONFIDENTIAL DDR3 DDR3 11

12 PCB: Selection of signals Select signals, define stimuli, chose drivers, simulate, create eye diagrams,. CONFIDENTIAL 12

13 Postlayout simulations Which interfaces should get simulated? Which signals should be simulated for which interface (DDR3 interface has clock, addresses, data, controls, )? What about second/third source supplier for your ICs? Very important for automotive design: corner simulations (TYP/FAST/SLOW): Wide variation from -40 C to 135 C IBIS TYP/FAST/SLOW refers to: Process Voltage Temp IBIS typ typ nom RT IBIS fast fast max min IBIS slow slow min max 13

14 Evaluation of results DDR interface Waveform FAST Over-/Undershoot criteria EMC compatibility... SLOW 14

15 Example complex SI simulation: SPI bus PCB1 (PCBS) Connector (MWS) PCB2 (PCBS) 15

16 Robust product 16

17 Summary and Outlook Many automotive components contain high speed interfaces Summary Signal integrity simulation vital for functionality over temperature Also EMC behaviour can be improved or optimized early in the design cycle IBIS version 6.0, IBIS-ISS,... Outlook User friendliness of SI-workflow: templates for simulations, results,... 17

18 Thank you for your Attention Stefanie Schatt EMC Validation Engineering / Simulation QL CBS 2 Qualification Laboratory Regensburg 18