Dissertation. Michael Lee Schuette, M.S. Graduate Program in Electrical and Computer Engineering. The Ohio State University. Dissertation Committee:

Transcription

1 Advanced Processing for Scaled Depletion and Enhancement Mode AlGaN/GaN HEMTs Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Michael Lee Schuette, M.S. Graduate Program in Electrical and Computer Engineering The Ohio State University 2010 Dissertation Committee: Wu Lu, Advisor Steven Ringel Siddarth Rajan

2 Copyright by Michael Lee Schuette 2010

3 ABSTRACT Demands for high-frequency signal amplification have been addressed over the past decades with high electron mobility transistors (HEMTs) based on III-V semiconductors such as GaAs, which can operate in mm-wave frequency bands ( GHz). The high dielectric breakdown strength, saturated electron velocity, and carrier mobility in AlGaN/GaN two-dimensional electron gas (2DEG) provides a platform for higher output power density for amplification over a similar frequency range compared to more mature material systems such as GaAs. Nitride semiconductors present unique challenges to the device designer in terms of their strong polarization fields and sensitivity of 2DEG to fluctuations in surface potential and chemistry. Aggressive geometry scaling is required in order to extend the frequency response of GaN-based HEMTs into the mm-wave regime, and short-channel effects (SCEs) thus far have resulted in diminishing returns as gate lengths (l g s) are reduced below 300 nm. As for other semiconductor materials, successful field-effect transistor scaling requires that not only l g be reduced for low gate capacitance, but that channel aspect ratio defined as l g /d, where d is the gate-channel distance, remain large. Satisfying this requirement enables vanishingly short gates to retain strong channel modulation efficiency. In order to exploit the fast frequency response of the scaled intrinsic device we must also maintain low parasitic impedances through which the device is accessed. ii

4 n + -GaN-capped HEMT structures are used in this work to exploit surface potential screening of the cap layer and its expected advantage in terms of DC-RF current dispersion. To overcome processing challenges associated with aggressive scaling of GaN-based HEMTs we have developed technology enabling us to construct gates shorter than 30 nm and to precisely remove GaN and AlGaN from the gate area of (GaN/)AlGaN/GaN HEMTs to reduce d. The optical transparency of GaN has made consistent sub-100-nm gate definition challenging for electron beam lithography tools that employ optical height detection, and our transparent substrate electron beam focusing strategy eliminates such difficulty. Recessed gate GaN-based HEMTs have historically been plagued with high gate leakage and DC-RF current dispersion due to ion damage incurred during recess etching, but the N 2 /Cl 2 /O 2 inductively-coupled plasma etch process described herein can provide very high GaN over AlGaN etch selectivity and does not require energetic ion bombardment. We verify this process using diodes on GaN/AlGaN/GaN and show that leakage currents are reduced by Schottky recessing when compared to non-recessed diodes, suggesting a low damage process. We begin HEMT fabrication work by comparing two AlGaN/GaN epitaxial structures in terms of channel confinement and surface trapping effects by preparing and testing 220 nm baseline devices on said structures. Record sub-threshold characteristics for submicron GaN HEMTs including sub-v T slope of 67 mv/dec and on/off drain current ratio greater than are achieved, suggesting good potential scalability of HEMTs on this structure which employs acceptor compensation doping in the buffer layer. Next we demonstrate first generation GaN/AlGaN/GaN HEMTs iii

5 with dielectrically-defined recessed 260 and 125 nm gates that exhibit reasonable DC performance, but low f t l g product of 10 GHz-µm due primarily to large fringing capacitance associated with long gate caps and high (0.87 Ω-mm) contact resistance. Electric field plating in these devices enables good X-band power performance e.g. 4.8 W/mm output power with PAE of 51%. Finally, we present systematic scaling of GaN/AlGaN/GaN HEMTs with process improvements such as recessed ohmic contacts providing uniform contact resistance below 0.5 Ω-mm. Variations of the gate recess process are used for controlled ( 1 nm/min) etching through the GaN cap and into the AlGaN barrier to fabricate HEMTs with dielectrically-defined gate lengths ranging from 29 to 1680 nm with barrier thicknesses of 29 (non recessed), 19, and 11 nm. We demonstrate enhancement-mode HEMTs with transconductance as high as 340 ms/mm and maximum drain current greater than 0.9 A/mm, as well as depletion-mode HEMTs with maximum drain current above 1 A/mm, small signal f t l g products exceeding 15 GHz-µm for l g down to 200 nm, and reasonable X-band output power of 3.3 W/mm with 46% PAE. With this we claim that by using our low-damage gate recess process we have effectively mitigated short channel effects into this l g regime. iv

6 ...to opportunity. v

7 ACKNOWLEDGMENTS Family: Thank you Mom for the confidence, and Dad for the loving discipline. You will always be my heroes. Thanks Brian for being the best brother in the universe. Professor Lu: Your wisdom, discipline, and friendship have guided and inspired me through the rocky road of graduate school. I ve been happy to reach for the high bar of excellence you set every day, and I ve been proud to call you advisor. Hyeongnam: You are insightful, meticulous, and selfless. Thanks in part to your help I ve embraced the art of HEMT fabrication and analysis. Thank you for your friendship. I thank the rest of my classmates at Ohio State from yesterday and today especially Dongmin, Jaesun, Xuejin, Hyun Chul, and Venky. It s been a pleasure working with and learning from all of you. Thanks to the dedication and skill of Mr. Jim Jones I ve had a functional and well-equipped processing lab in which to conduct much of my research. I wish you great joy in the future. Finally, I acknowledge the expertise and generosity of e-beam engineer Ms. Aimee Bross, and I thank Professors Ringel and Rajan for serving on my doctoral examination committee. vi

8 VITA May 1, Born - Delaware, Ohio May, B.S. Electrical & Computer Engineering, Ohio Northern University, Ada, Ohio , Graduate Teaching Associate, The Ohio State University, Columbus, Ohio National Science Foundation GK-12 Fellow, The Ohio State University, Columbus, Ohio August, M.S. Electrical & Computer Engineering, The Ohio State University, Columbus, Ohio Graduate Research Associate, The Ohio State University, Columbus, Ohio March, present R&D Device Engineer, TriQuint Semiconductor, Inc., Richardson, Texas PUBLICATIONS Journal articles M. L. Schuette and W. Lu. A simple technique for beam focusing in electron beam lithography on optically transparent substrates. Journal of Vacuum Science & Technology B, vol. 27, pp , M. L. Schuette and W. Lu. Highly selective zero-bias plasma etching of GaN over AlGaN. Journal of Vacuum Science & Technology B, vol. 25, pp , M. L. Schuette and W. Lu. Electrical transport in the copper germanide-n-gan system: experiment and numerical model. Journal of Applied Physics, vol. 101, pp , vii

9 M. L. Schuette and W. Lu. Compositional study of copper-germanium ohmic contact to n-gan. Journal of Electronic Materials, vol. 36, pp , H. Kim, M. L. Schuette, J. Lee, W. Lu, and J. C. Mabon. Passivation of surface and interface states in AlGaN/GaN HEMT structures by annealing. Journal of Electronic Materials, vol. 36, pp , H. Kim, M. L. Schuette, H. Jung, J. Song, J. Lee, and W. Lu Passivation effects in Ni/AlGaN/GaN Schottky diodes by annealing. Applied Physics Letters, vol. 89, pp , M. L. Schuette and W. Lu. Copper germanide ohmic contact on n-type gallium nitride using silicon tetrachloride plasma. Journal of Vacuum Science & Technology B, vol. 23, pp , J. Lee, D. Liu, H. Kim, M. Schuette, W. Lu, J. Flynn, and G. Brandes. Fabrication of self-aligned T-gate AlGaN/GaN high electron mobility transistors. International Journal of High Speed Electronics and Systems, vol. 14, pp , J. Lee, D. Liu, H. Kim, M. Schuette, W. Lu, J. Flynn, and G. Brandes. Self-aligned AlGaN/GaN high electron mobility transistors. Electronics Letters, vol. 40, pp , Conference contributions M. H. Wong, D. F. Brown, J. S. Speck. U. K. Mishra, M. L. Schuette, H. Kim, V. Balasubramanian, and W. Lu. X-band power performance of MBE-grown N-face GaN MIS-HEMTs. 37th International Symposium on Compound Semiconductors in Kagawa, Japan (May 31 - June ). M. L. Schuette, H. Kim, J. Song, and W. Lu. Near-ideal sub-threshold characteristics of AlGaN/GaN HEMTs. 12th International Symposium on Microwave and Optical Technology in New Delhi, India (December ). M. L. Schuette and W. Lu. A simple technique for beam focusing in electron beam lithography on optically transparent substrates. 53rd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication in Marco Island, Florida (May 26-29, 2009). viii

10 M. L. Schuette and W. Lu. Zero-bias N2/Cl2/O2 selective dry etching of GaN over AlGaN for HEMT gate recessing. 7th International Conference of Nitride Semiconductors in Las Vegas, Nevada (September 16-21, 2007). M. L. Schuette and W. Lu. Investigation of a low-temperature Cu3Ge ohmic contact to n-gan. 48th Electronic Materials Conference in University Park, Pennsylvania (June 28-30, 2006). H. Kim, M. L. Schuette, H. Jung, J. Song, J. Lee, W. Lu, and J. Mabon. EBIC and XPS study of post-annealing process on AlGaN/GaN Schottky diodes. 48th Electronic Materials Conference in University Park, Pennsylvania (June 28-30, 2006). (invited) M. L. Schuette and W. Lu. RIE-enhanced low-temperature copper germanide ohmic contact to n-gan and AlGaN/GaN heterostructures. 531st International Conference on Micro- and Nano-Engineering in Vienna, Austria (September 19-22, 2005). M. L. Schuette and W. Lu. Copper germanide Ohmic contact on n-type gallium nitride using silicon tetrachloride plasma. 49th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication in Orlando, Florida (May 31 June 3, 2005). M. L. Schuette and W. Lu. Copper germanide Ohmic contact on n-type gallium nitride using silicon tetrachloride plasma. 49th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication in Orlando, Florida (May 31 June 3, 2005). S. Ezekiel and M. Schuette. Magnetic resonance image segmentation technique by using Hurst coefficients. 2nd IASTED International Conference on Visualization, Imaging, and Image Processing in Benalmadena, Malaga, Spain (Sept. 9-12, 2002). FIELDS OF STUDY Major Field: Electrical and Computer Engineering ix

11 TABLE OF CONTENTS Page Abstract Dedication Acknowledgments Vita List of Tables ii v vi vii xiii List of Figures xiv Chapters: 1. Introduction Radio frequency power electronics The high electron mobility transistor Gallium nitride HEMTs Technological challenges for GaN HEMTs Crystal growth Current collapse Access resistance Scaling Short channel effects Cap layers and gate recess Goals and organization x

12 2. The sub-50 nm T-gate Background Transparent substrate focusing strategy (TSF) HEMT gate formation Free-standing gates Dielectrically-defined gates Gate recessing Etching of GaN-based semiconductors Techniques Challenges and prior art Gate recess development Preliminary etch tests Etching mechanism Electrical & chemical characterization SiO x patterning GaN-based high electron mobility transistors HEMT layers Device processing Baseline HEMTs - sub-v T analysis DC analysis D it estimation SIMS Dynamic I-V Small signal frequency response Recessed-gate HEMTs: 1st generation DC analysis Small signal frequency response Dynamic I-V RF power measurements Systematically scaled recessed-gate HEMTs: 2nd generation General process updates Recessed ohmic contacts Recess design and implementation DC analysis Small signal frequency response scaling RF power measurements xi

13 5. Conclusion and future vision Appendices: A. Basic HEMT process traveler A.1 Process overview A.1.1 Mesa isolation A.1.2 Fiducial A.1.3 Ohmic A.1.4 Gate A.2 Wet processing and photolithography A.2.1 Standard degrease A.2.2 Aggressive degrease (unsafe for ohmic, avoid water) A.2.3 Edge bead removal A.2.4 Shipley 1811 positive photolithography A.2.5 AZ5214 image reversal photolithography A.2.6 SiO x wet etch A.3 Plasma etching recipes for Oxford Plasmalab System100 ICP A.4 Metallization and liftoff A.4.1 General metallization in CHA evaporator A.4.2 General metal lift off A.4.3 Gate lift off A.5 Electron beam lithography A.5.1 ZEP520A (1000 Å) processing A.5.2 PMMA950k/PMMA-MAA/PMMA50k (1000/5000/1000 Å) processing A.5.3 Espacer processing A.5.4 E-beam HEMT direct-write command file B. Characterization methods B.1 DC I-V B.2 Capacitance-voltage B.3 Pulsed I-V B.4 Small signal S-parameter B.5 Load pull Bibliography xii

14 LIST OF TABLES Table Page 1.1 Material properties relevant to high frequency power performance of solid-state devices, including Johnson s figure of merit normalized to that of Si, for a selection of semiconductors Summary of f t l g for devices of similar gate length across three groups fabricated and analyzed in this work. With appropriate channel aspect ratio scaling we have fabricated 200 nm GaN HEMTs with f t l g greater than 15 GHz-µm A.1 Fiducial metal A.2 Ohmic metal A.3 Gate metal A.4 Plasma recipes xiii

15 LIST OF FIGURES Figure Page 1.1 Cross-sectional representation of a traditional high electron mobility transistor with lumped-element circuit model valid in the saturation region of operation, along with conduction band energy diagram. The barrier layer contains donors at an ionization energy level E d Drain current versus drain-source voltage for a series of gate biases, for an n-channel depletion-mode FET. The quiescent bias point for ac operation is (I d0, V ds0 ), I d1 is maximum drain current defined at the knee voltage V k for the gate forward biased maximally, and V b is the breakdown voltage Polarization effects in the strained Ga-face AlGaN/GaN HEMT. (a) Cross section of layer structure, (b) conduction band diagram, and (c) resulting charge distribution Drain-induced barrier lowering in HEMTs. (a) Device biased below threshold where the channel conduction band edge is horizontally symmetric, and the channel is fully depleted. (b) Device with same V gs but positive V ds the drain bias has reduced the potential barrier induced by the gate, and electrons can overcome this lowered barrier Short channel effect in AlGaN/GaN HEMTs in terms of electric flux lines. (a) Long gate can easily control channel. (b) Short gate approaches point source and looses control of channel. (c) Increasing gate aspect ratio by recessing restores modulation efficiency Conduction band energy and charge profiles for non-capped (a) and n + - GaN-capped (b) AlGaN/GaN HEMTs calculated using one-dimensional Poisson and Schroedinger equations. The cap layer reduces n s, but can screen surface potential variations from the channel xiv

16 2.1 (a) Free-standing T-gate formed by tri-layer e-beam resist, and (b) dielectrically-defined T-gate formed by dielectric trunk definition and bilayer e-beam resist Pores and gratings in ZEP520A on ITO (a-e, k-o) focusing at estimated substrate heights as noted in Figure 2.4 and (f-k, p-t) focusing at height of center cell. The first value is the estimated substrate height and the second is the focusing height, both in µm. For pores, average diameter and pitch are 18 nm and 59 nm. For gratings, average line width is 37 nm and pitch varies from 300 to 100 nm Gratings of 300, 200, and 100 nm pitch in ZEP520A on 4 inch quartz wafer. Average line width is 60 nm Measured data from metal edge bead and fitted plane for (a) 1 inch square ITO/quartz slide and (b) 4 inch quartz wafer. Line intersections indicate layout cell positions and arrows overlie the exposed rows of cells. Height was measured away from the edge of the 4 inch wafer to enable a square data pattern, although this is not required Average (lines + symbols) and maximum (symbols) error between height planes calculated using reduced numbers of measurement points Ĥ n relative to planes calculated using 24 points Ĥ 24 for (a) 1 inch square slide and (b) 4 inch wafer. Error bars show ± one standard deviation over 49 and 81 mesh points for 1 inch and 4 inch substrates Most aggressive gratings in ZEP520A on (a) Si, using automatic height compensation and (b) ITO/glass using our height estimation technique. Line width and pitch are 36 and 100 nm (a) Bilayer and (b) trilayer e-beam T-gate processes, using multiple resist sensitivities (S). 1) Exposure and development, 2) metallization, and 3) liftoff Exposure dose test summary for free-standing T-gates. (a) Trunk length dependence on trunk dose for fixed cap dose, and (b) representative gate profiles for 10 nm writing xv

17 2.9 Exposure dose test summary for free-standing T-gates. (a) Trunk and cap length dependence on cap dose for several trunk doses, and (b) representative gate profiles for 10 nm writing Process flow for dielectric T-gate construction. 1) Oxide etching through e-beam-defined ZEP520A mask, 2) Schottky metal deposition through e-beam-defined PMMA950k/PMMA-MAA/PMMA50k mask, 3) liftoff Exposure dose test summaries for 100 nm ZEP520A. (a) Preliminary 10, 25, and 75 nm-written isolated metal lines on Si substrate, and (b) SiO x etched lines defined in layout with various lengths and exposed at optimized dosing SEM image of a 68 nm SiO x -defined T-gate constructed using the process described in this Section Schematic diagram of an ICP-RIE reactor. Key components include the RF-powered table and independently-rf-powered coil Dependence of (a) Cl 2 and (b) O 2 fraction on GaN and Al 0.4 Ga 0.6 N etch rates and selectivity at a source power of 3 kw and a pressure of 10 mtorr. The 50% Cl 2 data were collected at 3% O 2, 3 mtorr, and 2 kw. The etch depth for the circled points is below the AFM detection limit so we include arrows indicating expected selectivity trends. (c) AFM step surface profiles for GaN and Al 0.4 Ga 0.6 N etched for 30 min using the recipe of the circled point in (b). This data is the average over 256 adjacent acquisition lines (a-c) AFM images of an HVPE GaN surface before plasma etching, after etching for 30 min in a Cl 2 -rich plasma, and after etching for 30 min in a N 2 -rich plasma. The 1 µm 2 R q more than triples after etching in the Cl 2 -rich plasma, and decreases after etching in the N 2 - rich plasma. (d) and (e) are images of the HEMT layer surface before and after etching for 3.5 min using the N 2 -rich recipe noted in Figure 3.4. The etch depth in (e) is 11 nm and the 1 µm 2 roughness was decreased by 50% after etching. All samples had been submerged in BHF for 90 s for SiO 2 mask stripping Etching trend for the n + -GaN/Al 0.3 Ga 0.6 N/GaN HEMT structure represented in the inset. The etch stops abruptly after clearing the n + - GaN cap layer. The lines are a guide for the eye xvi

18 3.5 (a) I-V characteristics for diodes that were recess-etched 0, 6, and 18 min,(b) reverse breakdown characteristics for non-recessed and 6-min recessed diodes, and (c) C-V -extracted n s and pinch off voltage versus recessing plasma exposure duration. The inset in (a) shows a plan view of the Schottky diode topology C-V -extracted electron profiles for non-recessed and 4 minute recessed Schottky diodes on AlGaN/GaN with 10 nm n + -GaN cap layer. The data points closest to the surface for each curve correspond to a DC bias of +3 V (a) X-ray photoemission spectra acquired from Al 0.4 Ga 0.6 N etched by N 2 /Cl 2 /O 2 ICP for varying durations. The binding energy scales have been corrected for charging effects (Trends in SiO x etch rate and selectivity over ZEP-520A with respect to (a) oxygen mole fraction and (b) chamber pressure for -200 V CHF 3 - based reactive ion etching SEM images of 300 nm PECVD SiO x films etched using CHF 3 /O 2 = 100/2.5 sccm RIE. We refer to the recipes by the letter appearing in the top left of each image. In each case the resist line width determined by metal liftoff was 100 nm, except for B 20, where the resist line width was 40 nm. The plot at right shows the normalized dependence of SiO x etch depth versus line width using recipe B, where a dependence is observed for sub-100 nm lines (SEM image of HVPE GaN etched for 20 min by N 2 /Cl 2 /O 2 ICP through a 100-nm-wide window in 100-nm-thick SiO x. The GaN etch depth is 24 nm and no SiO x is etched HEMT layer structures used in this work. Wafers A and C are from consecutive growth runs, and wafers B and D are from consecutive growth runs. All wafers have a barrier consisting of 23 nm Al 0.3 Ga 0.7 N and 1 nm AlN, as well as graded buffer Fe compensation doping xvii

19 4.2 Processing flow for recessed-gate GaN-based HEMTs: 1. Mesa isolation, 2. ohmic recessing, 3. ohmic deposition and anneal, 4. PECVD oxide deposit, 5. overlay oxide etch, 6. overlay metal, 7. gate footprint oxide etch, 8. gate recess, 9. anneal, 10. T-gate formation, and 11. optional oxide strip. Circled steps are specific to recessed-gate devices, and are not used for non-recessed devices (a) Transfer curves for 0.22 µm T-Gate GaN HEMTs built on wafers A and B, measured at V ds = 5 V (symbols) and 10 V (solid lines) where gate current is shown for V ds = 5 V and source-drain separation is 3.5 µm. (b) Subthreshold buffer and drain-gate current vs. total subthreshold drain current for all devices measured from each wafer. The lines are linear fits to the experimental data for wafer A Biasing schemes and symbol definition for off-state drain current analysis V V ds subthreshold swing with respect to gate to source and drain leakage at V gds = -5 V. Data are sorted by drain-source separation, and the two lines are log-linear fits to data from wafers A and B D-SIMS profiles for Al27 and Fe56 masses in wafers A and B Analysis of surface trapping effects on sub-v T for wafer A. (a,b) Pulsed I d -V d, and (c,d) DC transfer curves, before and after Si 3 N 4 passivation Pad de-embedded current gain ( h 21 ), maximum unilateral power gain ( MUG ), and stability factor (K) for 220 nm HEMTs on wafer A with 24 nm (AlGaN + AlN) barrier SEM images of first generation wafer D devices after gate recessing for (a,b) 260 nm, and (c) 125 nm recessed lines. GaN is etched by a nominal 10 nm. The scale lines are of length 2 µm for (a), and 500 nm for (b) and (c) (a,c) I d -V ds and (b,d) transfer curves for recessed-gate HEMTs for 260 and 125 nm devices. The insets in (b) and (d) are I d -V gs on a semilog scale using the same units as the primary plot xviii

20 4.11 Pad de-embedded current gain ( h 21 ), maximum unilateral power gain ( MUG ), and stability factor (K) for typical 125 and 260 nm recessedgate HEMTs on wafer D. f t and f max values are indicated along the f axis, where f max for both l g s is 62 GHz Dynamic I d -V ds for typical (a) 125 and (b) 260 nm recessed devices. The quiescent bias point QB0 corresponds to (V gs, V ds ) = (0, 0) V for both channel lengths, and QB2 is defined as (V gs, V ds ) = (-5, 7) V and (-4, 7) V for 125 and 260 nm devices, respectively. The pulse width and duty cycle is 0.2 µs and 0.01% X-band power performance of a recessed 125 nm channel device on wafer D. At V ds = 28 V we achieve maximum PAE of 51% with associated output power and gain of 4.8 W/mm and 6.2 db Summary of n + -GaN/AlGaN/GaN recessed Mo/Al/Mo/Au ohmic development. (a) Etch process trends using two plasma biases and two deoxidation conditions. The circled recipe was used in (b), which shows dependencies of specific contact resistivity and contact resistance on AFM-measured recess depth. The inset of (b) shows annealing temperature dependence on R c for 12 nm-etched ohmics Modeled threshold voltage versus AlGaN barrier thickness for three Schottky barrier heights, selected such that the model coincides with three pinch off voltages measured from Schottky diodes etched for three durations. Barrier thickness for the data points is constant since fullyselective etching was used during the recesssing of these diodes. Depending on the extent of surface oxidation after removal of AlGaN during moderately-selective etching, we may expect the required barrier thickness for E-mode operation to be between 6 and 18 nm Example AFM step height measurement result after (gate recess and) field oxide etch. (a) Non-recessed, (b) 10.4 nm recessed, and (c) 18 nm recessed. Average step heights were calculated over three devices of each etch depth. Values have been corrected for actual semiconductor etching since the raw step height includes a 12.8 nm oxide and sidewall resist-related layer. The shoulder at the base of the etch trenches is a measurement artifact caused by the finite diameter of the AFM scanning tip, which limits lateral resolution xix

21 4.17 SEM images of scaled recessed GaN/AlGaN/GaN HEMT gates (a) before and (b-g) after field oxide etching by BOE. We see an undercut etch off of the device mesa where the AlGaN layer has been removed, due to etch isotropy and higher etch rate of GaN compared to AlGaN for the selective recess etch process. Measured gate lengths are (a-b) 829 nm, (c) 747 nm, (d) 377 nm, (e) 168 nm, (f) 68 nm, and (g) 29 nm DC data for 800 nm devices for 29, 19, and 11 nm barrier thicknesses. (a) Transfer curves and (b) Family I-V. In (b) V gs is stepped from 1 to -8 V for non recessed devices, 2 to -5 V for 19 nm barrier devices, and 2 to -1 V for 11 nm devices, all in steps of -1 V. The inset of (a) shows corresponding gate current for the V g sweep data in this figure, also normalized to device width Transfer characteristic for 1.6 µm enhancement mode device with 11 nm-thick recessed barrier Trends in DC parameters with respect to inverse gate length for 29, 19, and 11 nm barrier thicknesses. The lines are linear regression fits to the data. Neither increasing or decreasing trends are apparent for non-recessed devices in (a) and (c) so no linear fits are included for them Pad de-embedded current gain ( h 21 ), maximum unilateral power gain ( MUG ), and stability factor (K) for (average) 186 nm HEMTs on wafer C with 29, 19, and 11 nm barrier thicknesses Trends in unity current gain (f t ) (a,b) and power gain cutoff frequency (b) with respect to inverse gate length for 29, 19, and 11 nm barrier thicknesses. The lines in (b) are least-squares regression fits to the data, and the numbers next to each line are the slopes of the fits in GHz-µm. (c) shows trends in the rate of increase in f t and f max with respect to decreasing gate length Dependence on f t and total gate capacitance on the gap between the gate cap and the semiconductor barrier surface for two gate lengths, using the model shown in the inset. Capacitance and f t curves are normalized to the intrinsic gate capacitance, and to f t expected for d cap = 200 nm xx

22 4.24 Analysis of short channel effects in our scaled GaN HEMTs using a model based on that of Jessen et al. (a) Linear relationship between gate length, gate-channel distance, and frequency response. Also in (a) we show modeled fringing capacitance as a fraction of total gate capacitance for two values of effective electron velocity. (b) Dependence of f t l g product on l g /d over three barrier thicknesses, along with trend expected from Equation The horizontal dash-dot line is maximum expected f t l g and the vertical line indicates minimum aspect ratio needed for sucessful RF scaling for AlGaN/GaN HEMTs, according to our measurement and analysis X-band power performance of a recessed 19 nm barrier 260 nm channel device on wafer C. At V ds = 28 V we achieve maximum PAE of 46% with associated output power and gain of 3.3 W/mm and 9.2 db B.1 Pulsed I d -V ds biasing using quiescent bias points of (a) (V ds0, V gs0 ) = (0 V, 0 V) and (b) (V ds0, V gs0 ) =(> V knee, < V t ) B.2 Load pull test bench used in this work. Points labeled GPIB are monitored or controlled by software xxi

23 CHAPTER 1 INTRODUCTION 1.1 Radio frequency power electronics Commercial, defense, and aerospace demands for high-frequency and low-noise signal amplification have been addressed over the past decades with solutions involving metal semiconductor field effect transistors (MESFETs) based on III-V semiconductors. Unlike the ubiquitous Si metal oxide semiconductor field-effect transistor (MOS- FET), channel modulation in these devices is accomplished by biasing a Schottky gate rather than an insulated one. MESFETs offer speed advantages over MOSFETs when built on materials with high carrier mobilities and drift velocities such as GaAs, and clever device structures such as the high electron mobility transistor (HEMT) have enabled operation in mm-wave frequency bands ( GHz) [1]. Due to excellent material properties and the availability of heterostructures, gallium nitride (GaN) HEMT technology can enable significantly higher output power density when compared to other materials for amplification over a similar frequency range [2]. Once several key processing hurdles are overcome, the operating frequency of GaN HEMTs can be extended even further. 1

24 Figure 1.1: Cross-sectional representation of a traditional high electron mobility transistor with lumped-element circuit model valid in the saturation region of operation, along with conduction band energy diagram. The barrier layer contains donors at an ionization energy level E d. 1.2 The high electron mobility transistor Channel carriers in conventional MESFETs come from intentional doping in the channel layer. Increased transconductance in this type of device requires elevated channel doping levels at the expense of mobility. This trade-off does not apply to HEMTs, whose structure and conduction band energy diagram is shown in Figure 1.1 along with the small signal equivalent circuit model whose elements will be refered to throughout this dissertation. In the traditional case, a Schottky barrier layer (AlGaAs) doped with donor atoms (typically away from the surface and channel) is grown upon a smaller band gap (GaAs), nominally non-doped layer (known as the 2

25 buffer). Electrostatics dictates constant Fermi energy across the structure at equilibrium resulting in a potential well in the buffer near the growth interface. Electrons from ionized dopants in the barrier populate the potential well, forming a dense quasitwo-dimensional electron gas (2DEG) only Å thick that is spatially separated from the dopant atoms. HEMTs possess three key advantages over conventional MES- FETs: 1) The two-dimensional channel is located very close to the gate, improving gate-channel communication or transconductance, 2) ionized dopant impurity scattering is eliminated, enabling elevated electron mobility in the non-doped channel, and 3) channel carrier densities can be much higher. HEMT operation This Section provides an overview of high-power and -frequency limitations of n-channel depletion-mode (D-mode) HEMTs, much of which can be applied to any such FETs, and implies guidelines for device design. Refer to Figure 1.1 for context of many of the lumped circuit elements referred to herein. In Figure 1.2 a family of drain current versus drain-source voltage (I d -V ds ) curves is shown for a series of gate biases (V gs ). The top curve corresponds to the maximum forward V gs dictated by the device s Schottky gate turn-on voltage, and the bottom curve corresponds to below the pinch off voltage V p which we define as V gs that reduces I d to 1 ma per mm of gate width (W ). The maximum AC output power is restricted essentially by the area of the large triangle in Figure 1.2, specifically P max = I d1 (V b V k ) 8 (1.1) 3

26 I d I d1 V gs > 0 V gs = 0 V gs < 0 I d0 V gs < V p V k V ds0 V b V ds Figure 1.2: Drain current versus drain-source voltage for a series of gate biases, for an n-channel depletion-mode FET. The quiescent bias point for ac operation is (I d0, V ds0 ), I d1 is maximum drain current defined at the knee voltage V k for the gate forward biased maximally, and V b is the breakdown voltage. where V b and V k are the breakdown and knee voltages. Since V b is limited by breakdown field a material parameter increasing the output of power amplifiers (PAs) entails adding additional stages, or gain blocks, leading to complicated circuits requiring elaborate impedance matching networks and cooling systems. We can simplify PA development by building upon a material system with high dielectric breakdown strength. The wide band gap semiconductor gallium nitride (GaN) satisfies this requirement, and has additional material properties that make it attractive for high frequency applications as well. The intrinsic transconductance g m0 is a measure of how strongly the gate modulates the current flowing from source to drain and is defined as the derivative of drain 4

27 current with respect to gate-source voltage. Assuming electron velocity saturation, g m0 can be expressed in terms of the gate capacitance (C gs ) as [3] g m0 = I d = C gs V g τ = C gsv s l g (1.2) where τ is the time needed for an electron with saturated drift velocity v s to traverse the channel of length l g. The parasitic source resistance R s = R c + R sh cannot be modulated by V g, and therefore reduces the measured transconductance as g m = g m0 1 + R s g m0 (1.3), valid in the saturation region of operation where I d does not change with V ds. In this dissertation for simplicity g m will be used to represent the measured (extrinsic) transconductance unless otherwise stated. Key figures of merit for radio frequency (RF) FETs include the frequency at which the short circuit current gain falls to unity (f t ) and maximum frequency of oscillation (f max ) where power gain falls to unity, which can be approximated as f t = g m 2π (C gs ) = g m 2π ɛlgw d (1.4) where d is approximately the barrier thickness and ɛ the barrier dielectric constant, and f max = f t ( ) 1 2 Rg+Ri +R s 2 R ds + 2πf t R g C gd (1.5) where C gd is the gate-drain capacitance, R g, R i, R s, and R ds are the gate, gate charging, source, and output resistances. For a device to produce useful power gain 5

28 at high frequencies it must have high f t as well as minimal extrinsic impedances R g, R s, and C gd. 1.3 Gallium nitride HEMTs GaN and related semiconductor alloys (III-nitrides) possess material properties that have opened doors to new and better devices in recent years. By varying the composition of (aluminum, gallium, indium)-nitride alloys, a continuous and direct band gap ranging from 0.74 to 6.2 ev can be accessed. Such an energy-gap range allows fabrication of light emitters and detectors covering visible red through deep ultraviolet (UV) radiation. Optoelectronics is a key market for III-nitrides, with important applications including blue lasers for reading optical media [4, 5, 6], full color light-emitting diode (LED) displays, and solar-blind UV detectors for missile detection [7]. The second of two pivotal markets for GaN the topic of this dissertation is RF electronics. Material properties of importance to power performance at high frequencies for several semiconductors are summarized in Table 1.1 [8]. Over 40 years ago Johnson showed that the maximum rate at which electrical charges in a semiconductor can be energized is set by the product of the material s breakdown field (E b ) and saturation velocity, and Johnson s figure of merit JM = E b v s /2π is often used to compare power-frequency limits across materials. Wide band gap semiconductors 4H-SiC, GaN, and diamond have higher E b and v s when compared to Si and GaAs resulting in significantly higher JM s, making them potentially superior candidates for use in high power RF devices. 6

29 Si GaAs 4H-SiC GaN Diamond E g (ev) n i (cm 3 ) (bulk) µ n (cm 2 /Vs) (2DEG) 1900 v s (10 7 cm/s) E b (10 6 V/cm) Θ (W/cm K) JM = E bv s 2π Table 1.1: Material properties relevant to high frequency power performance of solidstate devices, including Johnson s figure of merit normalized to that of Si, for a selection of semiconductors. JM for diamond is very high but technological challenges have so far precluded its electronic device development. A key advantage of GaN over SiC is that of band gap engineering and our ability to form heterostructures for HEMT devices. Currently SiC can be used only to form MESFETs which are inferior to HEMTs as outlined in Section 1.2. GaN HEMT technology currently has the greatest technological potential for RF PAs due to these devices high power density, allowing smaller devices with higher impedance and easier impedance matching. Also, a wide band gap enables high temperature operation, loosening cooling requirements. Polarization In the case of GaN, a 2DEG can exist without intentional doping due to large internal polarization fields. When grown pseudomorphically in the wurtzite crystal structure, piezoelectric polarization fields in the AlGaN layer of an AlGaN/GaN HEMT are over five times larger when compared to AlGaAs/GaAs [9]. Spontaneous 7

30 polarization within wurtzite group-iii-nitride materials is also large [10], and the implications of these fields on the electrostatics of the Ga-face ([0001]) AlGaN/GaN HEMT are illustrated in Figure 1.3 [11, 12]. Although excellent and exciting work is being done for the development of N-face ([000 1]) GaN HEMTs [13, 14], we focus solely on the more mature [0001] growth orientation. Figure 1.3 (a) represents a cross-sectional view of an AlGaN/GaN heterostructure with Schottky gate metal on top. The spontaneous polarizations P sp for AlGaN and GaN are in the same direction since both materials are Ga-face in the case shown. When the AlGaN barrier very thin compared to the GaN buffer is grown at a thickness below that at which the ternary alloy relaxes, it is under tensile strain and the associated piezoelectric polarization P pz is in the same direction as P sp. The large electric field in the barrier layer can exceed 5 MV/cm, and due to this and the conduction band offset between AlGaN and GaN, electrons accumulate in the potential well at the interface as shown in Figure 1.3 (b). The most widely accepted explanation for the source of 2DEG electrons in an Al- GaN/GaN HEMT is donor-like surface states, as proposed by Ibbetson [15]. The argument is based on charge neutrality of the structure in the absence of externally applied electric fields. In Figure 1.3 (c) a likely charge distribution is plotted for the HEMT system, where the summed polarization charges (spontaneous plus piezoelectric) are shown to lie at the top and bottom surface of the AlGaN barrier forming a zero-sum ±σ p dipole. In order for the 2DEG to be confined at the AlGaN/GaN interface any charge in the GaN buffer must be negative, so the 2DEG electrons cannot come from thermally generated buffer electrons which would leave behind positive 8

31 c P sp P pz tensile strain p surf P sp 2DEG p F c z Figure 1.3: Polarization effects in the strained Ga-face AlGaN/GaN HEMT. (a) Cross section of layer structure, (b) conduction band diagram, and (c) resulting charge distribution. charge. In fact, the buffer layer should be highly insulating for a low-leakage (scalable) HEMT, and by assuming zero buffer charge we can say the 2DEG charge is equal and opposite in sign to a positive surface charge, or in other words, the 2DEG electrons come from ionized surface donor states. Consistent with this surface donor theory, the electron density in an AlGaN/GaN HEMT channel is sensitive to surface chemical and electrical properties, and performance implication of this will now be discussed. 1.4 Technological challenges for GaN HEMTs Despite great advantages of GaN for microwave power amplification, several obstacles must be overcome before its potential is realized. Successful commercialization and wide deployment of GaN electronics will require advances in device reliability and better understanding of failure mechanisms and ongoing work is being done in regards to ohmic and gate metal degradation [16], passivation layer reliability, and 9

32 other processing issues. In general, technological challenges for GaN-based HEMTs can be categorized as material growth-related and process-related, although there is much overlap between these two groups due to interdependencies Crystal growth As was the case for GaAs in its nascent days and despite the major progress that has been made, GaN crystal growth remains relatively immature. GaN HEMT films are grown by metallorganic chemical vapor deposition (MOCVD) [17] or molecular beam epitaxy (MBE) [18] on non-native substrates such as 4H-SiC, sapphire, or Si. The chief difficulty pertaining to bulk GaN growth and the availability of large area GaN substrate is the high melting temperature of GaN. Lattice mismatch between GaN and the foreign substrates on which it is grown can result in high densities of threading dislocations (compared to more mature material systems) which can be donor-like and cause local charge accumulations, resulting in degraded mobility, inadvertent buffer conductivity, and electron trapping [19, 20, 21] Current collapse Dependencies of operating frequency and bias stress on drain current levels commonly referred to as RF dispersion or current collapse, are usually attributed to electron trapping activity at the device surface [22, 23]. The effects of surface states were first measured by Vetury who used floating gates to monitor negative surface potential extending from the gate edge across the gate-drain access region toward the drain electrode [24], and later the virtual gate model was proposed [25]. It was explained that under large V gd electrons from the gate fill donor-like surface states in the gate-drain access region and act as an extended gate that in turn extends the 10

33 depletion region along the channel. This dispersion, which limits microwave power output of GaN HEMTs, can been mitigated by surface passivation with dielectrics such as Si 3 N 4, SiO 2, MgO, and Sc 2 O 3 [26, 27, 28, 29], and also with epitaxially-grown GaN cap layers. It seems that the passivant buries the surface donors preventing them from being filled by electrons emitted from the gate edge. Field plating has been shown to reduce current collapse by lessening electric field crowding on the drain side of the gate [30, 31] and we will show that this strategy can greatly improve RF power performance. An interesting observation is that surface passivation not only can reduce trapping effects that show up as current collapse, but it also can increase the number of carriers in the channel, which may be seen as conflicting with the surface donor theory. It can be said that current collapse is both a material problem and a processing problem as it is affected by both stages of device construction Access resistance For both DC and RF device operation it is the extrinsic behavior that we observe by direct measurement. In order to fully realize the performance potential of a device predicted by its material properties, we must eliminate extrinsic impedances through which the intrinsic device is accessed. Large access resistance increases a device s measured knee voltage which limits maximum voltage swing (Figure 1.2), transconductance, and consequently, frequency response. Without elaborate heterostructure design we cannot form thermionic ohmic contact (i.e. zero Schottky barrier) to AlGaN/GaN HEMTs due to the wide band gap of AlGaN, so instead people rely on what seem to be tunneling ohmic contacts. Also, depletion of the twodimensional electron gas (2DEG) channel by negative trapped charge at the device 11

34 surface leads to increased resistance in the access regions between the ohmic regions and the intrinsic area below the gate [25]. Contact resistance can be minimized by optimization of the thicknesses and annealing conditions of multi-layer metal stacks [32, 33, 34, 35, 36], and by effective surface doping using ion implantation [37] or plasma etching [38, 39, 40, 41]. Another method that has potential for reducing access resistances while simultaneously alleviating current collapse is epitaxial growth of a capping layers upon the AlGaN barrier Scaling To correctly shrink FET we must carefully scale internal electric fields in threedimensions. For example, Si MOSFET engineers have reduced l g aggressively while simultaneously reducing the (effective) gate dielectric thickness. To date for GaN HEMTs, we have yet to see f t continuously increase with a l 1 g dependence into quarter-micron regime as dictated by Equation 1.4 and this is due to various short channel effects. For GaN HEMTs the intrinsic device length is always longer than the lithographic device length because of surface charge trapping mostly on the drain side of the gate which acts as a gate extension, or virtual gate [25]. In addition, fringing electric fields are always present, and have been approximated by Eastman to extend the electrostatic effective gate length by twice the barrier thickness [17]. For long gates this effect is negligible but for a typical 25 nm AlGaN barrier device, the effective gate length can exceed 150% of the lithographic gate length for 0.1 µm devices. As discussed in this dissertation, bringing short gates vertically closer to the channel can help mitigate short channel effects. 12

35 1.5 Short channel effects Although excellent work has demonstrated AlGaN/GaN HEMTs with gate lengths around 50 nm, short channel effects (SCE) are usually evident in DC electrical data [42, 43]. As the gate length of a FET is decreased and no other scaling measures are taken, the device characteristics become increasingly less ideal. For successful scaling we must adjust device geometries to maintain validity of the gradual channel approximation (GCA), where the rate of variation in the lateral electrical field within the channel is much smaller than that of the vertical field. When l g becomes small such that the GCA is no longer applicable, the gate looses control of the channel and we see SCE such as drain-induced barrier lowering (DIBL) which manifests as a negative threshold voltage (V T ) shift and decreased output resistance, and can prevent the channel from being pinched-off entirely. DIBL is illustrated in Figure 1.4, where in (a) the channel is pinched off at V gs < V T at zero drain bias. In Figure 1.4 (b) the drain is biased positively, the channel potential barrier is lowered, and the current due to electrons overcoming this barrier increases with drain bias. SCE can be reduced by ensuring that channel carriers are well-confined to a two dimensional space and that electron distribution tailing below the channel is minimized, so that the gate potential may fully modulate the carriers this condition is better satisfied with a HEMT structure than for a conventional MESFET. Improved electron confinement in GaN HEMTs has been achieved using double-heterojunction structures involving back barriers such as AlGaN and InGaN [44, 45], and with buffer compensation doping as applied in our work (Section 4.3). SCE has been well-mitigated in GaAs- and InP-based HEMTs by decreasing the barrier thickness 13

36 simultaneously with gate length, and this is an approach taken in this work. Refer to Figure 1.5 for a qualitative illustration of SCE in terms of electric flux lines between two parallel plates of a capacitor formed by the gate and channel, and how the effects can be removed by gate recessing. Here, d is the gate to channel distance in the y direction, and we now define the channel aspect ratio as l g /d. Figure 1.5 (a) is a representation of a relatively long gate AlGaN/GaN HEMT with large l g /d biased at an operating point where V ds > 0 V and V gs < 0 V. For the long gate case, fringing capacitance, represented by flux lines extending outside the lithographic gate length l g, can be neglected and the effective gate length l g is approximately equal to l g. For the short gate case of (b) the gate electrode approaches a point source (in the x y plane), fringing capacitance dominates, and l g is much greater than the lithographic gate length. In this small aspect ratio case DIBL becomes more severe and V T can be quite negatively large. Sub-threshold drain current for small l g /d HEMTs can be excessive and sub-threshold swing, which quantifies the rate of I d change with V gs near V gs = V t, can be small. By reducing as grown barrier thickness, or by gate recessing as shown in Figure 1.5 (b), l g /d can be restored to a larger value and the FET behaves more ideally. Usually decreasing the barrier thickness at the growth step increases parasitic resistance in the access regions which is not desirable. 1.6 Cap layers and gate recess Careful epitaxial design provides the foundation of HEMT technology and GaN capping layers grown upon an AlGaN barrier can provide several benefits. Shen et. al showed that a thick unintentionally-doped (UID) GaN layer can reduce dispersion by screening surface traps and associated frequency dependent changes in 14

37 S V gs <V t G D S V gs <V t V ds >0 G D E c (a) E c e - DIBL (b) qv ds Figure 1.4: Drain-induced barrier lowering in HEMTs. (a) Device biased below threshold where the channel conduction band edge is horizontally symmetric, and the channel is fully depleted. (b) Device with same V gs but positive V ds the drain bias has reduced the potential barrier induced by the gate, and electrons can overcome this lowered barrier. surface potential from the 2DEG [46]. We calculated the conduction band energy and corresponding 2DEG carrier profiles for two device structures by solving the onedimensional Poisson and Schroedinger equations self-consistently [47], and the results are shown in Figure 1.6. (a) is for AlGaN/GaN, and (b) is for the structure in (a) with a 10 nm thick n + -GaN cap layer with cm 3 doping. To simulate the effects of surface potential fluctuations on the channel charge level we calculated for two surface barrier heights for each structure differing by 0.2 ev. For the non-capped HEMT the small surface potential variation modulated the 2DEG by 3.4%, whereas the cap layer screens the surface potential change resulting in no channel fluctuation. Arulkumaran et. al compared the effects of 3-nm-thick capping layers of various conductivity types and found that after gate recessing n + -GaN capped HEMTs showed 70% lower current dispersion when compared to a UID-GaN capped HEMTs [48]. Although reduced source resistance for an n + -GaN capped AlGaN/GaN HEMT was 15

38 g g g g g g g g g Figure 1.5: Short channel effect in AlGaN/GaN HEMTs in terms of electric flux lines. (a) Long gate can easily control channel. (b) Short gate approaches point source and looses control of channel. (c) Increasing gate aspect ratio by recessing restores modulation efficiency. 16

39 also shown earlier by Egawa et al. [49] this is not always the outcome and trade offs must be considered. Heavily-doped capping layers, or ohmic layers, have been used successfully in more-mature III-V FETs to reduce ohmic contact resistance by orders of magnitude [50], but in order to realize benefits from a capping layer with AlGaN/GaN HEMTs where polarization fields dominate, the layer(s) and processing must be carefully designed. The tensile strain within a GaN cap causes a piezoelectric polarization field pointing in the opposite direction to that of the AlGaN barrier (compressively strained), which analogously places negative charge at the upper GaN/AlGaN interface reducing the 2DEG density (n s ) at the lower AlGaN/GaN interface [51, 52]. A decaying exponential dependence of n s on GaN cap thickness has been reported [52], and this dictates that a GaN cap should be thin in order to not over-deplete the channel in the access regions (note the decrease in channel electrons due to the 10 nm cap in Figure 1.6 (b)). Especially for the n + -GaN case, the cap layer should be recessed under the gate to restore modulation efficiency and to prevent excess leakage current. In either case for depletion mode devices, a good gate recessing process should restore n s directly beneath the recessed region to near the non-capped level so that charge screening and/or contact resistance benefits can be enjoyed without sacrificing g m or increasing gate leakage. Enhancement mode When the thickness and Al concentration of the AlGaN barrier in an AlGaN/GaN HEMT are sufficient, (e.g.. 5 nm for 34% Al) [15], a 2DEG is induced at the heterointerface. If these conditions are not met, a 2DEG may be induced by a forward bias and this is the basis of the enhancement-mode (E-mode) AlGaN/GaN HEMT demonstrated by Khan [53]. E-mode GaN-based HEMTs are 17

40 E c -E F (ev) surface potential fluctuation channel modulation (a) AlGaN UID-GaN Distance (nm) n (10 19 cm -3 ) E c -E F (ev) surface potential fluctuation (b) reduced channel modulation -0.5 n + -GaN AlGaN UID-GaN Distance (nm) n (10 19 cm -3 ) Figure 1.6: Conduction band energy and charge profiles for non-capped (a) and n + - GaN-capped (b) AlGaN/GaN HEMTs calculated using one-dimensional Poisson and Schroedinger equations. The cap layer reduces n s, but can screen surface potential variations from the channel. attractive for use in high-temperature/radiation-hard logic, and for simplified highpower inverter circuits for use in applications such as hybrid automobiles [54]. To maintain low R s and R d we need low sheet resistance in the source and drain access regions which may not be possible if the barrier across the entire source-drain gap is too thin. A gate recess process can be used to thin the barrier below the gate to the point of 2DEG pinch off without increasing R s [55, 56]. Annealing of gate metal can also cause a device s threshold voltage to shift positively [57, 58]. Cai et al. demonstrated E-mode operation by using a fluorine-based plasma treatment followed by a high-temperature anneal [59, 60, 61, 62] and others have combined such F-based plasma with gate recessing [63] and gate dielectrics [64]. Combinations of ohmic capping layers, gate recessing, and gate dielectrics have shown promise for high current density, high transconductance E-mode devices and such strategies are employed in the this work. 18

41 1.7 Goals and organization Having described operational principals of AlGaN/GaN HEMTs and challenges associated with scaling these devices, we are positioned to expound upon work we have completed to improve the understanding of and solve problems associated with AlGaN/GaN HEMT scaling and mitigation of short channel effects in these devices. From this point, we proceed by narrating two key process developments: 1) an electron-beam focusing strategy which enables us to routinely fabricate microwave HEMT T-gates into the sub-50 nm regime with and without dielectric footprint definition (Chapter 2), and 2) a low-damage, robust (Al)GaN plasma etching strategy which we later use to scale the gate-channel distance (Chapter 3). In Chapter 4 we compare two AlGaN/GaN epitaxial structures in terms of channel confinement and surface trapping effects, both of which have strong scaling implications, through preparing and testing 220 nm baseline devices on said structures. Next we demonstrate recessed-gate HEMTs with two channel lengths using a dielectrically-defined gate process, which points us toward necessary process improvements. Finally, we present systematic channel aspect ratio scaling of n + -GaN/AlGaN/GaN HEMTs fabricated using an updated process involving recessed ohmic contacts, and conclude that we have in fact mitigated short channel effects in these devices using the advanced fabrication strategies established in Chapters 2 and 3. 19

42 CHAPTER 2 THE SUB-50 nm T-GATE 2.1 Background For millimeter-wave operation HEMTs require gates shorter than 150 nm [65] to achieve small gate capacitance and fast frequency response. Delineating sub-micron gates requires direct-write electron-beam lithography (EBL), wherein an electronsensitive resist film is exposed by a focused, magnetically-steered beam of electrons [66]. Achieving usable microwave power gain requires high f max, which, according to Equation 1.5, requires that the access resistance of the gate electrode R g be minimized. To this end, microwave HEMTs use a T- or mushroom- shaped gate cross section with a short trunk contacting the semiconductor and a more bulky cap to provide low gate resistance. In this work we use two varieties of T-gate, formed by methods described later and illustrated in Figure 2.1: a) free-standing, and b) dielectrically-defined. Early in our work we discovered special challenges associated with forming sub-100-nm e-beam features on GaN, which were mainly related to its optical transparency. This chapter describes the development of a reproducible strategy for nanolithography on transparent substrates such as GaN/SiC, which we use to 20

43 cap trunk (a) (b) dielectric Figure 2.1: (a) Free-standing T-gate formed by tri-layer e-beam resist, and (b) dielectrically-defined T-gate formed by dielectric trunk definition and bilayer e-beam resist. form microwave transistor T-gates that are a prerequisite for the aggressively scaled devices this work intends to realize. Optical transparency problem EBL resolution is limited by beam spot size. Non-uniformities in substrate height can be caused either by wafer tilt due to holder mounting errors or by non-planar wafer or stage surfaces. To minimize beam spot diameter it is necessary that the height of the wafer surface coincides with the height of the beam focal point, which can be satisfied either by adjustment of biasing to the objective lens coil in the electron optics or by stage movement. Such corrections also help to maintain constant writing field size and accurate field stitching regardless of substrate height variations. To ensure good focus, EBL tools are commonly equipped with laser height sensors or similar light-exploiting instrumentation which can measure the wafer height relative to a reference plane. Such equipment is useful only if the surface of the substrate to be exposed is reflective to the wavelength(s) used for height detection, which is usually not the case for optically transparent substrates such as GaN and SiC both used for high power and high frequency transistors requiring sub-micron gate definition. Additionally, sub-micron patterning of glass is needed to form micro/nano-fluidic channels 21

44 for biomedical applications such as drug and gene delivery devices and systems [67]. These materials optical transparency can result in inaccurate height measurements during EBL or prevent measurement entirely. When using automatic height compensation routines for beam focusing, inaccurate substrate height measurements cause defocused beams at local writing points on the wafer surface, making high-resolution patterning of transparent substrates difficult or impossible. Our approach Conductive and/or reflective metal/inorganic or polymer films can be applied below or above e-beam resist for the purpose of charge dissipation and/or reflectivity for height measurements [68, 69, 70]. Although conductive films can reduce pattern placement errors and reflective films can enable automatic height compensation at each writing location, such films can degrade EBL resolution via additional electron scattering and inadvertent chemical interaction with resist and developer. Applying metal over the substrate below resist for reflectivity is generally incompatible with processes where later removal of the film would damage the underlying surfaces and patterns, which is certainly the case for sensitive electronic devices such as GaN HEMTs. To overcome these problems we developed a reliable high resolution EBL patterning scheme for optically transparent substrates which does not require blanket reflective coatings that could degrade resolution. This transparent substrate focusing (TSF) strategy ensures electron beam focus for transparent substrates as well as when using automatic height measurements and focus corrections by built-in systems on opaque materials. 22

45 2.2 Transparent substrate focusing strategy (TSF) It is common practice in photolithography to remove thick resist from the wafer edge (edge bead) prior to pattern exposure. Our method is to measure height from several points around the perimeter of a wafer where metal has been deposited owing to an earlier edge bead removal step. This data (predictors) is then used to numerically estimate the height (responses) at any point across the substrate as follows [71]. After measuring height data (x 1, y 1, h 1 ), (x 2, y 2, h 2 ),..., (x n, y n, h n ) from only the wafer perimeter we estimate coefficients H in the system of equations, H = MB+ε (2.1a) where h 1 h 2 h n H =. 1 x 1 y 1 x 1 y 1 2 x 2 y 2 x 2 y 2 M =. n x n y n x n y n B = b 1 b 2 b 3 b 4 ε 1 ε 2 ε =. ε n (2.1b) (2.1c) (2.1d) (2.1e) while minimizing the sum of the errors squares n i=1 ε2 i. The x y interaction term in the linear model h i = b 1 + b 2 x i + b 3 y i + b 4 x i y i + ε i has a subtle effect on the resulting 23

46 plane. For our test substrates we define a layout of m cells, calculating an m-point height mesh Ĥ 24 = M 24 B based on the measured heights H of 24 perimeter cells. Before exposing a given layout cell the column is adjusted to focus at the appropriate pre-mapped height (from Ĥ 24 ), and no height measurement is attempted during the exposure step. We tested this technique on 100 nm-thick ZEP520A resist (ZEON Corp.) on 1 inch square quartz slides with thin indium-tin-oxide (ITO) charge-dissipation films, as well as on 4 inch diameter quartz wafers. Prior to resist coating we deposited 100 nm of Au by e-beam evaporation at the perimeter of the substrates. Area doses of 1430 and 820 µc/cm 2 were applied for arrays of pores defined in layout as 4-pixel 10 nm x 10 nm squares, and gratings defined as singlepixel (5 nm) width lines, respectively, using a Vistec EBPG-5000 Gaussian beam tool equipped with a dual-diode laser height sensor at 50 kev and 100 pa. After mounting the 1 inch substrate on the EBL holder we measured 3.4 µm of height change per mm of substrate surface. Tilting of 1-5 µm/mm is typical of what we observe when loading small substrates. For the 4 inch wafer we used shims to affect a tilt of 1.4 µm/mm. We wrote gratings and pore arrays at several locations across the substrates, setting the beam focus at the pre-mapped estimated heights, and for comparison, at the estimated height of the center cell, for each substrate. The patterns used were smaller than the 70 µm x 70 µm writing fields so no field stitching was needed, and the height variation across each cell 170 and 70 nm for the 1 inch slide and 4 inch wafer, respectively was low enough to be neglected. Pattern imaging was done with a Zeiss Ultra 55 Plus FE-SEM at 2 kv. 24

47 Verification Figure 2.2 shows arrays of pores and gratings written on a 1 inch glass/ito slide. The first and second numbers noted on each image correspond to the estimated substrate heights at the writing locations, and the beam focusing heights, respectively. For the top rows of images in Figure 2.2 (a-e and k-o), although the substrate height varied by as much as 41 µm, consistent pore diameters and line widths were achieved by focusing at the pre-mapped heights. With correct beam focusing, we defined pores of 18 nm diameter on a 59 nm pitch, as well as gratings of line width 37 nm on pitches of 300, 200, and 100 nm. Effects of beam defocusing are shown in the bottom rows of images (f-j and p-t), where the patterns were written while fixing the focusing height at the estimated value for the center cell, i.e. 36 µm. In this case poor pattern definition was observed away from the center position. As expected, pattern degradation due to defocusing was exacerbated for the more aggressive nano-pores, compared to the larger scale grating patterns. 10 µm of defocusing was sufficient to prevent opening of the sub-20 nm pores, as seen in Figure 2.2 (i). For the same defocusing distance the gratings were still opened with minimal resist scumming, as shown in Figure 1 (s). With this data we estimate our tool s effective depth of focus under these conditions as 5-10 µm. In Figure 2.3 we show gratings defined on the 4 inch quartz wafer. Due to the lack of a conducting ITO film on this wafer, we used a spin-on water based conducting polymer (Espacer, Showa Denko, Inc.) for charge dissipation during exposure, and sputtered Au for SEM imaging. We attribute the degraded resolution compared to that of the ITO/quartz slide to these films. The result, however, is consistent with that shown earlier, where line definition across the wafer is uniform when focusing at pre-mapped heights (Figure 2.3 a-i, n), 25

48 and degrades with incorrect height compensation (Figure 2.3 j-m, o-r). In this case gratings were absent for a defocus greater than 28 µm. The measured heights for both substrates along with fitted surface planes Ĥ 24, are shown in Figure 2.4 where for each plot, line intersections indicate layout cell positions and the arrow coincides with the exposed row of cells. Cell pitch was 3 and 10 mm for the 1 inch slide and 4 inch wafer, respectively. To estimate the minimum number of measured height points n required for an accurate plane fit, we use Ĥ 24 as an estimation of the real wafer plane. The average error between a reduced-predictor plane and the reference is calculated as (Ĥn Ĥ 24 ) 2 Ē n = m (2.2) where Ĥ n is the m-point mesh calculated using n predictors (and m is 49 and 81 for the 1 and 4 inch substrates). The trend in error versus number of predictors is shown in Figure 2.5, where we plot the mean and maximum height errors over all m substrate positions. In general, error decreases as the number of predictors is increased, but its maximum does not exceed 4 µm for either substrate even when using only four points. This analysis suggests that given the measurement error of our system a four-point height regression can provide sufficient focus correction for definition of the reported patterns. The resolution realized on transparent substrates using this technique is consistent with the best achieved on Si substrates where automatic height detection and focus adjustment is used during exposure. Figure 2.6 shows a comparison of the most aggressive gratings we can define on Si and ITO/quartz. On both substrates gratings 26

49 Figure 2.2: Pores and gratings in ZEP520A on ITO (a-e, k-o) focusing at estimated substrate heights as noted in Figure 2.4 and (f-k, p-t) focusing at height of center cell. The first value is the estimated substrate height and the second is the focusing height, both in µm. For pores, average diameter and pitch are 18 nm and 59 nm. For gratings, average line width is 37 nm and pitch varies from 300 to 100 nm. 27

50 Figure 2.3: Gratings of 300, 200, and 100 nm pitch in ZEP520A on 4 inch quartz wafer. Average line width is 60 nm. of 36 nm lines on 100 nm pitch are achieved, indicating that our focusing scheme for transparent substrates is as effective as automatic height measurement by the built-in system for opaque substrates. Our method can be used during transparent integrated circuit processes wherein deposition of metal at the wafer perimeter can be done simultaneously with other metallization steps preceding EBL, and the planefitting can be done across any wafer geometry. In this experiment we assumed planar substrates, but by using additional height measurement points near the wafer center, and including higher-order terms in Equation 2.1a, this technique can account for wafer bowing as well. 2.3 HEMT gate formation In this Section we present our development of free-standing and dielectricallydefined GaN HEMT T-gates into the sub-50-nm regime. Use of the TSF strategy was critical in this work. 28

51 Figure 2.4: Measured data from metal edge bead and fitted plane for (a) 1 inch square ITO/quartz slide and (b) 4 inch quartz wafer. Line intersections indicate layout cell positions and arrows overlie the exposed rows of cells. Height was measured away from the edge of the 4 inch wafer to enable a square data pattern, although this is not required. 29

52 Figure 2.5: Average (lines + symbols) and maximum (symbols) error between height planes calculated using reduced numbers of measurement points Ĥ n relative to planes calculated using 24 points Ĥ 24 for (a) 1 inch square slide and (b) 4 inch wafer. Error bars show ± one standard deviation over 49 and 81 mesh points for 1 inch and 4 inch substrates. Figure 2.6: Most aggressive gratings in ZEP520A on (a) Si, using automatic height compensation and (b) ITO/glass using our height estimation technique. Line width and pitch are 36 and 100 nm. 30

53 2.3.1 Free-standing gates T-gates for fast heterostructure devices can be formed by using multiple layers of e-beam resist with varying electron sensitivity. Todokoro first developed a process using a high-sensitivity layer atop a low-sensitivity layer, which, after exposure and development, provided sufficient undercut to allow liftoff of T-shaped gates as shown in Figure 2.7 (a) [72]. An improved strategy, whose process sequence is outlined in Figure 2.7 (b), uses a second low-sensitivity top layer for improved undercut and process latitude [73]. Formulations of poly-methyl methacrylate (PMMA) of various molecular weights are commonly used for the low-sensitivity layers, while the copolymer P(MMA-MAA) routinely serves as the high-sensitivity middle layer. Usually a single e-beam step is used for free-standing T-gates in trilayer resist, including a high-dose, narrow line exposure for the trunk and a lower dose, wider line exposure for the cap. Besides spot size, forward electron scattering through the top and middle layers also limits gate length, and sub-100-nm gates can be difficult to achieve. A two-step strategy has been used to overcome such limits where first the top two layers are exposed and developed, followed by a second exposure and development of the bottom layer. This strategy, although more labor-intensive and prone to captrunk misalignment, lessens the forward scattering problem and has been used in a high-resolution ZEP/PMGI/ZEP resist stack to achieve sub-50-nm gates [74]. In this work, controlled beam focus from TSF coupled with minimal forward scattering of 100 kev electrons in our EBPG-5000 exposure tool allows us to fabricate sub- 50-nm free-standing T-gates using a single exposure and development of a standard PMMA/copolymer/PMMA stack. 31

54 1) High S Low S Low S High S Improved undercut Low S metal 2) 3) (a) Bilayer (b) Trilayer Figure 2.7: (a) Bilayer and (b) trilayer e-beam T-gate processes, using multiple resist sensitivities (S). 1) Exposure and development, 2) metallization, and 3) liftoff. Exposure dose tests To ensure our gate process would be applicable to real GaN devices we conducted e-beam dose tests on templates having identical substrate materials and surface topology compared with HEMTs to later be fabricated. That is, we wanted to keep effects from substrate backscattering and resist thickness non-uniformities related to mesa and ohmic metal proximity constant from gate fabrication tests to real device fabrication. The resist scheme used was, from bottom to top, PMMA950k/PMMA- MAA/PMMA50k (100/4900/90 nm). In layout we defined two trunk lengths 10 nm and 25 nm. The beam current and accelerating voltage used for this e-beam process was 100 pa and 100 kv, and these beam parameters are used in all subsequent gaterelated e-beam work described in this document. Under these conditions theoretical 32

55 beam spot size is 3 nm for our tool, although this is smaller than that which the tool can measure due to limitations imposed by marker quality. For 10 nm-written lines we divided the total dose into two beam passes to take advantage of statistical nanometer-scale spot placement error in order to improve exposure uniformity along the line. The cap length was laid out as 250 nm. Following exposure, per the recipe in Appendix A, we developed patterns in a 1:3 methyl isobutyl ketone (MIBK) - IPA solution, and then deposited and lifted-off Ni/Au gate metal. Results of varying trunk and cap doses are summarized in Figures 2.8 and 2.9. The SEM images, taken of gates ends extending 1 µm past the mesa edge, are for exposure conditions 1-3 in the corresponding length vs. dose plots. Figure 2.8 shows that with 10 nm writing we can construct gates between 45 and 100 nm using these conditions, and that for 25 nm writing we can extend above 150 nm. Dose 1 is not sufficient to clear the PMMA950k for the slightly thicker resist off the mesa compared to on-mesa, resulting in a cantilever. Using dose 2 we see gate contact off the mesa with a length of 44 nm. The cap length is roughly independent of the trunk dose. Figure 2.9 shows trends related to varying the cap dose at fixed trunk dose, and for 10 nm writing the cap becomes more full (lower R g ) for higher cap dose, where the length nearly doubles from 147 nm to 285 nm while varying the dose from 100 to 400 µc/cm 2. l g also doubles in this geometric regime, which should reduce f T significantly for a working device. One would expect high device yield for the third exposure conditions in each figure, and for the condition of Figure 2.8 it is possible that there exist points along the gate periphery that are not in good contact with the semiconductor. 33

56 Trunk length (nm) Trunk length (nm) Q cap = 270 μc/cm nm writing, double-pass 25 nm writing, single-pass Trunk and cap length (nm) nm DP, 4000 Q 350 trunk = Trunk nm, 2250 dose (μc/cm 2 ) nm, 3500 Cap 25 nm, Q cap = 270 μc/cm 2 25 nm writing, single-pass (a) (b) Trunk dose (μc/cm 2 ) nm writing, Figure 2.8: double-pass Exposure dose test summary for free-standing T-gates. (a) Trunk length dependence on trunk 1. dose for fixed cap (a) dose, and (b) representative gate profiles(b) for 10 25nm writing. Trunk and cap length (nm) (a) 25 nm, 2250 nm, 3500Trunk Cap nm, Cap dose (μc/cm 2 ) nm DP, Q trunk = 4750 Trunk (a) Cap dose (μc/cm 2 ) (b) (b) Figure 2.9: Exposure dose test summary for free-standing T-gates. (a) Trunk and cap length dependence on cap dose for several trunk doses, and (b) representative gate profiles for 10 nm writing. 34

57 2.3.2 Dielectrically-defined gates In Section we discuss development of anisotropic and selective PECVD SiO x etching for gate footprint definition. Here we describe our e-beam process that enables construction of sub-50 nm oxide-defined gates. Our dielectrically-defined gate process, which follows the ohmic level, is summarized in Figure After blanket deposition of PECVD oxide the gate trunk geometry is etched into the oxide using an e-beamdefined resist mask (step 1). ZEP is a used due to its improved dry etch resistance compared with PMMA, and this resist is known for high sensitivity and contrast. After stripping the resist and after a gate recess step (optional, Chapter 3) T-gates with a footprints longer than the recess opening are formed (steps 2 and 3). The lithographic footprint length (l g ) of dielectrically-defined gates (see Figure 2.1 (b)) is that of the bottom of the trench etched in the dielectric. Since developed ZEP520A resist gives an undercut profile we were able to start with metal line liftoff dose tests in 100 nm resist films a straightforward way of obtaining baseline critical dimension (CD) curves due to high SEM contrast of metal lines. The test, summarized in Figure 2.11 (a), revealed that we could pattern the resist down to 35 nm CDs. After developing an oxide etching process (Section 3.2.4) we repeated the test, this time with etched instead of metal lines, and found that we could reach even smaller CDs. Figure 2.11 (b) shows the final e-beam doses used to etch SiO x lines with widths ranging from 20 to 1000 nm, all in a PECVD oxide film of 100 nm thickness. Figure 2.12 is an SEM image of one of the dielectrically-defined gates. Note that large volume gate caps can be used with this process, providing small R g, since mechanical stability is not of concern if the oxide is not etched away. 35

58 (a) Bilayer (b) Trilayer plasma ZEP520A SiO x 1) 2) 3) Figure 2.10: Process flow for dielectric T-gate construction. 1) Oxide etching through e-beam-defined ZEP520A mask, 2) Schottky metal deposition through e-beam-defined PMMA950k/PMMA-MAA/PMMA50k mask, 3) liftoff. Figure 2.11: Exposure dose test summaries for 100 nm ZEP520A. (a) Preliminary 10, 25, and 75 nm-written isolated metal lines on Si substrate, and (b) SiO x etched lines defined in layout with various lengths and exposed at optimized dosing. 36

59 Figure 2.12: SEM image of a 68 nm SiO x -defined T-gate constructed using the process described in this Section. Overcoming challenges associated with sub-100-nm electron beam lithography on transparent substrates has provided a basis for much of the microwave HEMT fabrication work described in this dissertation. As the TSF strategy was developed after fabricating first generation recessed-gate HEMTs (Section 4.4), we were at first unable to construct gates shorter than 125 nm. Using this strategy along with the e-beam process development described in this chapter we were later able to construct much shorter l g s, which are presented in Section

60 CHAPTER 3 GATE RECESSING Our success in fabricating high-performance recessed-gate GaN HEMTs hinges on our ability to controllably remove (Al)GaN from a HEMT structure while inflicting minimal damage. In this chapter we first summarize techniques used for etching GaN along and their associated challenges, and then present our development of a controllable, low-damage GaN HEMT gate recess process. 3.1 Etching of GaN-based semiconductors Techniques Two strategies for removal of materials relevant to semiconductor device fabrication are 1) wet etching, where a wafer is immersed into or sprayed with an appropriate chemical etching solution, and 2) dry etching, where the wafer is attacked by a reactive gas-based plasma which either physically (by ion bombardment) sputters material from the surface or chemically forms an etch product at the surface that is either evaporated due to high volatility, sputtered away by energetic ions, or both. Dry etching techniques include reactive ion etching (RIE) [75], low energy electron enhanced etching (LE4) [76], chemically assisted ion beam etching (CAIBE) [77], electron cyclotron resonance (ECR) [78], inductively-coupled plasma (ICP) RIE [79], 38

61 and variations thereof. Usually, fluorine-based chemistries are used to etch Si and Sibased dielectrics, while etching of GaAs and GaN is typically chlorine-based. Pearton and Shul have reported on and reviewed dry etching of GaN and related materials in depth [80]. RIE and its variations find applications in laser facets, via holes, formation of isolating device mesas, and FET gate recessing. The reason that dry etching is used in GaN-based device processing is twofold. Due to the inert nature and strong bond energies (BE) of nitride semiconductors (BE InN = 7.72 ev/atom, BE GaN = 8.92 ev/atom, and BE AlN = ev/atom, all greater than 6.52 ev/atom for GaAs [81]), wet chemicals usually cannot provide a sufficient etch rate for these materials. Also, an anisotropic (vertical sidewall) profile is often desired which wet chemical etching cannot provide. Before GaN-based materials became widely used for electronic devices the major applications of dry etching lied in light-emitting diode and laser diode fabrication, where demands are fast etch rate and smooth surface morphology, while electrical damage is of secondary concern. Reactive ion etching To generate an RIE plasma RF power at a frequency of MHz (regulated by the Federal Communications Commission) is applied to an electrode known as the table, with respect to grounded chamber walls, ionizing a gas mixture to form plasma existing across this cathode-anode pair. A substrate is placed on the table and a negative self-bias potential is induced between the plasma and substrate due to the difference in mobility between electrons and ions. Electrons can then leave the plasma and accelerate toward the cathode while more ions remain in the plasma giving it a net positive charge. Ions, electrons, and free radicals that 39

62 comprise the plasma can react with the substrate material to form chemically volatile etch products, and ions are accelerated across the dark space in between the plasma and substrate, known as the sheath, where they participate in bond breaking and sputter desorption of these etch products. RIE relies on sputtering by energetic ions and electrons, and is known to cause lattice damage at the surface region [82]. Inductively-coupled plasma In ICP-RIE, the degree of chemical etching (plasma density) can be varied independently of the physical etching component (energy of ions impacting the surface) [79]. A key advantage of ICP is that for the same (or higher) etch rate, less material damage can occur when compared with pure RIE due to increased chemical activity. A basic ICP system (depicted in Figure 3.1, courtesy of reference [83]) consists of a dielectric vessel encircled an induction coil. The coil couples RF power to the plasma and is driven at MHz. Magnets external to the vessel aid in plasma confinement and uniformity and the substrate is supported by the RF-powered wafer table whose DC bias is independent of the inductive supply. Etching behavior is chiefly determined by the RF power applied to the table and coil, the chamber pressure, and the gas chemistry. In general, etch rates monotonically increase with inductive (plasma density), and table (ion energy) power. Although the DC bias, or ion energy of the plasma system increases with table power, changing the chamber pressure may increase or decrease the bias, depending on whether the system is in a reactant-limited or reactant-saturated regime Challenges and prior art As mentioned earlier, gate recessing should be done to reduce the distance from gate to channel, and to specifically remove a GaN cap layer which could serve to screen 40

63 Figure 3.1: Schematic diagram of an ICP-RIE reactor. Key components include the RF-powered table and independently-rf-powered coil. Figure 3.7: Schematic of an ICP-RIE system adopted from [70] gate potential variations from the channel and slow a device s frequency response. induces To define opposite fine gate current recess in the patterns plasmadry thatetching primarily should consists be used of high to density accurately thermal control electrons. lateral Thedimensions. interaction between Considerations thermalfor electrons a dry gate and neutral recessingas process molecules include create crystal a high density damage ions and (generally reproducibility. > min 3 reactive ). Sinceion thetching inductive (RIE), coils the are anisotropy not operated of the at etch a high voltage, usuallytheincreases energy of with ionsthe induced ion energy. by the coil However, is low. bombardment A separated RFofsource a semiconductor at 13.56MHz is coupled surface with to theenergetic capacitive ions planar causes electrodes. crystal damage The power which level most applied commonly to this source manifests gives itself as electrically-active trapping and recombination sites, as well as degradation of an independent control on ion energy in the plasma. Unlike the ECR plasma system, it rectifying characteristics of Schottky metals subsequently deposited on the damaged does not require large-sized magnetic source, so the system is easy to implement and can surface [84, 85]. For ohmic contact surface preparation this damage is favorable as be easily expanded for large wafer size. Therefore the ICP-RIE is the simplest yet most it increases conductivity and promotes interfacial field emission [38, 36, 86, 39], but effective high density plasma source. Such system is especially useful for the etching of for Schottky interfaces such as those of HEMT gates it can create leakage, current otherwise hard to etch compound semiconductors such as III-nitrides. Besides independent collapse, noise, and reliability problems. control on ion density and ion energy, the ICP system also operates at low chamber pressure 41 61

64 Selective etching For an etching process to be reproducible, i.e. if it should provide the same etch depth across fabrication runs, it is critical that the etching rate be low such that small fluctuations in the rate do not cause significant differences in etch depth for a given etch duration. If removing cap material from upon a dissimilar material the underlying material can serve as an etch stop layer and processes that selectively etch the top layer at a faster rate than the underlying layer can provide reproducibility of etch depth. A well-known example is the selective RIE of GaAs over AlGaAs, where after clearing the GaAs layer reactive fluorine species in a plasma create a nonvolatile AlF x selvedge layer on the AlGaAs surface that is not easily sputtered away. The ratio of the GaAs etch rate to the AlGaAs etch rate, known as the GaAs/AlGaAs selectivity, has been reported to be 200 [87]. Gate recessing for AlGaN/GaN HEMTs has been done previously by Cl 2 - and BCl 3 - based RIE [88, 89, 49, 90, 48]. Such processes offer little etch selectivity between a GaN cap layer and AlGaN barrier making it difficult to control the etch depth. Also, energetic ions used in RIE can cause electrical damage. For example, BCl 3 recessing of an n + -GaN cap in reference [48] increased gate leakage compared to devices with a cap layer beneath the gate. Although photo-enhanced chemical (PEC) etching has been applied to GaN-based gate recessing without ion damage [91], PEC etching typically creates rough surfaces and etch selectivity is low. High selectivity using Cl 2 - based plasmas containing oxygen, which form oxide-based layers on AlGaN, has been reported [92, 93, 94, 95]. Wang et al. demonstrated recessed n + -GaN/AlGaN/GaN HEMTs, where the gate recessing was done using Ar/Cl 2 /CH 4 /O 2 RIE, giving a selectivity of 11 and a GaN etch rate of 31 nm/min. Han et al. noted that oxygen 42

65 more readily reacts with AlN in plasmas containing N 2 [96], and subsequently used N 2 /Cl 2 /O 2 inductively-coupled plasma RIE (ICP-RIE) to selectively etch GaN over AlGaN [94]. In that report the high (-220 V) plasma bias resulted in GaN etch rates greater than 50 nm/min and selectivity as high as 60, and processes such as these cannot controllably etch thin ( 10 nm) cap layers without excessive damage. In this work we have focused on a similar etching chemistry, but with zero plasma bias for minimal crystal damage. 3.2 Gate recess development We based our etching strategy on the Cl 2 /N 2 /O 2 chemistry for two reasons: 1)Increase of n-conductivity in GaN has been credited to liberation of nitrogen during RIE [97, 98, 99], and an N 2 -containing etch process may reduce the number of nitrogen vacancies formed in the gate area preventing unintentional surface doping and increased gate tunneling current, and 2) The concentration of oxygen in a Cl 2 /N 2 /O 2 is a powerful process knob which can allow strong control over etch rates as we proceed slowly through GaN or AlGaN layers. Since organic resists are quickly etched by oxygen-containing plasma, and even oxygen-free plasmas can leave resist residues that are difficult to remove, we used hard dielectric masking for gate recessing. Surface passivation for AlGaN/GaN HEMTs is typically done by plasma-enhanced chemical vapor deposition (PECVD) dielectrics such as SiN x and SiO x [26, 27]. For our recessed HEMT process, we desired the option of leaving the dielectric recess masking layer in place for surface passivation so we needed a dielectric that was not easily etched by our recessing process. It is known that the etch rate of oxide in chlorine plasma is lower than that of nitride, although both are quite low. Furthermore, the 43

66 presence of nitric oxide in F-based plasmas has been shown to greatly increase the rate of chemical etching of Si 3 N 4 [100]. Since our N 2 /Cl 2 /O 2 plasma likely contains reactive NO, and despite reports that SiN x passivation is more effective than SiO x, we decided to use SiO x masking with the expectation of greater etch resistance during gate recessing compared to SiN x. We also anticipated the ability to etch more anisotropic, aggressively scaled gate trenches in oxide compared to nitride Preliminary etch tests In an Oxford Plasmalab System 100 plasma etching tool with an ICP source we monitored selectivity and etch rates as a function of table (RF) and source (ICP) power, pressure, and Cl 2 and O 2 mole fractions while etching hydride vapor-phase epitaxial (HVPE) films of n-gan and Al 0.4 Ga 0.6 N on c-plane sapphire substrates. After degreasing in organic solvents and masking with e-beam-deposited SiO x patterns, etching was carried out for 30 min at room temperature with a gas flow of 40 sccm and base pressure of Torr. After mask stripping by buffered HF (BHF), etch rates were determined by measuring the (Al)GaN etched step heights by surface profilometry (for step heights greater than 100 nm) and AFM (for step heights less than 100 nm). To eliminate etch dead time which has been blamed for the observed selectivity of some GaN-over-AlGaN etch processes, we preceded each etch with a mild BCl 3 RIE step for in-situ native oxide removal [97, 101]. This deoxidation step showed no etch selectivity and was used to etch 1 3 nm of material, depending on the intended total etch depth. We began with Cl 2 -rich, low pressure conditions. With a N 2 /Cl 2 flow ratio of 1/3, 3 mol% O 2, 2 kw source power, and set pressure of 3 mtorr, we varied table power 44

67 and realized a 38 nm/min GaN etch rate even at zero bias (much higher than our target rate of 5 nm/min), and etched surfaces that were visibly-roughened. We then set the table power to zero and varied the Cl 2 mol% from 50 to 0, which resulted in decreasing etch rates for GaN and AlGaN and visibly-smoother etched surfaces for mol% Cl 2 < 6. Based on this trend, we set the N 2 /Cl 2 flow ratio to 16 and varied the source power from 1.5 kw to 3 kw, over which the GaN etch rate increased from 6 to 24 nm/min while selectivity remained at a nearly constant value of 5. It was found that this level of selectivity persisted in a pressure- and oxygen-limited regime and that increasing these parameters increased the GaN-over-AlGaN etch selectivity. We evaluated Cl 2 and O 2 etch dependencies at 10 mtorr and 3 kw ICP, as shown in Figure 3.2. These plots show increasing selectivity for decreasing mol% Cl 2 and increasing mol% O 2, and since no AlGaN etching could be detected for mol% Cl 2 < 7 and mol% O 2 > 20, the selectivity for the corresponding points is unknown. For our purposes the GaN/AlGaN etch selectivity for points with finite GaN etch rate and zero AlGaN etch rate is infinite. The AFM height data of Figure 3.2 (c) show that after 30 min of etching using the ICP recipe corresponding to the 25 mol% O 2 point in Figure 3.2 (b), over 100 nm of GaN is etched while no AlGaN etching takes place Etching mechanism To evaluate the role of temperature in zero-bias GaN etching we decreased the table temperature from 20 to 0 C and saw no change in GaN etch rate. Next, to improve heat transfer, we flowed helium across the backside of the quartz carrier wafer upon which the sample was fixed during etching, and noticed a large decrease in the etch rate from 4 to 0 nm/min and concluded that the etching was driven 45

68 Etch rate (nm/min) Vertical distance (nm) (a) (b) (c) 10% O 2? mol% Cl 2 N 2 /Cl 2 = 16? GaN AlGaN mol% O 2 GaN 30 min etch AlGaN Lateral distance (μm) Selectivity Figure 3.2: Dependence of (a) Cl 2 and (b) O 2 fraction on GaN and Al 0.4 Ga 0.6 N etch rates and selectivity at a source power of 3 kw and a pressure of 10 mtorr. The 50% Cl 2 data were collected at 3% O 2, 3 mtorr, and 2 kw. The etch depth for the circled points is below the AFM detection limit so we include arrows indicating expected selectivity trends. (c) AFM step surface profiles for GaN and Al 0.4 Ga 0.6 N etched for 30 min using the recipe of the circled point in (b). This data is the average over 256 adjacent acquisition lines. 46

69 by evaporation of etch products from the high-temperature surface of the sample. Conversations with Oxford plasma engineers suggested that during etching sample surfaces commonly exceed 200 C. As evident from Figure 3.2 (a), high etch rates favor the availability of reactive chlorine species. The boiling point of GaCl 3 is 201 C, and evaporation of this and similar etch products likely enables zero bias etching, which is prevented by backside cooling. Oxygen slows etch rates of GaN and AlGaN as it forms stable oxides with Ga and Al, but due to the higher volatility of Ga-based oxides compared to oxides involving Al, the etching of Ga oxides takes place faster than Al oxides, providing GaN/AlGaN selectivity. N 2 acts to dilute reactive chlorine in the plasma, reducing etch rates, and also to increase the reactivity of O 2 [96] which enhances selectivity. The addition of N 2 to the plasma not only slows etch rates but also increases the smoothness of the etched GaN, as shown by the AFM images of Figure 3.3 (a-c). The GaN surface in (c) was etched using the N 2 -rich conditions of the circled point in Figure 3.2 (b), and in Figure 3.3 (b) the N 2 /Cl 2 flow ratio was 1/3. The rms surface roughness R q (evaluated over 1 µm 2 scan areas) increases from 21 to 73 Åafter etching in the Cl 2 -rich plasma, and decreases to 16 Å after etching by N 2 -rich plasma. We selectively etched [using recipe similar to the circled point in Figure 3.2 (b)] the MOCVD HEMT device structure represented in the inset of Figure 3.4. The AFM-measured etch depth versus time data show GaN etching at a rate of 4 5 nm/min, and stopping abruptly after clearing 11 nm of material which comprises the n + -GaN cap and native oxide layer. No AlGaN etching is observed even after 10 min (the longest duration considered here), suggesting that exact etch duration 47

70 Figure 3.3: (a-c) AFM images of an HVPE GaN surface before plasma etching, after etching for 30 min in a Cl 2 -rich plasma, and after etching for 30 min in a N 2 -rich plasma. The 1 µm 2 R q more than triples after etching in the Cl 2 -rich plasma, and decreases after etching in the N 2 -rich plasma. (d) and (e) are images of the HEMT layer surface before and after etching for 3.5 min using the N 2 -rich recipe noted in Figure 3.4. The etch depth in (e) is 11 nm and the 1 µm 2 roughness was decreased by 50% after etching. All samples had been submerged in BHF for 90 s for SiO 2 mask stripping. 48

71 Etch depth (nm) GaN cap thickness ~1 nm AlN ~10 nm n + -GaN 23 nm Al 0.3 Ga 0.7 N 2~3 μm UID GaN Sapphire (0001) N 2 :Cl 2 :O 2 = 70%:5%:25% 10 mtorr 3 kw ICP Etch time (min) Figure 3.4: Etching trend for the n + -GaN/Al 0.3 Ga 0.6 N/GaN HEMT structure represented in the inset. The etch stops abruptly after clearing the n + -GaN cap layer. The lines are a guide for the eye. is not critical for removal of the cap layer only. This N 2 -rich gate recessing process leaves very smooth AlGaN surfaces, which is evident from the AFM image of Figure 3.3 (e). This image shows the morphology of our device structure after etching to a depth of 11 nm, and the rms roughness (R q ) is actually reduced to 3 Å, compared to 6 Å for the non-etched surface [Figure 3.3 (d)] Electrical & chemical characterization We used Schottky diode structures [illustrated in the inset of Figure 3.5 (a)] to evaluate electrical characteristics of selectively-etched device layers. The fabrication commenced by defining a Ti/Al/Mo/Au ohmic field by e-beam deposition and liftoff and annealing at 850 C. After ensuring that our ICP process did not etch gold, a gold ohmic overlay was deposited to conceal the potentially-reactive ohmic contact (a strategy used later for recessed-gate HEMTs), and recess etching was self-aligned to 49

72 the gold-capped ohmic contact without further masking. To evaluate the sensitivity of AlGaN electrical properties to plasma exposure duration and hence the process controllability, three samples were considered: a reference that was not recessed, and two for which the cap was completely recessed for durations of 6 min and 18 min. Finally, circular Ni/Au Schottky contacts with diameters varying from 40 to 120 µm were deposited. Current-voltage (I-V ) and capacitance-voltage (C-V ) measurements were performed to characterize the leakage current and breakdown performance, as well as changes in n s, with respect to to recess etching. I-V results are shown in Figure 3.5 (a) and the relevant observations are that recess etching reduces reverse leakage current by nearly two orders of magnitude, and the forward saturation current is increased by a factor of three. The increase in forward current is due to removal of the cap layer between the Schottky and ohmic metal, which has reduced series resistance. Besides the slight increase in low-bias leakage for the 18 min-etched diodes compared to the 6 min-etched diodes, once the cap layer is completely etched (after 3.5 min), further plasma exposure has little effect on the -5 V leakage current. Attempts to extract meaningful Schottky barrier heights using thermionic models failed due to high ideality factors of 3 4, likely resulting from a dominant tunneling component through an oxide layer at the metal-semiconductor interface (for recessed diodes) and due to the heavily-doped cap layer (for non-recessed diodes). The high-bias reverse characteristics [Figure 3.5 (b)] showed a breakdown voltage for recessed diodes in excess of -200 V compared to -90 V for non-recessed diodes. 50

73 Finally by integrating reverse-biased C-V curves from zero bias to pinch-off, we observed that recess etching for 4 minutes induced a 14% increase in equilibrium n s from to cm 2, which is due to removal of negative polarization charge induced by the n + -GaN cap at its interface with AlGaN. Further plasma exposure decreased n s (without etching the AlGaN barrier, as suggested by Figure 3.4). As equilibrium n s decreases with exposure time, the pinch off voltage shifts in the positive direction reaching just greater than -2 V for 18 min exposure. We exploit this trend, along with actual thinning of the AlGaN barrier, in Chapter 4 to achieve enhancement-mode HEMTs. By the C-V profiling method [102] we mapped the electron distribution through the depth of non-recessed and 4 minute recessed heterostructures, and these profiles are shown in Figure 3.6. From these profiles we confirm that the 2DEG has indeed shifted by 10 nm from the surface due to a nominal 10 nm GaN cap layer etch. To generate these carrier profiles we biased diodes up to positive 3 V in attempts to accumulate electrons in the heavily-doped cap layer (positive-biased data not used to calculate n s ). Such accumulation was not observed and we can thus say that this surface layer is depleted of carriers an important observation when analyzing device gate leakage in Chapter 4. To correlate electrical and chemical surface behaviors of etched nitride surfaces, non-patterned Al 0.4 Ga 0.6 N samples were processed in the ICP chamber along with the diodes, and were immediately loaded into an x-ray photoelectron spectroscopy (XPS) chamber for surface analysis. The core level electron spectra shown in Figure 3.7 were acquired by normal-incidence collection of electrons excited by monochromated Al Kα (for Al 2p and Ga 3d) and Mg Kα (for O 1s and N 1s) sources. The 51

74 Current density (A/cm 2 ) Current density (A/cm 2 ) (a) Applied bias (V) (b) reference 6 min 18 min Applied bias (V) DEG density (10 12 cm -2 ) (c) Plasma exposure time (min) Pinchoff voltage (V) Figure 3.5: (a) I-V characteristics for diodes that were recess-etched 0, 6, and 18 min,(b) reverse breakdown characteristics for non-recessed and 6-min recessed diodes, and (c) C-V -extracted n s and pinch off voltage versus recessing plasma exposure duration. The inset in (a) shows a plan view of the Schottky diode topology. Electron density (cm -3 ) For C-V, recessed V max = +3 V 10 nm non-recessed Depletion width (nm) Figure 3.6: C-V -extracted electron profiles for non-recessed and 4 minute recessed Schottky diodes on AlGaN/GaN with 10 nm n + -GaN cap layer. The data points closest to the surface for each curve correspond to a DC bias of +3 V. 52

75 positive binding energy (BE) shifts of the Al and Ga peaks after etching suggest increased surface Al-O and Ga-O bondings at the expense of Al-N and Ga-N bondings, and a post-etch increase in surface oxidation is confirmed by chemical ratios (not shown), where surface compositions were calculated considering integrated peak intensities and sensitivity factors for the instrument. These data show a post-etch decrease in all mass% ratios with oxygen in the denominator. We hence attribute the decrease in diode leakage to (1) removal of the heavily-doped cap layer, and (2) a thin insulating oxide layer at the metal-semiconductor interface. The low-be shoulder of the reference oxygen peak shown in Figure 3.7 (a) (likely indicative of O-H bonding) is decreased after etching at the expense of a high-be component (O-Ga and O-Al bonding), and the nitrogen peak shifts to higher BE, possibly due to oxynitride formation. It is interesting to note that the BE shifts of the 18 min-etched sample are identical to those of the 6 min etched sample, and this further suggests that this N 2 /Cl 2 /O 2 selective etching should not suffer from run-to-run variability SiO x patterning Before applying our recess etching to HEMTs we needed to verify its scalability to deep-submicron dimensions, and hence first optimized anisotropic low-bias etching of PECVD SiO x. Etching of SiO x (or Si or SiN x ) is typically done with fluorinebased plasmas such as CF 4, SF 6, NF 3, C 4 F 8, or CHF 3, where the main etch product is SiF 4. Our goal was to obtain vertical etching at low plasma bias (to minimize damage to the underlying device layers) usually conflicting goals. To this end, we exploited the tendency of nonvolatile fluorocarbons to adsorb on surfaces in plasmas containing F and C. When a sufficient plasma bias is applied, polymerization occurs 53

76 Figure 3.7: (a) X-ray photoemission spectra acquired from Al 0.4 Ga 0.6 N etched by N 2 /Cl 2 /O 2 ICP for varying durations. The binding energy scales have been corrected for charging effects. 54

77 only on sidewalls of etch trenches, since normally-incident ions sputter polymer at the bottom of a trench. The F/C ratio determines the degree of polymerization that takes place and sidewall profiles can be tuned by adjusting this ratio. In general, lower F/C means more polymerization and a more vertical or even sloped profile. One would expect SF 6 RIE, for example, to give a more undercut (isotropic) SiO 2 profile than CF 4. Adding H 2 (O 2 ) reduces (increases) F ion concentration by forming HF (CO 2 ) [103, 104]. A disadvantage of dielectrically-defined gate fabrication [105] where the gate cap directly contacts the dielectric is an increase in parasitic fringing capacitance when compared to a typical free-standing gate cap with a lower dielectric constant air between gate cap and channel [106, 107]. We hence needed to evaluate the trade-off between reducing capacitance by increasing oxide thickness, and increased process difficulty with respect to forming short gates in thick dielectric. To make very short lines in e-beam resist the resist must be thin to minimize line broadening from forward electron scattering. When used as an etch mask the resist must be thick enough as not to be etched away during the time it takes to clear the underlying masked layer. The time it takes to clear the underlying layer (oxide) in our case becomes longer as the film thickness is increased, and these interacting factors describe our design challenge. We calculated the total gate capacitance with respect to oxide thickness by modeling the gate as parallel capacitors whose top electrodes are a 100 nm gate footprint and 500 nm gate cap (similar to the model shown later in Figure 4.23). We estimated that, compared with 200 nm oxide, reducing to 100 nm increased fringing capacitance by 9% whereas decreasing to 20 nm increases the extra capacitance by 55

78 59%. We resumed our process development using a 100 nm thick oxide film. For reduced forward electron scattering during EBL we used a thin (100 nm) ZEP-520A layer to define fine lines for SiO x etch testing, and hence we required SiO x /ZEP etch selectivity greater than unity. We found, however, that the etch selectivity under F-based RIE is typically low. We first explored CF 4 (F/C=4) RIE of SiO x, and found under all conditions selectivities well under unity. We next considered CHF 3 (F/C 2) and obtained insufficient etch rates over the desired bias range ( 200 V). As shown in Figure 3.8 (a), by adding a small fraction of O 2 to CHF 3, higher etch rates (and reasonable selectivity) can be achieved. We also found that selectivity is a strong function of chamber pressure, as shown in Figure 3.8 (b). SEM images of trenches etched by various CHF 3 /O 2 plasmas are shown in Figure 3.9. Increasing the ion density by applying ICP power created a resist residue layer that could not be removed by acetone, as shown in Figure 3.9 (C). We attribute this to resist crosslinking and cooking by high energies and temperatures associated with ICP plasma. At low temperature the etch is more anisotropic than when the table is held at room temperature, which can be seen by contrasting images A with A. At 80 mtorr a more anisotropic etch is possible than at 90 mtorr, although the selectivity is also lower. This suggests increasing polymerization with pressure, making the resist more etch-resistant and over-passivating the trench sidewalls. This increased anisotropy allowed us to reduce the plasma bias to -120 V while maintaining vertical sidewalls as shown in Figure 3.9 (B ). As the resist line width is reduced to 40 nm, SiO x line width is reduced to about 20 nm [Figure 3.9 (B 20 )] and etch depth is reduced by about 40% compared with oxide line widths greater than 100 nm. The trend of etch depth versus SiO x line width is shown in the plot of Figure 3.9 and here we can 56

79 SiO x etch rate (nm/min) CHF 3 /O sccm 80 mtorr -200 V %O 2 (a) SiO x /ZEP selectivity SiO x etch rate (nm/min) CHF 3 /O 2 100/2.5sccm -200 V (b) Pressure (mtorr) SiO x to ZEP selectivity Figure 3.8: (Trends in SiO x etch rate and selectivity over ZEP-520A with respect to (a) oxygen mole fraction and (b) chamber pressure for -200 V CHF 3 -based reactive ion etching. see that the dependence is most pronounced for sub-100-nm lines. We later verified the process by etching oxide layers on GaN and saw no etching of the underlying GaN layer. SiO x /GaN recessing Before applying the oxide-etch/gate-recess to HEMT fabrication we verified the process by etching thick-film HVPE GaN through e-beamdefined trenches in oxide. The SEM image of Figure 3.10 shows the resulting cross sectional etch profile where in this case the oxide and GaN etch steps were done in serial under a single reactor pump-down. Later for HEMT fabrication the sample is removed from the etch tool in between etching steps to strip the oxide mask. Through 100 nm oxide openings we removed 24 nm of HVPE GaN in this test. During this experiment we also confirmed that the wet BHF mask stripping of earlier tests was not responsible for GaN etching. 57

80 SiO x line width (nm) A 90 mtorr -200 V 23 nm/min S=3.4 A 90 mtorr -200 V 3 o C 40 nm/min S= B 80 mtorr -120 V 27 nm/min S=1.6 B B mtorr -120 V 3 o C C 80 mtorr -120 V 3 o C 27 nm/min S= mtorr -200 V 500 W ICP Normalized etch depth Recipe B 500 nm SiO x line width (nm) Figure 3.9: SEM images of 300 nm PECVD SiO x films etched using CHF 3 /O 2 = 100/2.5 sccm RIE. We refer to the recipes by the letter appearing in the top left of each image. In each case the resist line width determined by metal liftoff was 100 nm, except for B 20, where the resist line width was 40 nm. The plot at right shows the normalized dependence of SiO x etch depth versus line width using recipe B, where a dependence is observed for sub-100 nm lines. Figure 3.10: (SEM image of HVPE GaN etched for 20 min by N 2 /Cl 2 /O 2 ICP through a 100-nm-wide window in 100-nm-thick SiO x. The GaN etch depth is 24 nm and no SiO x is etched. 58

81 To our knowledge ours (see reference [108]) was the first report of purely chemical plasma etching of GaN, whereas other reports have depended in energetic ion sputtering of etch products. Variations of the N 2 /Cl 2 /O 2 ICP process described in this chapter are used in the next chapter both for highly selective etching of GaN cap layers, as well as controlled ( 1 nm/min) etching into the AlGaN barrier to fabricate depletion and enhancement-mode HEMTs. 59

82 CHAPTER 4 GaN-BASED HIGH ELECTRON MOBILITY TRANSISTORS 4.1 HEMT layers For our study we consider four different HEMT layer structures, all of which were procured from a common vendor, and are depicted in Figure 4.1. All wafers were grown by MOCVD in the [0001] direction and wafers A and C were grown in consecutive growth runs, as were wafers B and D. All wafers have a 23 nm thick Al 0.3 Ga 0.7 N barrier layer with a 1 nm AlN interfacial layer. The AlN layer is meant to reduce alloy disorder scattering by reducing channel distribution tailing into the AlGaN layer [51, 109]. Each wafer has a GaN buffer with graded Fe compensation doping, where the density is graded from level deep in the layer down to zero (nominally) near the channel. Wafers C and D have Si-doped n + -GaN cap layers of 5 and 10 nm, respectively. Wafers A, B, and C have 4H-SiC substrates, and wafer D is C-plane sapphire. Wafer D was used for some of the gate recess process development discussed in Section 3.2 as well as for preliminary recessed-gate device development (Section 4.4). On wafers A and B we fabricated baseline 0.22 µm devices to evaluate the epitaxial material, and finally we carried out our systematic device scaling study 60

83 n + -GaN, 5 nm n + -GaN, 10 nm Nominal buffer Fe grading High Low Al 0.3 Ga 0.7 N, 23 nm GaN:Fe, 2 m Buffer #1 Nucleation layer 4H-SiC AlN, 1 nm Buffer #2 4H-SiC Buffer #1 4H-SiC Buffer #2 Sapphire A B C D Figure 4.1: HEMT layer structures used in this work. Wafers A and C are from consecutive growth runs, and wafers B and D are from consecutive growth runs. All wafers have a barrier consisting of 23 nm Al 0.3 Ga 0.7 N and 1 nm AlN, as well as graded buffer Fe compensation doping. on wafer C. Throughout this section we will use letters A-D in reference to these GaN HEMT wafers. 4.2 Device processing A summary of our recessed-gate GaN HEMT process flow, which is based upon mesa-isolated liftoff technology, is given in Figure 4.2. Circled steps are specific to recessed-gate devices and we skip these steps for a basic non-recessed process, as is used for the baseline devices of Section 4.3. Further fabrication details can be found in the sample process traveler included in Appendix A. We begin with electrical isolation etching using BCl 3 /Cl 2 /Ar ICP-RIE to a depth of 75 nm below the channel. Throughout this work we evaluate devices with 100 µm of gate periphery (2 50 µm T-shaped topology) where the gates must overlap the mesa edge to connect with their central feed electrode. This overlap limits the mesa etch depth as too deep an etch would increase the risk of the gate metal separating at this edge. Ohmic 61

84 recessing with SiCl 4 RIE is done for second generation devices to reduce the effective surface barrier in the ohmic regions [41]. Our ohmic contact stack is, from bottom to top, Ti/Al/Mo/Au. Using Mo as a diffusion barrier has been reported to improve morphology and edge acuity when compared to other common diffusion barrier metals [110]. Development of the ohmic process for GaN-capped wafers, including etching and annealing, is described in Section Following ohmic we blanket deposit an oxide film by PECVD, and then remove the oxide from over the probing pads and deposit Ti/Au overlay metal. This step is done early so that annealed ohmic metal is never exposed to plasma during gate recess steps, and to avoid coating resist unnecessarily over the recessed active region later in the process. Next we transfer the gate footprint lines into the oxide using EBL and the CHF 3 /O 2 etch process described in Section 3.2.4, and perform gate recess per the technology outlined in Section 3.2. Finally, T-gates are defined by EBL and Ni/Au metallization as described in Section Baseline HEMTs - sub-v T analysis We fabricated 0.22 µm devices on wafers A and B using our non-recessed base process to establish a performance baseline. We found that wafer A exhibited record pinch off and subthreshold performance, and we attribute this behavior in part to a highly insulating Fe-doped buffer DC analysis For this wafer we optimized the ohmic annealing temperature and time to 870 C and 30 s, which gave contact resistance of Ω-mm using the transfer length method. Sheet resistances of 342 and 365 Ω/ were estimated for wafers A and B, 62

85 4. Oxide deposit 8. Gate recess GaN AlGaN GaN 1. Mesa isolation 5. Overlay oxide etch 9. Anneal 400 o C 2. Ohmic recess 6. Overlay metal 10. Gate metal 3. Ohmic metal/anneal 7. Gate oxide etch 11. Oxide strip (optional) Figure 4.2: Processing flow for recessed-gate GaN-based HEMTs: 1. Mesa isolation, 2. ohmic recessing, 3. ohmic deposition and anneal, 4. PECVD oxide deposit, 5. overlay oxide etch, 6. overlay metal, 7. gate footprint oxide etch, 8. gate recess, 9. anneal, 10. T-gate formation, and 11. optional oxide strip. Circled steps are specific to recessed-gate devices, and are not used for non-recessed devices. 63

86 respectively. For wafer A we found that in order to measure off-state drain and gate current we needed to improve our low-current measurement capability. So, a Faraday cage was constructed around our DC probe station allowing us to drop the noise floor of our Agilent 4156c semiconductor parameter analyzer DC setup to several femtoamperes. Although devices on both wafers showed DC transconductance of 190 ms/mm and threshold voltages around -3.7 V at V ds = 5 V, the measured DC transfer curves and corresponding gate leakage at this drain bias for the two wafers shown in Figure 4.3 (a) showed acute differences in the subthreshold region of operation. Devices on wafer A showed exceptional pinch off performance, one in particular having subthreshold V gs swing of 67 mv/dec measured at V ds = 5 V. Around the pinch off regime of operation, subthreshold swing (S), defined as [3] S = ln10 dv gs d(lni d ) (4.1) is a measure of the decrease in gate voltage needed to reduce the drain current by one decade, and is an indicator of the channel confinement and potential scalability of a FET. The theoretical limit of S is ln10kt/q or 60 mv/dec at room temperature. The on/off drain current ratio I ON /I OF F for this device, where I ON and I OF F were measured at V gs = 0 and V, respectively, exceeded the level. Although improvements in off-state drain leakage have been demonstrated by oxidation of the gate and access regions of AlGaN/GaN HEMTs for reduced surface and barrier tunneling leakage [111, 112], these two figures of merit were better than any previously-reported values for submicron GaN HEMTs. Many devices on both wafers showed little or no 64

87 Drain and gate current I d, I g (A) wafer "B" S = 127 mv/dec I on /I off = 1.4 x 10 7 wafer "A" S = 67 mv/dec I on /I off = 1.4 x (a) Gate to source voltage V gs (V) Buffer I ds and gate I dg current (A) 10-5 I "A" ds I dg "A" 10-7 I ds "B" I dg "B" (b) V ds = 5 V V gs = -5 V Off-state drain current I OFF (A) Figure 4.3: (a) Transfer curves for 0.22 µm T-Gate GaN HEMTs built on wafers A and B, measured at V ds = 5 V (symbols) and 10 V (solid lines) where gate current is shown for V ds = 5 V and source-drain separation is 3.5 µm. (b) Subthreshold buffer and drain-gate current vs. total subthreshold drain current for all devices measured from each wafer. The lines are linear fits to the experimental data for wafer A. DIBL effects, defined as the change in V gs Id =1mA/mm for an increase in V ds from 5 to 10 V. The solid lines in Figure 4.3 are for drain current measured at V ds = 10 V, and are not shifted noticeably from the I d points measured at 5 V. When comparing V ds = 0.1 V to V ds = 5.1 V we see average DIBL of 24 mv/v. Compared to HEMTs fabricated on wafer B, those on wafer A showed S reduced nearly by half. I ON /I OF F increased and gate current decreased, both by several orders of magnitude. The ability to realize record pinch off characteristics with 0.22 µm gate devices speaks to the potential scalability of devices based on wafer A. The level of gate leakage current in the off-state is usually of the same magnitude as the drain leakage, for both wafers, and it is interesting to evaluate the subthreshold 65

88 drain current as two components drain to gate leakage I dg and drain to source leakage I ds. After measuring I g and I d at (V gs, V ds ) = (-5, 0) V and at (V gs, V ds ) = (-5, -5) V, we estimated each component as I ds5 = I g5 + I d5 I sg0 (4.2a) and I dg5 = I d5 I ds5 (4.2b) Where the variables are defined in the model of Figure 4.4. The current flowing from source to gate under zero bias, I sg0, was estimated as the gate current less the drain current measured during a gate-to-source diode sweep with drain shorted to source. Results of this analysis are plotted in Figure 4.3 (b) where it can be seen that the two components are generally of the same order of magnitude. When drain leakage current exceeds a few nanoamperes the majority of the drain leakage is through the gate, rather than the buffer. It is only for wafer A devices with off-state drain current below approximately 50 pa that buffer leakage exceeds drain-gate leakage. For most devices at V gs = -5 V, gate current is greater than or equal to drain current due to source-gate leakage. Devices were sufficiently isolated such that leakage across the isolating field region is negligible. A previous report showed a log-linear dependence of subthreshold swing on gate leakage [111], and we also observed an increasing trend as shown in Figure 4.5. Here we plot, for each device measured, S versus I g for V ds = 5 V and V gs = -5 V. Devices on wafer A showed subthreshold swing below 100 mv/dec, even for I g as high as 100 na. S for wafer B devices is larger and the S-I g slope is larger by factor of four, 66

89 V gs = -5 V (pinched-off) V ds = 0 V G I g0 V gs = -5 V (pinched-off) V ds = 5 V G I g5 I sg0 I sg0 I dg5 S D S D (a) I ds5 (b) I d5 Figure 4.4: Biasing schemes and symbol definition for off-state drain current analysis. suggesting that some other mechanism dominates here. A possibility is that for higher gate leakage, as well as for higher off-state drain leakage, either more of the leakage current flows along the mesa edge or the gate-drain leakage is high due either to tunneling or surface current D it estimation Along with HEMTs we fabricated circular Schottky diodes of 200 µm diameter for capacitance-voltage measurements, and we used these diodes to analyze trapping activity in the devices. The room-temperature capacitances measured at 1 MHz are 380 and 340 nf/cm 2 for wafers A and B, respectively. To estimate the effective density of Ni/AlGaN interface traps (D it ) for these samples we assume that these traps have time constants slower than 1 µs and use the measured capacitances as the AlGaN barrier capacitance C i in the MOSFET expression S = ln10 kt q ( 1 + C ) D + C it C i (4.3) 67

90 Fig. 3. Subthreshold buffer and drain-gate current vs. total subthreshold drain current for all devices measured from each wafer A. The lines are linear fits to the experimental data. NEED TO MEASURE WAFER B! ALSO CONSIDER OTHER LEAKAGE PATHS, SUFRACE CURRENT Subthreshold swing S (mv/dec) μm "A" 2.5 μm "A" 2.0 μm "A" 1.5 μm "A" 3.5 μm "B" 4x larger slope Gate current I G (A) Fig V V DS subthreshold swing with respect to (a) gate to source and drain leakage at V GDS = -5 V and (b) off-state drain current at V GS = V. Results for devices with four Data are sorted by drain-source separation for wafer A, and the two lines are log-linear fits to data from wafers A and B. s 3.5, 2.5, 2.0, and 1.5 μm are shown. Figure 4.5: 5 V V ds subthreshold swing with respect to gate to source and drain leakage at V gds = -5 V. Data are sorted by drain-source separation, and the two lines are log-linear fits to data from wafers A and B. Add something like this somewhere: where kt/q is the thermal voltage. We neglect the very small depletion capacitance Devices on wafers A and B showed 14 and 12 percent C D for the non-doped I D collapse, HEMT respectively, and estimate compared the effective to measurements capacitancepulsed due to Schottky from (V GS,V DS ) = (0, 0) V. To determine the impact of interface traps, C it, for the two wafers. We use average values of subthreshold swing surface trapping on device pinch-off, we passivated wafer A for each waferdevices in our calculation, with SiN x as and well as repeated the 1 MHz the capacitances, pulsed and to dc estimate D it measurements. Although I D collapse reduced to 9 percent, for wafers A and suggesting B as 7.3± a decrease 11 in and surface 2.3± trapping 12 activity, cm 2 evthe 1, sub-v respectively. T D it swing did not change significantly. This indicates that the values below 10 excellent 12 are exceptionally low for AlGaN/GaN HEMTs and when extracting pinchoff reported here for wafer A is not D it solely based significantly on S we must influenced keep in by mind surface that electron DC leakage trapping currents related that are not channel depletion. trap-related can affect the result SIMS We used Dynamic secondary ion mass spectrometry (D-SIMS) to estimate the distribution of Fe atoms in the two wafers and correlated this with electrical behavior. The instrument used was a Cameca ims-5f with an O + 2 analysis beam and magnetic 68

91 Figure 4.6: D-SIMS profiles for Al27 and Fe56 masses in wafers A and B. sector analyzer. The sensitivity of the instrument is cm 3. The measured concentration profile is shown in Figure 4.6, where we notice three distinct differences in the distributions of Fe atoms in the two wafers, namely, the Fe concentration in wafer A when compared to wafer B is: 1. over an order lower deep in the buffer, 2. slightly greater in the region just below the heterointerface, and 3. two orders lower at the surface. Although during epitaxy the iron source was turned off early during buffer growth, it seems as if residual Fe in the MOcVD reactor continued to incorporate toward the surface. Although D-SIMS measurements at the surface can be erroneous and the absolute concentrations are likely much lower than shown in Figure 4.6, the surface Fe concentration in wafer B is clearly larger than in wafer A, which may be responsible for larger D it and gate leakage for wafer B. We may also credit the increased Fe concentration just below the channel region of wafer A to improved channel electron confinement, which would also result in reduced subthreshold swing. 69

92 4.3.4 Dynamic I-V Thus far we correlated the superior subthreshold behavior of devices on wafer A with low D it at the gate-algan interface, which may be related to lower unintentional Fe doping of the AlGaN surface region compared to wafer B. However, surface trapping near the gate in a device s access regions could play a major role in a its transfer curve, where for V gs V t and positive V gd electrons from the gate fill donor-like states and further deplete the channel [25]. This virtual gating phenomenon could manifest as off characteristics and low off-state drain current, and hence we needed to evaluate such effects. To this end we passivated devices on wafer A with PECVD Si 3 N 4 performing pulsed I d -V ds and DC I d -V gs measurements before and after passivation. If surface trapping dominates the sub-v T behavior then we expect passivation to degrade sub-v T and also to decrease the degree of current collapse seen in the pulsed measurements. For details of dynamic I-V measurements refer to Appendix B. Pulsing from a quiescent bias of V gs, V ds = (0, 0) V with a pulse length and duty cycle of 1 µs and 0.01%, we measured I d -V ds at V gs = 0 V for three devices on wafer A before and after passivation (Figure 4.7 (a,b)). After passivation, DC drain current increases along with a negative shift in V T, likely due to increased sheet carrier concentration consistent with what has been previously reported [28]. Also, we see an average of 3% DC to pulsed I d recovery after passivation, suggesting a slight reduction in current collapse. In general, current collapse after passivation occurs without decreasing sub-v T swing (It actually has dropped slightly from 89 to 87 mv/dec for the device considered here, as shown in Figure 4.7 (c,d)). From these observations along with 70

93 Drain current I d (ma/mm) Drain current I d (ma/mm) dc pulsed (V gs0, V ds0 ) = (0, 0) V 1 μs, 0.01% before passivation before passvation (I pulsed - I dc )/I pulsed = 13% 651 ma/mm 567 ma/mm S = 89 mv/dec (a) Drain to source voltage V ds 10 3 V 10 2 ds = 5 V (c) Gate to source voltage V gs (V) Drain current I d (ma/mm) Drain current I d (ma/mm) dc pulsed (V gs0, V ds0 ) = (0, 0) V 1 μs, 0.01% after passvation (I pulsed - I dc )/I pulsed = 10% 855 ma/mm 767 ma/mm Drain to source voltage V ds V ds = 5 V after passivation S = 87 mv/dec (b) (d) Gate to source voltage V gs (V) Figure 4.7: Analysis of surface trapping effects on sub-v T for wafer A. (a,b) Pulsed I d -V d, and (c,d) DC transfer curves, before and after Si 3 N 4 passivation. the analysis presented in this section we believe that the sub-v T characteristics of devices on wafer A are not dominated by electron trapping at the device surface, but instead by low D it and an insulating buffer enabled at least in part by well-distributed Fe compensation doping Small signal frequency response We measured S-parameters for all devices over a frequency range of 1 to 41 GHz to determine unity current gain cutoff (f t ) and maximum oscillation (f max ) frequencies, using measurement, pad de-embedding, and extraction techniques described in 71

94 Gain (db) h 21 MUG l g = 220 nm f t = 51 GHz f max = 115 GHz Stability factor K Frequency (Hz) Figure 4.8: Pad de-embedded current gain ( h 21 ), maximum unilateral power gain ( MUG ), and stability factor (K) for 220 nm HEMTs on wafer A with 24 nm (AlGaN + AlN) barrier. 0.0 Appendix B. Biasing these 0.22 µm HEMTs for maximum current gain at 5 GHz [(V gs, V ds ) = (-3.5, 10) V] the devices displayed average (f t, f max ) = (46, 102) GHz, and the frequency response of a typical device is shown in Figure 4.8. These devices are not passivated, and for later comparison the average f t l g product for these baseline, non-capped devices is 10.1 GHz-µm. 4.4 Recessed-gate HEMTs: 1st generation In Section 4.5 we discuss device scaling on wafer C, which was grown in an MOCVD run adjacent to wafer A but includes a GaN cap layer. In this section we present preliminary recessed-gate HEMTs built on wafer D, grown serially adjacent to wafer B, but on a sapphire substrate and with a GaN cap. 72

95 Figure 4.9: SEM images of first generation wafer D devices after gate recessing for (a,b) 260 nm, and (c) 125 nm recessed lines. GaN is etched by a nominal 10 nm. The scale lines are of length 2 µm for (a), and 500 nm for (b) and (c). These first-generation recessed-gate HEMTs were fabricated using the process flow of Figure 4.2, omitting the ohmic recess, recess anneal, and oxide strip steps. These devices gates were formed with bilayer e-beam resist, so that the entire gate cap rests upon the oxide layer different from the three-tiered gate profile implied by step 10 in Figure 4.2 (which is used for second generation recessed devices). Also the overlay oxide removal and metallization step was carried out following gate recessing. Channels of length 125 and 260 nm were fabricated, recessing in fully-selective plasma mode such that only the 10 nm GaN cap layer was removed, leaving the full nm AlGaN+AlN thickness. Attempts at defining sub-100 nm channels failed due to poor e-beam focusing, as at the time of this process run we had not yet developed the TSF strategy of Section DC analysis Ohmic contact resistance for these devices was measured by TLM to be 0.87±0.08 Ω-mm and the extracted sheet resistance was 479 ± 33 Ω/. DC curves are shown in 73

96 Figure For the I d -V ds curves the gate was stepped from -6 V to 1 V for 125 nm devices and from -4 V to 1 V for 260 nm devices, and data is shown for all working devices of each l g. I dss for these devices defined as maximum current at zero gate bias was low, due to high source resistance R s but increased from 490 ma/mm to 573 ma/mm when decreasing the gate length due to increased v e in the channel. Estimating R s coarsely by adding the access resistance from half of the 3.5 µm sourcedrain gap to the contact resistance for a 100 µm-wide device gives a value of 16.3 Ω, and this high R s dominates much of the extrinsic device performance. The slope of the linear region is the same for the two gate lengths suggesting a negligible increase in access resistances for the shorter gates. The transfer curves of Figure 4.10 (b) and (d) show an average maximum transconductance of around 200 ms/mm for both gate lengths at a drain bias of 6 V, suggesting no loss of channel modulation ability when shortening the gates. It is interesting to note that intrinsic transconductance g m0, according to Equation 1.3, is near 300 ms/mm. Reducing l g from 260 to 125 nm reduces V T by 61 mv (29%), consistent with the increase in drain current. Over the 1 cm 2 wafer piece on which the devices were prepared, V T uniformity was excellent for 260 nm devices with a standard deviation of 75 mv (4%) compared to 280 mv (10%) for 125 nm devices. This difference points to non-uniform focusing of the e-beam during gate footprint writing (as TSF was not applied here) which is most evident for short gate lengths. Pinch off performance for these recessed devices was good when compared with typical published reports for recessed-gate AlGaN/GaN HEMTs [48, 113, 114]. Several 260 nm devices off-state drain current was less than 0.01 ma/mm at V ds = 6 V, and even for 125 nm channel devices I OF F was less than the 1 ma/mm gate-drain breakdown criteria. Several devices did show high I OF F, 74

97 Drain current I d (A/mm) Drain current I d (A/mm) Drain to source voltagev ds (V) l g = 125 nm -6 < V gs < 1 V l g = 260 nm -4 < V gs < 1 V I dss = 0.57 A/mm I dss = 0.49 A/mm (a) (c) Drain to source voltagev ds (V) Drain current I d (A/mm) Drain current I d (A/mm) (b) g m = 201 ms/mm l 0.1 g = 125 nm V 25 ds = 6 V V t = V Gate to source voltagev gs (V) (d) g m = 199 ms/mm l 0.1 g = 260 nm 25 V ds = 6 V V t = V Gate to source voltagev gs (V) Transconductance g m (ms/mm) Transconductance g m (ms/mm) Figure 4.10: (a,c) I d -V ds and (b,d) transfer curves for recessed-gate HEMTs for 260 and 125 nm devices. The insets in (b) and (d) are I d -V gs on a semilog scale using the same units as the primary plot. which is due to large I g. It is not likely that contact between the gate trunk and the heavily-doped cap layer is responsible for high leakage since our measurements have indicated that this layer is fully depleted under normal operating conditions as shown in Section Possible explanations for high I g include nonuniformities in oxide quality and surface or mesa edge resist residue. Measures are taken for second generation devices to help ensure better resist cleanup after etching steps. 75

98 4.4.2 Small signal frequency response From S-parameter measurements we obtained, at (V gs, V ds ) = (-1.5, 5.6) and (-2.2, 4.8) V for 260 and 125 nm devices, respectively, typical (f t, f max ) values of (39, 62) and (42, 62) GHz, respectively. The f t l g product for 260 nm devices is 10.1 GHz-µm The devices become unconditionally stable at 20.0 and 21.5 GHz for 260 and 125 nm channels, and it is from this frequency that we extrapolate from the maximum unilateral power gain ( MUG ) at -20 db/dec to estimate f max. Although increases in f t and f max with decreased gate length was expected, these figures of merit were significantly lower than expected. For more desirable values of R c = 0.5 Ω-mm and ρ s = 300 Ω/, and no change in gate capacitance, we would expect an increased g m leading to a subtle increase in f t from 43 and 48 GHz. The small-signal performance is dominated by parasitics, as suggested by identical f max for each channel length. High extrinsic gate capacitance plays a major role in reducing f t and f max. As mentioned earlier the gate metal was defined by a bilayer e-beam process such that the full cap length rested upon the oxide. The final gate cap length was 1 µm, longer than intended due to over-development, and quick calculations indicate that if the cap length is reduced to 500 nm f t should increase by 26%. Measures are taken in the design of second generation recessed devices to reduce the parasitic resistance and capacitance that was present in these HEMTs for improved small-signal frequency response Dynamic I-V Pulsed and DC I d -V ds curves for typical 125 and 260 nm devices are shown in Figure At 7 V drain and 0 V gate bias the collapsed I d is 20-24% lower than 76

99 35 30 open symbols: 260 nm solid symbols: 125 nm 2.0 Gain (db) h 21 MUG Stability factor, K GHz 62 GHz 42 GHz Frequency (Hz) Figure 4.11: Pad de-embedded current gain ( h 21 ), maximum unilateral power gain ( MUG ), and stability factor (K) for typical 125 and 260 nm recessed-gate HEMTs on wafer D. f t and f max values are indicated along the f axis, where f max for both l g s is 62 GHz. when pulsing from QB0, or (V gs, V ds ) = (0, 0) V. When pulsing from a pinchedoff quiescent point (QB2) the drain current still exceeds or matches the DC current for low I d and high V ds. By applying high V gd with the QB2 condition we attempt to set up a surface trap frozen state, where electron traps near the drain-side gate edge are filled causing a temporal lag in channel recovery when the gate is pulsed positively. We do not see the expected collapse in QB2 current, suggesting that surface trapping effects are minor or negligible for these devices. We conclude that electrical field plating from the 1 µm long gate caps have nearly eliminated surface trapping effects, and the negative slope in the DC characteristic for high V ds is caused essentially by channel heating effects. The surface oxide layer and/or the GaN cap 77

100 Drain current I ds (A/mm) l g = 260 nm -4 < V gs < 1 dc QB0 QB2 20% (a) Drain current I ds (A/mm) l g = 125 nm -5 < V gs < 1 dc QB0 QB2 24% (b) QB2 0.0QB Drain to source voltage V ds (V) QB2 0.0QB Drain to source voltage V ds (V) Figure 4.12: Dynamic I d -V ds for typical (a) 125 and (b) 260 nm recessed devices. The quiescent bias point QB0 corresponds to (V gs, V ds ) = (0, 0) V for both channel lengths, and QB2 is defined as (V gs, V ds ) = (-5, 7) V and (-4, 7) V for 125 and 260 nm devices, respectively. The pulse width and duty cycle is 0.2 µs and 0.01%. likely have a secondary effect in passivating surface traps and/or screening surface potential variations from the channel RF power measurements The 1 µm long gate caps of these first generation recessed gate HEMTs provide electrical field plating toward the source and drain sides of the devices. Although field plates increase gate capacitance and severely limit small signal gain, as shown in Section 4.4.2, we expect such gate cross sections, particularly the cap extension toward the drain, to benefit the breakdown voltage and RF power performance of these devices. We evaluate RF power performance as follows (refer to Appendix B): After fully calibrating our load pull test bench built around computer-controlled mechanical tuners and WinPower measurement software (Focus Microwaves) we first bias our device in class A/B operation (I ds 120 ma/mm), and then sweep source 78

101 and load tuner positions iteratively to converge on input and output impedances matched to the device. In an impedance-matched environment we then measure and calculate large signal transducer gain (G T ), output power (P out ), and power-added efficiency (PAE) as a function of power delivered to the input of the device (P in ). We measure at X-band (10 GHz), a frequency range commonly used for radar and satellite communications. As shown in Figure 4.13, for one of our 125 nm devices biased at V ds = 28 V and I ds = 127 ma/mm we achieve a maximum PAE of 51% and associated output power and power gain of 4.8 W/mm and 6.2 db. The DC gate current during this measurement did not exceed 1 ma/mm, an indication of the good breakdown behavior the field plate structure buys us. This performance compares well with reports in the literature at this operation frequency, and with an f t of only 42 GHz this demonstrates the trade-off between frequency response and breakdown (power) performance for field-plated HEMTs at microwave frequencies. 4.5 Systematically scaled recessed-gate HEMTs: 2nd generation We built second generation devices on wafer C to explore geometrical scaling behavior by varying channel aspect ratio l g /d, where d is the gate to channel distance. Variations of our Cl 2 /N 2 /O 2 zero-bias ICP-RIE etch process were used for gate recessing General process updates Through analysis of first generation capped and recessed devices, and through extensive process development efforts in the interim, we made many improvements to our recessed gate GaN HEMT process. 79

102 Output power P out (dbm), Transducer gain G T (db) f = 10 GHz V ds = 28 V P out PAE G T 4.8 W/mm 51 % 6.2 db Input power (dbm) Power added effeciency PAE (%) Figure 4.13: X-band power performance of a recessed 125 nm channel device on wafer D. At V ds = 28 V we achieve maximum PAE of 51% with associated output power and gain of 4.8 W/mm and 6.2 db. E-beam CD control One of the strategies we considered in efforts to achieve minimal gate CDs was an oxide-first process, wherein dielectric was deposited on the wafer as the first fabrication step. Although the intention was to provide a planar surface for improved CD control during gate footprint EBL, and to prevent the semiconductor surface from being exposed to many process steps, this approach was discarded due to ohmic contact incompatibility. It was necessary that oxide reside between source and drain electrodes during ohmic annealing, and we found that the oxide became conductive due to lateral metal diffusion, effectively shorting the device. In addition to huge improvements later realized by employing the TSF technique, we further improved CD uniformity in our gate EBL processes by performing dose arrays on test devices with mesa and ohmic layers complete rather than on planar material 80

103 so that resist thickness nonuniformities and backscattering effects were identical to those experienced on real devices. Resist cleanup Those involved in semiconductor device processing know that complete removal of photoresist and e-beam resist after patterning steps can be critical as well as challenging. For second generation recessed devices we employed several measures to both prevent stubborn resist residues from forming as well as to facilitate easier residue cleanup. First, we swapped the order of fiducial and mesa steps. Traditionally we would first define metal fiducial alignment patterns and align subsequent layers, including mesa, to this layer. Mesa isolation is done with plasma etching, which can cause severe crosslinking and general heat damage to resist at feature (mesa) edges, leaving residues that can be removed only with aggressive chemicals, high temperature, and/or mechanical force which can damage existing metal layers. Completing mesa isolation first allows use to aggressively remove residues from mesa edges without damaging metal fiducial patterns, as they are not defined until after the mesa layer. Another adjustment for mitigation of the resist residue problem performing the probing pad overlay lithography and metallization before gate recessing. This was done to reduce the number of times that the active device area, sometimes defined in sub-50 nm oxide trenches, was covered with resist. Resist used during the final gate metal e-beam step could not be avoided. Typically we would expose source and drain overlay metal patterns at the same time as gate metal, but we found that electron scattering effects from overlay exposure prohibited us from defining T-gates below 120 nm. With overlay metal already in place we could perform gate-only exposure, which enabled more-deeply scaled l g s. 81

104 For second generation devices we formed T-gates upon recessed lines using a trilayer e-beam resist process, different from the bilayer approach used for first generation devices. This still allowed a gate cross section with long cap (to minimize R g ) but with a relatively shorter metal cross section contacting the oxide surface for lower fringing capacitance. Such a profile is depicted in step 10 of the process flow shown in Figure 4.2. With a shorter contact length between gate metal and oxide we could use a thinner (50 nm, compared with 100 nm) oxide film without a large increase in associated fringing capacitance from the second tier gate extension in contact with the oxide. Also, for second generation devices we did post-recess annealing for 10 min at 400 C in N 2 ambient, which showed slight improvements in RF performance compared with non-annealed devices. This process is believed to help recover plasmainduced surface damage [115]. Following the gate metal step we etched the oxide layer in buffered hydrofluoric acid (BHF) leaving free-standing T-gates for reduced fringing capacitance. This process was found not to etch ohmic or gate metal Recessed ohmic contacts The high (0.87 Ω-mm) ohmic contact resistance for first generation devices is largely due to an increased Schottky barrier height at the n + -GaN/AlGaN heterointerface compared to the non-capped case, arising from the negative polarization charge here. This effect is illustrated in the energy band diagram shown in Figure 1.6 (b), where in this calculation the effective barrier height increases from 1.7 ev to 3 ev. By reducing the cap layer thickness from 10 to 5 nm we have not only reduced the sheet resistance in the HEMT access regions, but we have also lowered this Schottky barrier. We found that by removing the cap layer completely in the ohmic regions 82

105 we could achieve much lower and more uniform ohmic contact resistance. Benefits of ohmic contact recessing had been demonstrated previously for GaN-capped and non-capped AlGaN/GaN HEMTs [41, 40]. When developing such a process one must achieve an optimal balance between reduced Schottky barrier (and reduced barrier thickness for tunneling) and 2DEG density in the etched area. We carried out a TLM study wherein Ti/Al/Mo/Au ohmic contact resistance to wafer C was be measured as a function of SiCl 4 RIE recessing in the ohmic area - in investigation similar to earlier work we did for Cu-Ge ohmic contacts [36, 39, 86]. For the case of thick film n-gan (not HEMT material) we had previously found that 300 V plasma bias induces optimal electrical damage and corresponding surface energy band bending to provide minimal contact resistance to n-gan. The ohmic contact mechanism for AlGaN/GaN HEMT layers is different from the thick film GaN case, as we strive to contact a buried channel. Because of this we have observed that it is more critical when plasma etching to optimize the barrier thickness rather than the surface chemistry for optimal contact resistance. The results of the experiment, done using wafer D, are summarized in Figure We considered two RIE biases for our SiCl 4 etching process 109 and 214 V and as shown in the etch trends of Figure 4.14 (a) the 109 V process gave a more reasonable etch rate for removal of up to 20 nm of material. As with many of our (Al)GaN etch processes we begin with a BCl 3 plasma step to remove a few nanometers of native oxide, eliminating etch dead time at the commencement of the etch. A 15 W deoxidation step was chosen to remove 4 nm of material. In Figure 4.14 (b) we show trends of specific contact resistivity (ρ c ) and R c with respect to recess depth (measured by AFM) and we see that removing the GaN cap and etching slightly into the AlGaN layer gives the lowest contact resistance 83

106 which is less than half that of the non-recessed case. The inset shows annealing temperature dependence on R c for ohmic contacts etched nm into the AlGaN. This process, where the etching is self-aligned to the ohmic metallization, was used for second generation GaN (5 nm)-capped devices to achieve R c = 0.48 ± 0.06 Ω-mm Recess design and implementation Variation of both gate length and recess depth was necessary to achieve a wide range of channel aspect ratios (l g /d). To isolate the effects of gate recessing, all device samples underwent parallel identical process steps, through SiO x gate footprint etching, prior to the gate recess operation. To achieve high l g /d we etched many devices through the GaN cap and into the AlGaN layer, and to maintain precise etch depth control we used a two-step recess. The first step was a fully GaN-over-AlGaN selective 25% oxygen Cl 2 /N 2 /O 2 ICP process. The coil power was reduced from 3 kw as used to clear the 10 nm cap of wafer D, to 2.5 kw to give an etch rate of 1.7 nm/min through the 5 nm thick n + -GaN cap of wafer C. After a 10% cap over etch we proceeded into the AlGaN layer at 0.9 nm/min by reducing the O 2 mol fraction in the plasma to 10% and increasing the coil power to 3 kw. The etch rates cited above were confirmed by etching gate footprints on pilot device samples, and were reproduced on actual devices with sub-nm accuracy. Before deciding how deeply to etch we modeled the barrier thickness dependence on threshold voltage. Threshold voltage modeling In Section we showed that pinch off voltage (approximately equal to V T ) could be increased by several volts using an 18 min fully GaN/AlGaN selective zero-bias recess etch on Schottky diodes. At this point in our work we model the dependence of 84

107 Etch depth (nm) ρ c (10-6 Ω-cm 2 ) Etch duration (s) (a) (b) n + -GaN 109V/20Wdeox, y = 2.13x V/20Wdeox, y = 10.8x V/15Wdeox, y = 1.66x V/15Wdeox, y = 11.0x AlGaN Ohmic recess depth (nm) Rc (Ω-mm) Figure 4.14: Summary of n + -GaN/AlGaN/GaN recessed Mo/Al/Mo/Au ohmic development. (a) Etch process trends using two plasma biases and two deoxidation conditions. The circled recipe was used in (b), which shows dependencies of specific contact resistivity and contact resistance on AFM-measured recess depth. The inset of (b) shows annealing temperature dependence on R c for 12 nm-etched ohmics. 85

108 V T on gate recessing depth to help direct our device design, where this time we adjust the process to controllably etch into the AlGaN layer. Since in our study we employ GaN HEMT structures with 1 nm AlN at the AlGaN/GaN interface to improve 2DEG confinement, our V T model includes an effective AlGaN/GaN conduction band discontinuity of 0.78 ev, a value that had been measured directly by electron holography in reference [116]. Subsequently ignoring the AlN interlayer we approximate the threshold voltage for a (GaN/)AlGaN/GaN HEMT with unintentionally-doped layers as V T = φ eff b dσ ɛɛ 0 φ eff c φ F 0 (4.4) where the dielectric constants ɛ of GaN and AlGaN are assumed equivalent. σ and d are the total polarization charge ( cm 3 for 30% AlN [11]) near the Al- GaN/GaN interface and the AlGaN barrier thickness. From left to right, the terms represent the effective Schottky barrier height, polarization potential across the Al- GaN barrier, AlGaN-GaN conduction band discontinuity, and equilibrium Fermi potential with respect to the GaN conduction band edge at the AlGaN/GaN interface. The expression is modified from that given in reference [117] for the AlGaAs/GaAs system by including the polarization term and omitting depletion potential terms (assuming full depletion of barrier and cap layers at thermal equilibrium as confirmed in Section 3.2.3). φ F 0 is related to channel density by [118] φ F 0 = k 1 + k 2 ns + k 3 n s (4.5) 86

109 where the first two sub-bands in a triangular well are considered, and k 1 3 are constants for three device operation regimes. To calibrate the model we use n s = cm 3 extracted from 3.85 min etched Schottky diodes from Section 3.2.3, assuming this channel density exists after just removing the GaN cap layer. Then, we calculate V T as a function of AlGaN barrier thickness per Equation 4.4, changing φ eff b to force the trend to intersect with three values of pinch off voltage as extracted for recessed Schottky diodes -5.08, -3.31, and V all for 24 nm barrier thickness as fullyselective GaN-over-AlGaN etching mode was used. The result shown in Figure 4.15, where φ eff b of 3.21, 4.84, and 6.48 ev are used as fitting parameters. These large Schottky barrier heights may be reasonable when considering that the AlGaN surface is oxidized during recess etching. Depending on the extent of surface oxidation after etching AlGaN in moderately selective mode, as opposed to the fully selective mode used in Sections and 4.4, the required remaining barrier thickness for enhancement-mode operation likely lies somewhere between 6 and 18 nm. This large uncertainty leads us to choose a conservative value of 11 nm to help ensure E-mode operation without high risk of over-etching the barrier. Etch depth verification We attempted three nominal recess depths 10, 18, and 25 nm to achieve barrier thicknesses of 29 (non-recessed), 19, and 11 nm. Example AFM step height data for the three recess depths are shown in Figure These measurements were made after recess etching followed by a BOE field oxide strip. The nominally non-recessed profile is shown in Figure 4.16 (a), where an average step height of 12.8 nm was measured. Ideally we would have measured no step for non-recessed devices, and we believe that the observed step is due to plasma hardening of the resist and related chemical 87

110 Threshold voltage V T (V) V T = φ eff b dσ Δφ εε eff φ b Barrier thickness d (nm) 0 (ev) eff C φ F min 6 min 18 min Figure 4.15: Modeled threshold voltage versus AlGaN barrier thickness for three Schottky barrier heights, selected such that the model coincides with three pinch off voltages measured from Schottky diodes etched for three durations. Barrier thickness for the data points is constant since fully-selective etching was used during the recesssing of these diodes. Depending on the extent of surface oxidation after removal of AlGaN during moderately-selective etching, we may expect the required barrier thickness for E-mode operation to be between 6 and 18 nm. 88

111 Figure 4.16: Example AFM step height measurement result after (gate recess and) field oxide etch. (a) Non-recessed, (b) 10.4 nm recessed, and (c) 18 nm recessed. Average step heights were calculated over three devices of each etch depth. Values have been corrected for actual semiconductor etching since the raw step height includes a 12.8 nm oxide and sidewall resist-related layer. The shoulder at the base of the etch trenches is a measurement artifact caused by the finite diameter of the AFM scanning tip, which limits lateral resolution. modification of remaining oxide. We do not believe that the CHF 3 /O 2 footprint oxide etch step removed any semiconductor material, as GaN/oxide selectivity better than 20 had been previously observed for this process. We have therefore corrected the three AFM etch depth profiles by this 12.8 nm offset, giving recess depths of 0, 10.4 and 18 nm. We should mention that working 11 nm barrier devices presented later were etched using the same process as that used in Figure 4.16 (c), and had the barrier been etched by 31 nm the devices would have not worked. To help ensure sufficient alignment of gate metal lithography to gate recess, the T-gate cap length was designed to extend by 150 nm in each direction past the recess giving an alignment tolerance of 150 nm. SEM images of typical gate profiles are shown in Figure 4.17 before (a) and after (b-g) field oxide etching by BOE. The gate recess process etches GaN much more rapidly than AlGaN, and this selectivity, along 89

112 with the isotropy resulting from zero plasma bias, can create an undercut profile beneath the oxide in the off-mesa region where the AlGaN layer had been removed during the earlier mesa isolation step. The undercut profile disappears for l g < 100 nm. Key challenges facing our short gate device yield are 1) gate metal-to-recess e-beam alignment, and 2) mechanical instability of gates with large l cap /l g ratios [see Figure 4.17 (e-g)]. The fact that sub-50 nm gates were not lost during the BOE field oxide etch step indicates that the oxide in the gate area was completely removed during the CHF 3 /O 2 footprint oxide etch step, and that the gates do not have SiO 2 beneath them DC analysis DC measurements for three barrier thicknesses and constant l g = 800 nm, are summarized in Figure In both the transfer curves of (a) and the family I-V s of (b) we see a dramatic increase of channel control with decreasing d. Even for 800 nm-long devices we cannot control the channel well with the non-recessed n + -GaN capped structure due to gate potential screening as discussed in Section 1.5, and even short channel effects including high output conductance g ds and poor pinch off in the I d -V d curves are observed. I g -V gds, also at V ds = 6 V and with current normalized to device width, is shown for each device in the inset of Figure 4.18 (a). None of the devices gate-drain diodes has broken down over this measurement range (using the criteria I g = 1 ma/mm), and the gate current level for each is similar. This indicates that recessing has not increased gate leakage beyond that due to other possible leakage sources independent from the gate Schottky interface. We achieved high DC g m with deeply-recessed devices 334 ms/mm for an 800 nm HEMT with 11 nm barrier 90

113 Figure 4.17: SEM images of scaled recessed GaN/AlGaN/GaN HEMT gates (a) before and (b-g) after field oxide etching by BOE. We see an undercut etch off of the device mesa where the AlGaN layer has been removed, due to etch isotropy and higher etch rate of GaN compared to AlGaN for the selective recess etch process. Measured gate lengths are (a-b) 829 nm, (c) 747 nm, (d) 377 nm, (e) 168 nm, (f) 68 nm, and (g) 29 nm. 91