Final Report. Contract Number Title of Research Principal Investigator

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1 Final Report Contract Number Title of Research Principal Investigator Organization N AIGaN/GaN HEMTs on semi-insulating GaN substrates by MOCVD and MBE Dr Umesh Mishra University of California, Santa Barbara

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3 Abstract Silicon (Si) implantation into AIGaN/GaN high electron mobility transistors (HEMTs) has been studied in this program as a method to reduce the sharp increase in the dynamic source resistance at increasing current levels that result in a reduction both in the transconductance g m and the current gain cut-off frequency fj. During the program two different approaches have been investigated to decrease the electric field in the source access region. To prevent breakdown between source and gate, different barrier layers have been investigated. Ultimately, these barriers allow an overlap between the gate and the source implant region. First, a regrown AIGaN/GaN channel as the barrier between the source implant region and the gate has been investigated. In the past, silicon has been found to create a buried parasitic layer conductive path at the re-grown interface. In this work, multiple-cycle treatment with hydrofluoric acid and ozone was used to reduce the silicon at the regrowth interface by 80%. Second, using silicon nitride (SiN) as the barrier layer between the implanted source region and the gate allowed a regrowth free structure. MOCVD grown SiN was deposited in situ after the activation anneal of the implanted silicon. With channels lengths down to 0.3 jam and gate lengths of 200 nm, these devices exhibited constant dynamic source resistances which improved the transconductance linearity at high current levels significantly.

4 Contract Information Contract Number Title of Research Principal Investigator Organization N AIGaN/GaN HEMTs on semi-insulating GaN substrates by MOCVD and MBE Dr Umesh Mishra University of California, Santa Barbara Introduction AIGaN/GaN HEMTs have demonstrated record power densities at microwave operation [1]. However, these devices usually exhibit a fast decrease in current gain cut-off frequency fr. Most of the decrease in fj can be attributed to the decrease of g m at high currents. This decrease can be explained by the increase of the small signal source access resistance, r s, with drain current. Since the electron velocity varies with the electric field, a decrease in the electron mobility for high fields is most likely the reason for this increase of access resistance [2]. Sample A col o c I 1 o ; 1 is q> 100 nm Sample B Sample C 450 ATLAS Simulations 1 1 > 1 > 1 ' 1 > <-«300 _ E g (/) S E O) , Sample A: Std.HEMT Sample B: Source n* layer to Ihe gate Sample C: Source n* layer 100 nm from gale edge " V Rfi (V) Fig 1: Left: Proposed structures to increase the linearity of g m and f T. Right: Simulated g m profiles by ATLAS -

5 A g m linearity improvement can be achieved if the electric field at the source can be kept below its quasi saturation value (-10 kv/cm). ATLAS simulations have shown that an introduction of low resistivity areas between the source and the gate can improve the linearity (Fig 1), [2]. To create the structure Sample B in Fig. 1, ion implantation is a promising technology after excellent low sheet resistances as low as 14 Ohm/ Square have been demonstrated [3]. An important feature of this structure is the barrier layer that separates the gate from the implanted source region, avoiding high leakage current or even breakdown between the gate and source. In this program, two different approached have been investigated to form this barrier layer. The results are described in the following section.

6 Barrier layer by channel regrowth Figure 2 shows a schematic cross section of the AIGaN/GaN HEMT with buried implants. The barrier between the implanted source region and the gate consists of a regrown AIGaN/GaN channel. Source Gate Drain S AIGaN GaN Channel i+ GaN buffer Si + GaN:Fe Fig 2: AIGaN/GaN HEMT with buried Si- implants The process flow involves implanting highly doped source and drain regions into an insulating GaN substrate and then regrowing the GaN channel and AIGaN barrier layer. A significant challenge in this approach is the formation of a Si layer on the surface after removing the GaN substrate from the growth chamber (MBE and MOCVD) and preparing it for implantation. In a regrown HEMT structure, this Si layer forms a parasitic conductive leakage path parallel to the 2 DEG. To mitigate this effect, a cycled UV ozone treatment was employed. Prior to regrowth, the GaN buffer surface was exposed twice to a 5 min ozone treatment followed by 30 sec hydrofluoric acid (HF) dip. Ozone treatment enhances the oxidation of the Si layer. HF treatment then removes the formed oxide layer.

7 Figure 3 shows the DC IV curve of a regrown AIGaN/GaN structure with (a) no ozone treatment and (b) cycled ozone treatment before regrowth r V G = + 1V NoOzone Ozone g E 400 AV G = 1V V) Q 200 V. [V] DS Figure 3: DC l-v curve of regrown AIGaN/GaN HEMT (a) with ozone/hf treatment and (b) no treatment before regrowth. It can be observed that both devices do not pinch off. Nevertheless, a reduction in leakage current for the ozone treated sample is obvious. An 80% reduction of silicon concentration at the interface was observed. Although significant, this reduction was not sufficient for transistor applications. Further cycling of ozone and HF treatment did not completely remove the parasitic layer.

8 Buried Implant by metal insulator semiconductor heterostructure FET (MISHFET) The second approach under this program was the investigation of an AIGaN/GaN metal insulator semiconductor heterostructure FET (MISHFET) structure that allows the overlap of gate and implanted source region (Fig. 4). Figure 4: Schematic of an AIGaN/GaN metal insulator semiconductor heterostructure FET (MISHFET) Previously, ion implantation has been demonstrated to be an excellent choice to form contact resistances as low as 0.2 Qmm to HEMT structures [4]. Figure 4 shows a schematic of the MISHFET structure. Fabrication of the MISHFET started with deposition of a Si0 2 /Ti/Ni ion implantation mask with Ti/Ni removed in the source and drain regions (S/D) for implantation. Source to drain spacing was 0.4 am. Si ions at a dose of 1 * cm" 2 were implanted at 0 at 60 kev at room temperature. After the implantation mask was removed the sample was subject to an activation anneal for 30 sec at C in an MOCVD system flowing N 2 and NH3at atmospheric pressure (760 Torr). A 5 nm SiN layer was deposited in situ. The AIGaN layer was removed in the S/D regions using CI2 reactive ion etching (RIE) and ohmic

9 Ti/Au/Ni contacts were deposited onto the underlying implanted GaN. A contact resistance of 0.5 Qmm was obtained. Ni/Au/Ni gates were formed by ebeam lithography (300 nm). The overlap between the implanted source region and the gate was 100 nm. SD121408A-D R7C3T28 AV = 0.5V v = ov SD12H08A-DR7C2T28 E E 5-1 I i L_ Figure 5: Left: DC-IV curve; Right: g m -l D curve of 0.4 nm channel MISHFET Figure 5 left depicts the DC IV curve with a maximum drain current of 1.5 A/mm at a drain bias of V D s=3.6 V. Figure 5 right shows g m and l D versus gate voltage. The device exhibits a maximum transconductance of 350 ms/mm and the drop of g m at high current is minimal. SD121408A-D R7C2T28 V«M Figure 6: Current-gain cutoff frequency f T versus gate voltage

10 Figure 6 shows fj versus gate voltage. The sharp drop in g m and f T as described by Palacios et al. [2] is not observed. References: [1] Y.F. Wu, A. Saxler, M. Moore, R.P. Smith, S. Sheppard, P.M. Chavarkar, T. Wisleder, U.K. Mishra, and P.Parikh, "30 W/mm GaN HEMTs by field plate optimization," IEEE Electron Dev Lett, vol. 25, no. 2, pp , Feb 2004 [2] T. Palacios, S. Rajan, A. Chakraborty, S. Heikman, S. Keller, S.P. DenBaars, U.K. Mishra, "Influence of the Dynamic Access Resistance in the g m and f T Linearity of AIGaN/GaN HEMTs," IEEE Trans. Elect. Dev, vol 52, no 10, pp , Oct 2005 [3] H. Yu, L. McCarthy, S. Rajan, S. Keller, S. DenBaars, J. Speck, U. Mishra," Ion Implanted AIGaN/GaN HEMTs With Nonalloyed Ohmic Contacts," IEEE Elect Dev Lett, vol 26, no 5, pp , May 2005 [4] F.Recht, L. McCarthy, L. Shen, C. Poblenz, A.Corrion, J.S. Speck, U.K. Mishra, "AIGaN/GaN HEMTs with large angle Implanted Nonalloyed Ohmic Contacts," 65th Device Research Conference, South Bend, IN, 2007

11 Dear Sir or Madam, Please find attached the final report for N (UC Santa Barbara, Prof. Mishra). I apologize for the delay. Best Regards, TtcLf Felix Recht ECE Dept UC Santa Barbara Santa Barbara, CA recht@ece.ucsb.edu