MITLL Low-Power FDSOI CMOS Process

Transcription

1 MITLL Low-Power FDSOI CMOS Process Application Notes Revision 2006:1 (June 2006)

2 2006 by MIT Lincoln Laboratory. All rights reserved. This work was sponsored by the United States Air Force under Air Force Contract #F C Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

3 CONTENTS CONTENTS 2D FDSOI Design... 5 Introduction... 5 Mesa Isolation... 5 Silicided Poly and Active Features... 6 Floating MOS Body Effects... 7 Chemical-Mechanical Polishing... 7 Standard NMOS and PMOS Devices... 8 Standard NMOS Devices... 8 Dog Bone Transistors... 9 NMOS and PMOS Body Implant Surrounds...10 Edge Effects Layout Post-processing for Sidewall Implants Effect of Floating Body on Drain Current Effect of Floating Body on Noise Special Purpose MOS Structures Edgeless Annular Devices Source-Side Body Contacted Devices H-Gate Devices Abutting Devices Conductive Lines Dense Contacts and Vias Diodes Linear Capacitors Resistors Resistor Devices and the DEVR Layer Inductor Devices and the DEVL Layer Active, Poly and Metal Fill Patterns Automatic Generation of Fill Patterns by MITLL Antenna Effects and the Metal Z Layer RF Transistor Layout Suggestions D FDSOI Design Introduction D Circuit Integration D Design Practices D Layout Orientation Thermal Management Considerations Contact Information Revision History Rev.: 2006:1 (Jun 06) 3

4 This page intentionally left blank

5 Introduction The MITLL 0.18-µ m low-power FDSOI CMOS process offers many advantages over bulk CMOS, including full dielectric device isolation, high packing density, reduced parasitic junction capacitances, and improved subthreshold slope. Certain features of the process, however, can present challenges for the circuit designer. Mesa isolation, silicided active and polysilicon features, floating MOS body effects, and chemical-mechanical polishing (CMP) effects all contribute to circuit performance. Here, the effects of these features on device layout are discussed, and design examples are presented that respond to the challenges. Several new process variations have been added since the RF07 and 3DL1 reticle sets. Some versions of the process allow suppression of silicide growth by masking the etch of the Si 3 N 4 spacer using the NOSLC layer. Another option is a separate pair of reticles for source and drain extensions (SNX and SPX), distinct from the pair of reticles for source and drain degenerate implants (SN and SP). To access the geometries on these reticles, a designer should draw NSD or PSD in conjunction with either NOSDX or NODEG. The NOSDX and NODEG will suppress the extension and degenerate implants, respectively. Throughout these notes, values for particular process parameters are mentioned, some of which depend on the particular process version that is implemented. Hence, when seeking the exact value for a particular process parameter, it is always advisable to refer to the appropriate process parameter table in MITLL Low- Power FDSOI CMOS Process: Design Guide. Numbers in these notes are intended to ensure that a correct order of magnitude is associated with qualitative comments. While every attempt is made to use actual process parameter values in the examples, exact specifications are not guaranteed. The drawings do not necessarily reflect minimum rules, and they may contain some rule violations Mesa Isolation In the 0.18-µ m low-power FDSOI CMOS process, devices are mesa isolated. Hence, each active region consists of a 40-nm silicon island. With any device layout, it is important to consider the effect of the island edge on device performance. While not a concern for many digital designs, edge effects can contribute to noise and may significantly alter subthreshold device characteristics. Such effects are discussed in detail here. Layout options for edgeless devices are also presented. Rev.: 2006:1 (Jun 06) 5

6 1.3. Silicided Poly and Active Features Following polysilicon definition, all exposed polysilicon and active regions not protected with NOSLC are silicided. This silicide layer has a sheet resistance on the order of Ω/sq. As a result, all silicided undoped poly and active features become conductive. In addition, any exposed diodes resulting from abutment of opposite implants will be shorted by the silicide layer. This situation is illustrated in Fig Silicide NSD PSD Figure 1-1: NSD-PSD diode shorted by silicide. Shunting of such a diode can be avoided by use of NOSLC in some versions of the process. The designer should be aware that NOSLC blocks the source and drain implants but does not block the extension implants. Such devices will be discussed under Special Purpose MOS Structures. The shunting of the diode illustrated in Fig. 1-1 is not perfect. Chains of thousands of such shunted diodes tend to be open. We strongly recommend that, wherever possible, a width greater than the minimum be used for such transitions. Similarly, the transition between n type and p type should not run lengthwise along a segment of poly. Transitions in poly dopant type were previously not allowed under contacts, but recent data show that such transitions do not cause failure in short-term tests. However, in cases in which reliability must be maximized, such transitions should be avoided. Long segments of undoped, minimum-dimension poly also are occasionally found to be open. Therefore, we strongly recommend that all poly be doped, and that long poly wires be wider than the minimum dimension. The preferred doping is p type (PSD layer), since it produces a somewhat lower silicide sheet resistance. 6 Rev.: 2006:1 (Jun 06)

7 1.4. Floating MOS Body Effects Unlike bulk CMOS devices, fully depleted SOI devices do not require body contacts. Thus, the body node is often left floating. In these cases, the floating body voltage is affected by diode current, impact ionization, GIDL, and capacitance displacement current. It is also possible to implement a body contact, in which case the body contact current also contributes to the body voltage. For body contacted devices, the body contact series resistance can be large, so floating body effects cannot be completely discounted. The impact of floating body effects on device characteristics and related design considerations are discussed in detail in the following notes. Several body contact layout options are presented Chemical-Mechanical Polishing Planarization of ILD layers can result in a layout-dependent dielectric thickness distribution. In some cases, this can cause wide variation in interconnect capacitance and may affect circuit yield. When polysilicon and metal features are evenly distributed across a wafer, this variation is minimized and the CMP process is better controlled. In order to reduce process variations, constraints have been placed on metal and poly pattern densities. Further details are presented in Section Rev.: 2006:1 (Jun 06) 7

8 1.6. Standard NMOS and PMOS Devices As in bulk CMOS, a MOS device is defined by the intersection of active and poly. In mesa-isolated SOI, the active area corresponds to a thin silicon island, which is doped with a threshold adjust implant CBN or CBP for an NMOS or PMOS device, respectively. The source and drain extension implants and the source and drain degenerate implants are both controlled using the NSD and PSD layers Standard NMOS Devices. Figure 1-2 shows the layout for a standard 0.6-µ m by 0.2-µ m NMOS device (etched poly length of 0.18 µ m). 0.1 µm Active Poly Contact CBN NSD Cut Figure 1-2: Standard NMOS device. W = 0.60 µ m, L = 0.20 µ m. 8 Rev.: 2006:1 (Jun 06)

9 Dog Bone Transistors. A minimum-geometry 0.5 µ m by 0.20 µ m dog bone transistor device is illustrated in Fig. 1-3, showing the dog bone shape of the active area. Rule 9.04 requires a µ m poly to active spacing. However, the bend in the poly must be placed µ m away from the gate region, as required by Rule Recent test results have shown transistor characteristics are not affected by moving the dog bone width transition closer to the gate. In Fig. 1-3, the distances corresponding to Rules 9.04 and 9.05 are at their minimum allowed values. For devices in which gate length control is especially important, the distance from gate extension poly to active should be increased. 0.1 µm Active Poly Contact CBN NSD Cut Figure 1-3: Dog bone NMOS device. W = 0.50 µm, L = 0.20 µ m. Rev.: 2006:1 (Jun 06) 9

10 NMOS and PMOS Body Implant Surrounds. Figure 1-4 shows a sample layout of a 0.6 µ m by 0.20 µ m PMOS device. Note that the CBP surround on the PMOS channel is the same as the CBN surround on the NMOS channel illustrated in Figs. 1-2 and 1-3. An attempt has been made to make the layout rules for the MITLL FDSOI process symmetric, with CBN rules corresponding to CBP rules, and NSD rules corresponding to PSD rules. 0.1 µm Active Poly Contact CBP PSD Cut Figure 1-4: PMOS device. W = 0.60 µ m, L = 0.20 µ m. 10 Rev.: 2006:1 (Jun 06)

11 Edge Effects. Since the MITLL FDSOI process is mesa isolated, the standard NMOS and PMOS devices illustrated in Figs. 1-2 through 1-4 each include parasitic MOS devices at the island edges. A schematic cross section of a typical parasitic edge device is shown in Fig These devices result in poor threshold voltage control. In addition, some tests have shown that edge devices may have substantially increased low-frequency noise. In the majority of MITLL FDSOI process versions, edge effects are minimized through the use of a sidewall implant. It is important for the designer to understand that post-processing of layout data will be performed in order to create the appropriate sidewall implant masks. Poly Gate Parasitic Edge Device Desired Device ISLAND Buried Oxide Parasitic Edge Device Figure 1-5: Cross section of parasitic edge device. In addition, it should be understood that edge effects can be completely eliminated by designing with devices that have no edge as drawn. See the section Special Purpose MOS Structures for more information on edgeless devices. Rev.: 2006:1 (Jun 06) 11

12 Layout Post-processing for Sidewall Implants. To avoid formation of parasitic edge transistors, layout data will be post-processed by MITLL to allow for sidewall implants. This operation will create the required sidewall implant mask layers and will adjust the size of active islands slightly to ensure that MOS channel widths correspond to drawn data. This post-processing is important for proper operation of MOS devices. Occasionally, a design requires the suppression of post-processing. This occurs most often when nonstandard devices such as depletion-type MOS transistors are used. The ACTXPP layer is provided to allow for such cases. This active island layer will receive no sidewall post-processing. For more information on the proper use of this layer in a design, please contact MITLL. A typical post-processed MOS layout is shown in Fig Note that the drawn active area has been oversized near the gate to form ACTEXP, and that sidewall implant regions defined by SWN have been generated. Also note that the device width is now determined by the boundaries created by the sidewall implants, and not by the island edge. The automatic generation algorithm and corresponding sidewall implant process are designed so that this diffusion-determined width of the device corresponds to the drawn active width. 0.1 µm Active Poly Contact Cut CBN ACTEXP (Defined Island) SWN (NMOS Sidewall Implant) Figure 1-6: Post-processed NMOS device. W = 0.60 µ m, L = 0.20 µ m. 12 Rev.: 2006:1 (Jun 06)

13 The generated layers ACTEXP and SWN are never drawn by the designer. These are generated by MITLL, and the rules for generation of these layers are determined by process-related trade-offs. Hence, the sidewall implant mask will not necessarily look like that shown in Fig The designer should keep in mind that postprocessing will be performed on the layout, and that further information on the specifics of the sidewall process is available from MITLL on a case-by-case basis. To eliminate edge effects, a number of possible edgeless device structures are suggested. These include the annular structure, the H-gate, and the source-side body contacted devices. Examples are presented in the section Special Purpose MOS Structures Effect of Floating Body on Drain Current. The floating body node of SOI MOS devices can be considered as the base of a parasitic bipolar transistor. At higher drain-source voltages, impact ionization current charges this node, resulting in the kink effect. Typical drain current characteristics are presented in MIT Low-Power FDSOI CMOS Process: Device Models. At room temperature, a good body contact eliminates the kink, as confirmed by tests of several H-gate and source-side body contacted device structures. In testing at cryogenic temperatures, however, the body contacts failed to eliminate the kink effect. Body contact designs are discussed in the section Special Purpose MOS Structures. It is strongly recommended that sensitive devices be biased below the kink region Effect of Floating Body on Noise. A large increase in device noise has been observed in the kink region. For this reason, it is recommended that noise-sensitive devices be biased below the kink Special Purpose MOS Structures Several special purpose MOS layouts are described in this section. In practice, an additional feature must be drawn on the FLGCHAN layer to identify the desired channel region for verification purposes. This has been omitted from the illustrations in this section. There are two reasons for these structures: edge effects and the floating body effect. Edge effects apply equally to transistors of all gate lengths. The floating body effect is more important for longer channels. For 180-nm gate length (0.2-µ m drawn length) the body of the transistor is more fully depleted than for long channels because of the depletion regions extending laterally from the source and drain. This increase in depletion nearly eliminates the kink effect for short-channel devices, in contrast to partially depleted SOI technologies. Rev.: 2006:1 (Jun 06) 13

14 Edgeless Annular Devices. Figure 1-7 shows an edgeless annular PMOS device. Edge effects are eliminated, resulting in better threshold control and lower noise. The electrical device width is slightly larger than the inside perimeter of the gate. It should be noted that sharp drawn corners are rounded and bloated by optical effects, changing the effective physical length and width. This effect is reduced in structures that do not have sharp corners. Matching of ring gate MOS devices has not been characterized. 0.1 µm Active Poly Contact Cut CBP PSD Metal 1 Figure 1-7: Edgeless PMOS device. W = µ m, L = 0.20 µ m. 14 Rev.: 2006:1 (Jun 06)

15 Source-Side Body Contacted Devices. The layout for an 8-µ m by 0.5-µ m source-side body contacted (SBC) PMOS device is illustrated in Fig On the source side of the device, PSD has been replaced with NSD in three sections to create body contacts. The diode formed between NSD and PSD regions is shorted by silicide. No metal contact to the body contact regions is required, as they are already shorted to the source. Since the body of every SBC device is shorted to the source by silicide, the device is asymmetric, and thus the source and drain cannot be exchanged µm Active Poly Contact Cut CBP PSD Metal 1 NSD Figure 1-8: Source-side body contacted PMOS device. W = 8.00 µ m, L = 0.50 µ m. For SBC devices at room temperature a body contact separation of 8 µ m effectively eliminates the DC kink at higher drain voltages, but at cryogenic temperatures these body contacts are not effective. Body contacts separated by less than 8 µ m have not been characterized. A minimum body contact width of 0.5 µ m is recommended. Body contact width and body contact spacing are defined in Fig Rev.: 2006:1 (Jun 06) 15

16 Body Contact Width Body Contact Spacing Active Poly Contact Cut CBP PSD Metal 1 NSD Figure 1-9: Definitions of body contact width and body contact spacing. Note that on the SBC device illustrated in Fig. 1-8 the body contact NSD implants overlap the gate by 0.15 µ m. This is slightly larger than the minimum overlap of 0.1 µ m specified by Rules and in MITLL Low-Power FDSOI CMOS Process: Design Guide. A sufficient overlap of the body contact implant is necessary to ensure that alignment error does not affect body contact function. By increasing the overlap on both sides slightly to a more conservative 0.15 µ m, yield may be increased. It is important to remember that device threshold is sensitive to gate doping, and local threshold variation can occur as a result of body contact implants. Care should be taken to ensure that matched transistors have identical regions of opposite-type poly doping. In SBC transistors the device width is determined by the body contact implant edges, dopant diffusion, and current spreading between source and drain. For the same source, drain, and body contact geometry the electrical width varies with gate length. This has not been characterized precisely, so if a particular ratio of transconductance of two devices is desired, appropriate provisions must be made by the designer. If current values are critical in a narrow SBC transistor, contact MITLL for further information. The SBC structure in Figs. 1-8 and 1-9 may be considered edgeless in strong inversion, where current is dominated by drift. In subthreshold, some small edge current contribution may occur. The amount of edge current contribution in the latter case may be strongly affected by gate length, body contact width, and alignment error. This behavior, however, is not well characterized. It is recommended, but not required, that the CBN or CBP body implant be drawn with a µ m surround on the intersection of poly and active rather than with a µ m surround on the channel region as specified in Rules 4.02 and This will help to ensure that the active edges bordering the body contact regions receive sidewall implants. Annular gate SBC devices and H-gate devices may also be used to ensure that the device is truly edgeless. For further information concerning the efficacy of a particular body contact geometry, please contact MITLL. 16 Rev.: 2006:1 (Jun 06)

17 H-Gate Devices. The layout for an 8-µ m by 0.5-µ m H-gate PMOS device is illustrated in Fig In this structure, poly lines are used to prevent the diodes between NSD and PSD regions from being shorted by silicide. Recent experimental results have led to a change in the design rule for these uprights of the H structure: Their width must be at least 0.3 µ m to avoid the possibility of overlap of the body contact onto the drain side due to misalignment. MITLL is presently conducting experiments on the overlap of source-drain and extension implants on the uprights µm Active Poly Contact Cut CBP PSD Metal 1 NSD Figure 1-10: H-gate body contacted PMOS device. W = µ m, L = 0.50 µ m. For narrow transistors, the T-shaped gate is a possible variation of the H-gate layout, which provides a body contact while maintaining device symmetry between the source and drain. A T-shaped gate is drawn with an H-gate like body contact on one edge of the channel, and a standard mesa edge on the other. Since the T-shaped gate device is only edgeless on one side, parasitic edge effects are present in this structure. The discussion of body contact effectiveness vs width and temperature for SBC devices applies as well to H- gate and T-shaped gate devices. In process versions that include the NOSLC layer, the extra gate capacitance of H-gate and T-gate devices can be reduced. NOSLC can be used to replace poly in the uprights of the H or T. The NOSLC structure must be wider than the equivalent poly because there are additional components in the misalignment error budget. MITLL is presently conducting experiments to determine the minimum width and the best overlap of the source-drain and extension implants onto the NOSLC. (Designers should remember that NOSLC blocks the source-drain implants but not the extension implants.) Rev.: 2006:1 (Jun 06) 17

18 Abutting Devices. Since all exposed active and poly surfaces are silicided following poly deposition, abutting devices of opposite types may be used to save area, as illustrated in Fig µm Active Poly Contact Cut CBP PSD NSD CBN Figure 1-11: Abutting NMOS and PMOS devices. W = 0.80 µ m, L = 0.25 µ m. In tests to date MITLL has seen no effect of such abutting active regions as long as they are at least 0.4 µ m from the channel. Yield of such devices, however, has not been characterized by testing large numbers, so their use entails some risk. 18 Rev.: 2006:1 (Jun 06)

19 Conductive Lines. Long minimum-width and minimum-gap conductive lines should be avoided unless necessitated by capacitance or density considerations. This applies to all metal and silicided silicon lines. If long, wide parallel lines are used, increased line spacing should be considered. It is strongly recommended that when silicided active or poly is used as a conductor, the feature should be doped with NSD or (preferably) PSD. While this is not essential to device operation, it reduces the risk that defects in the silicide will reduce circuit yield. A test device comprising a long wire of minimum-dimension, undoped poly has a high probability of being open, while doped wires of the same geometry are rarely open. PSD-doped silicided poly is preferred because its sheet resistance is lower and more reproducible. Even distribution of active, poly, and metal will reduce process variations and increase yield Dense Contacts and Vias. Closely spaced contacts and vias result in thinning of the dielectric through which they are etched during polishing of the tungsten plugs that fill the contacts or vias. Therefore, we strongly recommend increasing the separation between them above the minimum allowed values for arrays of more than a few contacts or vias. The following algorithm is implemented in the MITLL design rule checker: Create a temporary layer by resizing and merging the contacts or vias by one half the recommended spacing, for a count of 5 to 24, less µ m. Flag with a warning the regions where the temporary layer encloses five or more contacts or vias. Repeat the above steps for the recommended spacing for 25 or more contacts, or vias and flag regions enclosing 25 or more. The recommended spacings are included in the MITLL Low-Power FDSOI CMOS Process: Design Guide Diodes. Lateral diodes of good quality can be made in active by blocking silicide formation using either poly or NOSLC. MITLL is presently conducting experiments to determine the best rules for overlap of sourcedrain and extension implants. The body of the diode may be doped with either CBN (to make an n + /p diode) or CBP (to make a p + /n diode). The active region should be specified using ACTXPP instead of ACT, to avoid generating sidewall implants. For poly-defined diodes the poly length must be at least 0.3 µ m to avoid possible overlap due to misalignment. The poly may be connected electrically to either end of the diode or it may be floating, as desired. The designer should remember that the reverse bias voltage across the diode will be divided across two gate oxide thicknesses, anode to gate in series with gate to cathode. For long-term reliability the safe value of either gate voltage is limited to the power supply voltage of the process, usually 1.5 V. The best gate oxide reliability is expected to result from leaving the poly floating since this allows the poly potential to adjust itself in real time. (In the present design rules, this floating poly will be flagged as an error.) For NOSLC-defined diodes this gate oxide reliability concern is gone. The NOSLC length must be larger than the poly length because of more contributions to the misalignment budget. Designers should remember that NOSLC does not block the extension implants. Rev.: 2006:1 (Jun 06) 19

20 Linear Capacitors. Some versions of the MITLL low-power FDSOI CMOS process include additional process steps for fabrication of capacitors with low temperature and voltage coefficients. The CAPLCN, CAPP, and CAPN design layers may be used to define these devices. The active region of CAPP devices is doped using the SWN (NMOS sidewall implant) reticle, and CAPN devices use the SWP reticle. The nature of these two implants is determined primarily by transistor behavior, so the dose and energy may change in the future as the process evolves. Any such changes will affect the performance of capacitors that use these layers. Contact MITLL for information on the availability of these process steps. In process versions that include the CAPLCN option, the electrodes of linear capacitor structures are formed by an n + (i.e., CAPLCN implant) island and an n + poly layer. The sheet resistance of the CAPLCN island is approximately 160 Ω/sq. For certain applications, the designer may wish to reduce the resulting parasitic resistance by increasing the width of NSD-implanted active surround. If a silicide conductive surround is desired, the minimum NSD-implanted active surround should be at least 0.5 µ m. A sample layout for a linear capacitor structure is shown in Fig Active Poly CBP CAPLCN NSD 0.25 µm Figure 1-12: Capacitor device of approximately 100 ff. 20 Rev.: 2006:1 (Jun 06)

21 Likewise, CAPN may be used with n + poly, and CAPP with p + poly, to form capacitor devices with various capacitance-voltage properties. These are generally inferior to CAPLCN capacitors. For more information on the properties of various capacitor structures, contact MITLL. Note that a significant, bias-dependent parasitic capacitance exists between the capacitor bottom plate and the handle wafer. This capacitance is approximately 90 af/µ m 2. Rev.: 2006:1 (Jun 06) 21

22 Resistors. The digital and RF-optimized process versions may utilize either local or global SOI thinning. Modules available in other process versions include higher-level metals, deeply scaled PSM gates, 3D integration, local silicide, and additional implants. An example of a NOSLC resistor is presented in Fig In process versions that do not include a salicide protection layer (NOSLC), doped active resistors may be formed by using poly as a silicide block. The resistor is shunted by capacitance to the poly, but good RF resistors have been made by leaving the poly undoped and floating. Details of such devices are available in the MITLL FDSOI Cell Library. Sheet resistance is about 1000 Ω/sq for CAPN, 5000 Ω/sq for CAPP, and 180 Ω/sq for CAPLCN. The source-drain implant should overlap the poly by at least 0.1 µ m to assure that the resistor length is well defined. The same warning given for capacitors applies here: The CAPN and CAPP implants are determined primarily by the evolving transistor process, so they may change. Any such change would affect the values of resistors built this way. Low-value resistors such as 50-Ω matching devices are best fabricated using PSD-doped polysilicon. Heating of such devices is an issue owing to the thermal resistance of the buried oxide. If resistor value is critical, the power dissipation should be no more than about 0.1 mw/µ m 2. Using a large-area resistor also allows multiple contacts and hence reduces the effect of variation of contact resistance. MITLL has recently greatly improved the silicide process, resulting in lower values of silicided poly and active sheet resistance, particularly in the RF07 reticle set. Contact resistance has also improved. Some changes are likely to continue, but they should be smaller than the recent ones. ~3.8 kω Active NOSLC NSD CAPN Contact Cut 0.25 µm Figure 1-13: Doped island resistor. 22 Rev.: 2006:1 (Jun 06)

23 Resistor Devices and the DEVR Layer. The DEVR layer, shown in Fig. 14, is intended to designate polysilicon regions that are designed to act as resistors. It may be used by CAD tools that need to extract a netlist from an IC layout, for example, a layout-vs-source (LVS) tool. The DEVR layer allows polysilicon resistors to be distinguished from polysilicon conductors. For users of the Mentor Graphics layout tool, ICgraph, the MITLL process file will support device generators for n-doped and p-doped polysilicon resistors that will place the DEVR layer over the resistor from the contacts at one terminal to the contacts at the other terminal. The available rules file will support the recognition (by a Calibre netlister) of that device as a resistor whose resistance value matches that supplied to the generator. Poly DEVR Contact Cut Figure 1-14: Structure showing DEVR layer Inductor Devices and the DEVL Layer. The DEVL layer is intended to designate metal paths that are designed to act as inductors. For users of the Mentor Graphics layout tool, ICgraph, the MITLL process file will support device generators for spiral inductors that will place the DEVL layer over the entire metal path. However, no rules file is available at this time that will support the netlisting of such a spiral inductor as an inductor. A Calibre netlister, using the available rules file, will treat it as a conductor. Rev.: 2006:1 (Jun 06) 23

24 Active, Poly and Metal Fill Patterns. Planarization and etch processes are facilitated by relatively uniform metal and poly pattern densities. Even distribution of active, poly, and metal will reduce process variations and increase yield. In order to meet active, poly, and metal density constraints, dummy patterns should be added to the layout in open areas. The design layers ACTF, POLYF, M1F, M2F, M3F, M4F, M5F, and MTLRFF are provided for this purpose. The poly reticle will be produced based on the union of POLYF with POLY. Likewise, the metal reticles will be produced based on the union of M1F, M2F, M3F, M4F, M5F, and MTLRFF with M1, M2, M3, M4, M5, and MTLRF, respectively. The active island reticle will be produced based on the union of post-processed active layers ACTEXP and ACTF. This use of logical layers is intended to simplify computer-aided design. Layers ACTF, POLYF, M1F, M2F, M3F, M4F, M5F, and MTLRFF should only be used for fill features that do not contribute to the design functionality. Fill patterns may be floating or grounded. For floating metal fill the pattern illustrated in Fig. 1-15(a) is recommended. This consists of 10-µ m metal squares with centers spaced 15 µ m apart and 20-µ m clearance to same-level circuit metal. The resulting fill pattern density is about 44%. For active islands a fill pattern consisting of 7-µ m squares on 10-µm centers gives a 49% pattern density. For floating poly fill the pattern illustrated in Fig. 1-15(b) is recommended. This consists of 5-µ m poly squares with centers spaced 10 µ m apart and 11-µ m clearance to circuit poly. The resulting fill pattern density is about 25%. Fig. 1-15(c) shows generated metal fill 3 layers, and Fig. 1-15(d) shows generated active and poly fill layers. Consideration of the parasitic capacitances to fill structures is essential. Unwanted coupling of signals through floating fill features is possible. In some sensitive circuit areas, the designer may choose to use grounded fill patterns to achieve required pattern densities. When grounded fill features are used, however, capacitances to fill patterns may still contribute to circuit delays. Therefore, it is especially important that fill-related parasitics be included in simulations. MITLL will generate fill patterns in unused areas unless the NOFILL layer is present. When NOFILL is used, the designer is still responsible to ensure compliance with all layer density specifications. Noncompliant layouts will require discussion between the designer and MITLL, and will delay reticle generation. Therefore, if a design violates the density specifications, the designer should explain the reason at the time or before the design is submitted. 24 Rev.: 2006:1 (Jun 06)

25 10 µm 5.0 µm Metal Fill Pattern Poly Fill Pattern 20 µm 11 µm 15 µm (a) Circuit Metal (Same Level) Poly Circuit (b) 10 µm Fill Squares: Large Small Metal: Wide Narrow Metal Metal Fill (c) (d) Figure 1-15: Recommended fill patterns for (a) floating metal fill and (b) floating poly fill, and (c) generated metal fill 3 layers and (d) generated active and poly fill layers. Rev.: 2006:1 (Jun 06) 25

26 Automatic Generation of Fill Patterns by MITLL. During layout post-processing, MITLL will generate fill patterns in open areas, provided that no feature exists on the NOFILL layer in that region. The present version of this autogeneration routine is summarized in Table 1-1. (The descriptions in Table 1-1 express the primary intent but leave out several details for simplicity.) The output from this routine will be made available to each designer to allow simulation of fill effects. Table 1-1: Fill Generation Routine Step Layer(s) Description 1 Active, poly Active and poly are OR ed together and scaled by 6 µ m to form region ACTR1, and by 2 µ m to form region ACTR2. A fill feature is then formed by the operation ACTR1 AND (NOT ACTR2). This leaves a 4-µ m fence of active fill around the circuit area as shown in Fig. 1-15(d). 2 Active Squares of active fill of 7 µ m x 7 µ m are generated with a pitch of 10 µ m in X and Y. They are excluded from within 10 µ m of ACT, ACTXPP, or POLY and 3 µ m of ACTF and POLYF. Smaller squares 1.5 µ m x 1.5 µ m with a pitch of 1.6 µ m in X and Y are then placed in the region 2 µ m away from ACT, ACTXPP, or POLY and out to 16.5 µm. These small squares are also excluded from ACTF and POLYF, including the previously generated 7-µ m ACTF squares, by 1 µ m. 3 Poly Squares of poly fill are generated by sizing down the ACTF squares 3.7 µ m x 3.7 µ m with a pitch of 10 µ m centered on the large squares, and 0.8 µ m x 0.8 µ m with a pitch of 1.6 µ m centered on the small squares. 4 All metals Metal fill is first generated as squares of 10 µ m x 10 µ m with a pitch of 15 µ m in X and Y. This metal fill is excluded by 20 µ m from metal and 5 µ m from drawn metal fill. Squares of metal fill of 1 µ m x 1 µ m are placed in the region 1 µ m away from the metal out to 30 µ m and excluded 2 µ m from previously drawn or generated fill of the same layer. These small squares are also excluded 10 µ m from metal wider than 9 µ m, and 20 µ m from metal wider than 29 µ m. (Generated M1F is only determined by M1, M1F, and NOFILL; M2F by M2, M2F, and NOFILL; etc.) Note that fill is generated for the entire top-level cell extent, except in regions that have the NOFILL flag layer. 26 Rev.: 2006:1 (Jun 06)

27 Antenna Effects and the Metal Z Layer. Many foundry process design guides include rules related to transistor gate damage by antenna effects during etching of the gate itself and all the metal layers attached to it. Antenna damage is reduced in SOI because the buried oxide greatly suppresses the current through gate oxides during etch, so MITLL has not imposed antenna rules. We have observed, however, indications of damage on test transistors in which the probe pad itself constitutes a large antenna. These transistors have pads attached to the gate on all three metal layers, along with many plasma-etched vias, so they represent an extreme example of a large antenna. For our test devices we plan to make two versions of the metal 1 mask. One version, called metal 1, will be used on wafers that will continue to higher levels of metal. On metal 1, we will not include a probe pad, but just a via (or a few vias) up to a small piece of metal 2, and a second via (or a few vias) up to the probe pad on metal RF. The other version, called metal Z, will be used on experimental wafers that will finish after metal 1 (and perhaps overglass). Metal Z will be the same as metal 1, except that it will include probe pads. Thus, metal Z will look similar to past metal 1 reticles. This added reticle is available to designers outside MITLL who wish to take advantage of it. For RF designers, it provides the opportunity to minimize pad capacitance by leaving out metal 1 under the metal RF I/O pads while still having devices that are testable on wafers whose process ends after metal Z. This option is relevant only for devices that do not depend on higher metal layers. Designers who are not interested in it can either make metal Z identical to metal 1 or leave metal Z blank. In the latter case the metal Z layer will contain nothing but a uniform array of fill. Metal Z will be used only for wafers on which metal 2 and higher will not be processed. The design rules for metal Z are identical to those for metal 1. Fill will be generated automatically and suppressed by the NOFILL flag just as for metal 1. Users should contact MITLL before attempting to use the metal Z layer. Rev.: 2006:1 (Jun 06) 27

28 RF Transistor Layout Suggestions. Four suggestions on the layout of an RF transistor, illustrated in Fig. 1-16, are presented below. ACT Source CBN NSD TGSRF Gate POLY Drain M1 MTLRF M2 V12, VTLRF Source CON Figure 1-16: RF transistor. 1. The T-gate slot (TGSRF) should cover the entire poly-si gate over the active (for a minimum-length gate). The metal 1 needs to cover the T-gate slot. The metal surround requirement, Rule 17.03, on contacts is ignored on TGSRF because we anticipate that only very small circuits will use TGSRF. A designer can reduce fabrication risk slightly by providing a µ m surround of metal 1 on TGSRF at the expense of increased distance between gate and source drain contacts. 2. Even with T-gate, a poly-si contact cut is required (Rule 15.09) for connecting the gate to metal 1 to reduce fabrication risk. 28 Rev.: 2006:1 (Jun 06)

29 3. The contact cut to the source/drain regions must follow the design rule requirement for density. For a wide source/drain region, contact cuts should be placed close to the edge facing the gate to minimize series resistance. 4. Source/drain fingers can include all metal layers to minimize the series resistance (for good f T and f max ) and to reduce the current density in the metal fingers (to minimize electromigration). MITLL does not specify electromigration requirements because we have not done long-term accelerated testing of the metal, and circuits built in multiproject lots are intended for demonstration, not for deployment in the field. The conventional DC rule of thumb for aluminum interconnect, 1 ma/µ m 2, would require very wide metal in the source and drain fingers of many RF transistors. We have found that 3 ma/µ m 2 has been sufficient for our devices. We remind designers that the drain finger in Fig carries current for two gates, not just one. Minimum widths specified by the design rules for source/drain and metal fingers may be too small if a large drive current is expected. The drive current of each finger increases with increasing finger width. Rev.: 2006:1 (Jun 06) 29

30 A sample layout of probing pads for on-wafer RF testing is shown in Fig Source Gate Drain Source Figure 1-17: Sample layout of probing pads for on-wafer RF testing. The spacing from gate/drain pads to source pads is determined by the pitch of the probes and the requirement for achieving 50-Ω impedance. The width of the pads is tapered to the device to maintain a 50-Ω impedance. The source pads can be made wide enough to accommodate probe pitches from 100 to 150 µ m in order to increase probing flexibility. MITLL and AFRL have found that 50-µ m and 100-µ m widths of gate and drain pads are appropriate. A spacing of 35 µ m results in a transmission line of approximately 50 Ω. The small green squares shown are the active fill patterns. The impact of adding fill patterns under the metal pads is small, and only a small area around the device should be free of fill patterns. This can be done by adding a nofill box around the device. If no specifications are made, the automatic fill rules we use are adequate for fill-pattern exclusion near the device. Two source pads can be connected by extending the source metal around the gate/drain pads, as shown in Fig This will provide a better-defined ground plane, but the area increases significantly. Parasitic capacitance can be minimized by placing gate and drain pads only on the top metal layer with a small array (2x2) of vias to connect each pad to metal 1. This reduces the accuracy requirement for deembedding, particularly for relatively narrow transistors. To allow probing such a device on experimental fabrication runs that go only through one metal layer, pads can also be provided on metal Z. See the section Antenna Effects and the Metal Z Layer. 30 Rev.: 2006:1 (Jun 06)

31 3D FDSOI DESIGN 2. 3D FDSOI DESIGN 2.1. Introduction Lincoln Laboratory has developed a three-dimensional (3D) integrated circuit technology in which circuit structures formed on several silicon-on-insulator (SOI) substrates may be integrated into a 3D integrated circuit. The building blocks of the 3D circuit integration technology are fully depleted SOI circuit fabrication, low-temperature wafer-wafer oxide bonding, precision wafer-wafer alignment, and electrical connection of the circuit structures with dense vertical interconnections. When compared to conventional bump bond technology, this 3D technology offers better circuit-to-interconnect ratio, higher-density vertical interconnections, and reduced system power. This section describes the integration process and highlights some unique design requirements D Circuit Integration Three-dimensional circuits are fabricated by transferring and interconnecting the active sections of wafers fabricated on 150-mm SOI substrates to a base wafer. The active section, labeled a tier, in a 3D system of n tiers consists of the interconnect and active silicon and is transferred to the base tier, tier 1, which can be either a bulk or SOI wafer. Since all 3D circuits that are designed as part of the digital 3D Multiproject program will be composed of three SOI tiers, the base wafer will also be SOI. The 3D circuit integration process begins with the fabrication of three fully depleted SOI tiers, as shown in Fig Then, wafer 2 is inverted, aligned, and bonded to wafer 1, as shown in Fig The handle silicon is removed from tier 2, 3D vias are etched through the oxides of tiers 2 and 1 and stop on metal pads in tier 1, and tungsten is deposited and planarized using chemical-mechanical polishing (CMP). The structure shown in Fig. 2-3 is a two-tier assembly with electrical connections between the top-level metal of tier 2 and the toplevel metal of tier 1. Following the inter-tier via formation, back side via (BVIA0) and back side metal (BM1) are formed, as shown in Fig Tier 3 is transferred to the two-tier assembly using the same processes as for the tier 2 transfer, except that the 3D vias connect the top-level metal of tier 3 to the back side metal of tier 2, as shown in Fig The completed 3D assembly is shown in Fig. 2-6 after back side metallization of tier 3. Bond pads and heat sink cuts are formed (3DOGC) to expose this tier 3 BM1 for probing, wire bonding, and cooling. A detailed list of layer thicknesses is presented in Fig Rev.: 2006:1 (Jun 06) 31

32 3D FDSOI DESIGN Wafer 3 Buried Oxide Handle Silicon Tier 3 Wafer 2 Buried Oxide Handle Silicon Tier 2 Wafer 1 Buried Oxide Handle Silicon Tier 1 Figure 2-1: Three tiers that will be integrated to form a 3D integrated circuit at the completion of conventional integrated circuit fabrication. Wafer 2 Handle Silicon Tier 2 Wafer Bond Tier 1 Wafer 1 Figure 2-2: Tier 2 aligned and bonded to tier 1 before removal of the handle silicon. The wafer bond is a low-temperature oxide bond. W Connection Tier 2 Concentric 3D Via Wafer 1 Tier 1 Handle Silicon Figure 2-3: Tier 2 electrically connected to tier 1 with tungsten plugs after removal of the handle silicon, etching of 3D vias between the tiers, and deposition and planarization of tungsten. 32 Rev.: 2006:1 (Jun 06)

33 3D FDSOI DESIGN Tier 2 Tier 1 Wafer 1 Handle Silicon Figure 2-4: Tiers 1 and 2 after teir 2 back side via and back side metal formation. Tier 3 Tier 2 Tier 1 Wafer 1 Handle Silicon Figure 2-5: Tier 3 after it was aligned, transferred, and interconnected to the assembly shown in Fig DOGC Opens to This Metal Level Tier 3 Tier 2 Tier 1 Wafer 1 Handle Silicon Figure 2-6: Three-tier assembly of Fig. 2-5 shown after tier 3 back side metal formation. Locations of possible 3DOGC overglass cuts are indicated. Rev.: 2006:1 (Jun 06) 33

34 3D FDSOI DESIGN Tier 3 Back Metal 1 (RF) 2000 Tier 3 : BM1 Tier 3 : BM1 Tier 3 : BM1 Tier 3 Cap oxide 200 Tier 3 BOX 400 Tier 3 SOI island 50 Tier 3 LTO over island 800 Tier 3 Metal Tier 3 Tier 3 Metal 2 Tier 3 Tier 3 Metal 3 Tier 3 Tier 3 Tier 2 Tier 2 Tier 2 ILD 1-2 PECVD TEOS ILD 2-3 PECVD TEOS Back metal M3 overglass PECVD TEOS 500 BSG cap oxide 500 BSG cap oxide PECVD TEOS 630 Tier 2 Cap oxide 200 Tier 2 BOX 400 Tier 2 SOI island 50 Tier 2 LTO over island 800 Tier 2 Metal Tier 2 ILD 1-2 PECVD TEOS 1000 Tier 2 Metal Tier 2 ILD 2-3 PECVD TEOS Tier 2 Metal Tier 2 M3 overglass PECVD TEOS 500 Tier 2 BSG cap oxide 500 Tier 1 BSG cap oxide 500 Tier 1 M3 overglass PECVD TEOS 500 Tier 1 Metal Tier 1 ILD 2-3 PECVD TEOS 1000 Tier 1 Metal Tier 1 ILD 1-2 PECVD TEOS 1000 Tier 1 Metal nm T3 BV0 Tier 3 : M1 Tier 3 : M3 Oxide-Oxide Bond Tier 2 : M3 Oxide-Oxide Bond 1450 nm 2000 nm Tier 2 : M1 3D Via 7340 nm Tier 2 : BM1 T2 BV0 Tier 1 : M nm 3D Via Tier 2 : BM1 3D Via 7340 nm 2000 nm Tier 1 : M nm 3DM2 Tier 3 3DM2 Tier 2 3DM2 Tier 1 Tier 1 LTO over island 800 Tier 1 SOI island 50 Tier 1 BOX 400 Tier 1 Silicon substrate Figure 2-7: Thickness stack for three-tier structure with actual layer thicknesses indicated. 34 Rev.: 2006:1 (Jun 06)

35 3D FDSOI DESIGN D Design Practices The layout of each tier of a 3D circuit should be done as in conventional 2D technology. The designer must take into account the integration process discussed above, since the two upper tiers will be inverted with respect to tier 1 and the three tiers must be designed such that they will be aligned during fabrication. The layers for each tier will be placed correctly on each reticle with existing layout software, provided the designer has designed each tier with coincident origins. Connections between tiers require a 3DCUT, which defines the 3D via starting point on the higher numbered tier, and 3DLAND, which defines the 3D via stopping location on a metal layer on the lower numbered tier. When the tiers are overlaid, the 3DCUTs must exactly match the 3DLANDs in the lower tier and each 3DLAND must have a matching 3DCUT in the higher tier. The top of a 3D via starts on the back side of the higher numbered tier, and the 3DCUT dimension determines its size. The size of the 3D via in the lower tier is defined by the doughnut opening in metal 3 of the upper tier; the doughnut is illustrated in the MITLL Low-Power FDSOI CMOS Process: Design Guide (Rule 41.06). The 3DCUT feature is unique to the 3D technology, but the designer must ensure that the 3DLAND and doughnut features are included in the metal designs of the FDSOI layers. Table 2-1 shows the metal layers of the 3DLAND and doughnut features for each tier; the two 3DCUT layers are color coded to associate them with the tiers to be interconnected. Table 2-1: Metal features associated with 3DCUT and 3DLAND layers required for 3D circuit integration Tier 3DLAND Doughnut Tier 3DCUT 1 1 Metal 3 None 1 2 Metal 1 Metal None Metal 3 3 3DCUT D Layout Orientation Layouts for all three tiers should be done as viewed after assembly, with bond pads to the 3D circuit face up Thermal Management Considerations The analysis and control of temperature effects in a 3D circuit is a topic of current research. The designer can reduce the effects of power dissipation on the operation of 3D circuits by placing the circuits that dissipate the most power in tier 1, since the base of tier 1 is the silicon handle and it will be attached to an IC package for mechanical stability and heat conduction. Heat generated by circuits in tier 3 can be managed by including a back metal structure to aid the extraction of heat through the top side of the circuit. Rev.: 2006:1 (Jun 06) 35

36 This page intentionally left blank

37 CONTACT INFORMATION CONTACT INFORMATION For specific inquiries: Technical: Layout submission: Brian Tyrrell Bruce Wheeler (781) (781) Device modeling: Editorial: Peter Wyatt Karen Challberg (781) (781) For any other questions, comments, or suggestions: MIT Lincoln Laboratory Advanced Silicon Technology Group 244 Wood Street Lexington, MA Phone: (781) Fax: (781) Rev.: 2006:1 (Jun 06) 37

38 This page intentionally left blank

39 REVISION HISTORY REVISION HISTORY Rev. 2006:1 (May 06) Revision of paragraph 1, Section 1.1, Introduction Revision of paragraphs 2 and 3, Section 1.3, Silicided Poly and Active Features Revision of subsection 1.6.2, Dog Bone Transistors Replacement of notation SWNCH by SWN Modification of Figure 1-6 Revision of introductory paragraph, Section 1.7, Special Purpose MOS Structures Revision of subsection 1.7.1, Edgeless Annular Devices Modification of Figures 1-8 and 1-9 Revision of paragraphs 4 and 6, subsection 1.7.2, Source-Side Body Contacted Devices Revision of paragraphs 1 and 3, subsection 1.7.3, H-Gate Devices Deletion of paragraph 2, subsection 1.7.4, Abutting Devices Revision of paragraph 2, subsection 1.7.5, Conductive Lines Revision of paragraphs 1 and 4, subsection 1.7.7, Linear Capacitors Revision of subsection 1.7.8, Resistors Modification of Figure 1-13 Revision of paragraph 3, subsection , Active, Poly and Metal Fill Patterns Modification of Figure 1-15(b) (d) Revision of Table 1-1 Addition of paragraph 6, subsection , Antenna Effects and the Metal Z Layer Revision of Section 2.2, 3D Circuit Integration Renumbering of Figures to Figures Addition of new Figure 2-4 Modification of new Figure 2-7 Deletion of Section 2.3, 3D Circuit Example, and renumbering of Sections Revision of Section 2.5, Thermal Management Considerations Addition of detailed revision log Rev.: 2006:1 (Jun 06) 39