SpringerBriefs in Electrical and Computer Engineering

Transcription

1 SpringerBriefs in Electrical and Computer Engineering For further volumes:

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3 Vikram Arkalgud Chandrasetty VLSI Design A Practical Guide for FPGA and ASIC Implementations

4 Vikram Arkalgud Chandrasetty University of South Australia Adelaide, Australia ISSN e-issn ISBN e-isbn DOI / Springer New York Dordrecht Heidelberg London Library of Congress Control Number: Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (

5 To My Family and Friends

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7 Preface The area of VLSI design has gained enormous popularity over the past few decades due to the rapid advancements in integrated circuit (IC) design and technology. The ability to produce miniaturized circuits with high performance in terms of power and speed is the reason for its popularity. Low production cost and advanced techniques for reduced time-to-market adds to the ever-growing demand for ICs. The two major IC design flows FPGA and ASIC have their own advantages and disadvantages. FPGAs are widely used for quick prototyping and also implementation of various multimedia applications by compromising power, area and speed performance with substantially reduced time-to-market and cost factors. Using ASIC technology, it has been possible to develop high performance multi-core processors. Verification and testing of such complex designs is a critical and challenging task to ensure the quality of the resulting circuits. The advances in EDA software and CAD tools alleviate the effort necessary to carry out the cumbersome design and verification process of ICs. As we understand that the subject of VLSI design is vast, it is quite complex to find and comprehend the complete details about the design process. This book VLSI Design: A practical guide for FPGA and ASIC implementations provides an insight into practical design of VLSI circuits with minimal theoretical arguments. While this publication is not a complete text book on VLSI design, it is intended to serve as supplementary or reference material on practical design and implementation of VLSI circuits. The content of the book is focused for novice VLSI designers and other enthusiasts who would like to understand the VLSI practical design flows. The designs are demonstrated using industry standard software from MATLAB, Mentor Graphics, Xilinx, Synopsys and Cadence. I encourage you to send any errata or feedback for improving the quality of this book to vikramac@ieee.org. Thank you, Adelaide, Australia Vikram Arkalgud Chandrasetty vii

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9 Contents 1 CMOS Digital Design Design of CMOS SRAM Cell and Array Plan of SRAM Cell and Array Design of 6 Transistor SRAM Cell Simulations of SRAM Cell Layout of SRAM Cell Design of SRAM Array Simulation of SRAM Array Design of SRAM Chip Circuit Elements SRAM Chip Circuit Elements Design of Complete SRAM Chip Simulations of Complete SRAM Chip Delay Extraction for SRAM Chip Write/Read Operation Re-Design of SRAM Chip for Low Power Consumption Appendix References FPGA Application Design Design of Direct Sequence-Spread Spectrum System PN Sequence Generator Transmitter for Direct Sequence-Spread Spectrum System Receiver for Direct Sequence-Spread Spectrum System FIR Filter Design Concepts of FIR Filter Low Pass FIR Filter Design Distributed Arithmetic Architecture Simulation and Synthesis Results ix

10 x Contents 2.3 Discrete Cosine Transform Algorithms Concepts of DCT DCT Architectures on FPGA Scaled 1-D 8-Point DCT Architecture Simulation and Synthesis Results Convolution Codes and Viterbi Decoding Concepts of Convolution Codes Viterbi Decoder Simulation and Synthesis Results Appendix References ASIC Design ASIC Front-End Memory Design Introduction Memory Architecture and Specifications Implementation and Simulations Results Analysis and Conclusion ASIC Front-End Matrix Multiplier Design Introduction Problem Statement Matrix Multiplier Design Implementation and Simulations Analysis of Results and Conclusion Physical Design of Matrix Multiplier Introduction to Systolic Array Matrix Multiplier Physical Design Flow Results and Conclusion Appendix References Analog and Mixed Signal Design Schematic Design of OPAMP Introduction Two Stage OPAMP Design Results Layout Design of OPAMP Introduction Layout Design Summary and Results Appendix References About the Author

11 Abbreviations ADC ASIC ATM AWGN BJT BPSK CAD CDMA CDR CMOS CORDIC CP CTO CTS DAA DAC DCT DEF DFM DFT DRAM DRC DSPF DSSS DTC DTFS DUT DWT Analog to Digital Converter Application Specific Integrated Circuit Asynchronous Transfer Mode Additive White Gaussian Noise Bipolar Junction Transistor Binary Phase Shift Keying Computer Aided Design Code Division Multiple Access Clock Data Recovery Complementary Metal Oxide Semiconductor Coordinate Rotation Digital Computer Charge Pump Clock Tree Optimization Clock Tree Synthesis Distributed Arithmetic Architecture Digital to Analog Converter Discrete Cosine Transform Design Exchange Format Design For Manufacturability Design For Testability Dynamic Random Access Memory Design Rule Check Detailed Standard Parasitic Format Direct Sequence Spread Spectrum Divide by Two Circuit Deflash Trim Form Singulation Device Under Test Discrete Wavelet Transform xi

12 xii Abbreviations EDA EEPROM ERC FDA FEC FF FFT FIR FPGA FSM GDS II GUI HDL ICMR IGFET IOV ITF ITRS JFET JPEG LEF LFSR LP LPE LSB LUT LVS MAC MBE MEMS MOSFET MOSIS MPEG MSB OVS PFD PG PIT PLL PN PPO PWM Electronic Design Automation Electrically Erasable Programmable Read Only Memory Electrical Rule Check Functional Data Analysis Forward Error Correction Codes Flip Flop Fast Fourier Transform Finite Impulse Response Field Programmable Gate Array Finite State Machine Graphic Data System II Graphical User Interface Hardware Description Language Input Common Mode Range Insulated Gate Field Effect Transistor Input Offset Voltage Interconnect Technology Format International Road Map for Semiconductors Junction Field Effect Transistor Joint Photographic Experts Group Library Exchange Format Linear Feedback Shift Register Low Pass Layout Parasitic Extraction Least Significant Bit Look Up Table Layout Versus Schematic Multiply And Accumulate Molecular Beam Epitaxy Mico Electro Mechanical System Metal Oxide Semiconductor Field Effect Transistor Metal Oxide Semiconductor Implementation Service Moving Picture Experts Group Most Significant Bit Output Voltage Swing Phase Frequency Detector Power Ground Progressive Image Transmission Phase Locked Loop Pseudo-random Noise Post Placement Optimization Pulse Width Modulation

13 Abbreviations xiii QAM QDR QPSK RC RF ROM RTL SDC SDF SNR SOI SOP SPEF SRAM STA TDF TLU TSMC TS-OPAMP USB VCD VCO Quadrature Amplitude Modulation Quad Data Rate Quadrature Phase Shift Keying Resistance Capacitance Radio Frequency Read Only Memory Register Transfer Level Synopsys Design Constraint Standard Delay Format Signal to Noise Ratio Silicon On Insulator Sum Of Products Standard Parasitic Exchange Format Static Random Access Memory Static Timing Analysis Top Design Format Table Look Up Taiwan Semiconductor Manufacturing Company Two Stage Operational Amplifier Universal Serial Bus Value Change Dump Voltage Controlled Oscillator

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