Energy-Efficient Fault-Tolerant Systems
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1 Energy-Efficient Fault-Tolerant Systems
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3 Jimson Mathew Rishad A. Shafik Dhiraj K. Pradhan Editors Energy-Efficient Fault-Tolerant Systems 123
4 Editors Jimson Mathew Department of Computer Science University of Bristol Bristol, UK Rishad A. Shafik Department of Computer Science University of Bristol Bristol, UK Dhiraj K. Pradhan Department of Computer Science University of Bristol Bristol, UK ISBN ISBN (ebook) DOI / Springer New York Heidelberg Dordrecht London Library of Congress Control Number: Springer Science+Business Media New York 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (
5 Dedicated to our inspirations Raisa Alan Linda Babita Sonia
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7 Foreword Energy efficiency is a prime design objective for embedded systems. Over the years, various techniques have been proposed highlighting energy-efficient systems design. These techniques have shown effective ways to reduce energy, while satisfying the system performance needs. However, due to continued device miniaturization and technology scaling, reliability in the presence of ever-increasing number of faults is emerging as an additional design challenge. Incorporating fault tolerance and energy efficiency is not trivial since they are two conflicting design objectives. Currently no book exists that gives a complete account of the state-of-the-art and emerging techniques for design, analysis, and testing of energy-efficient, faulttolerant electronic systems. The book at hand is expected to appropriately fill this gap and will be highly useful for students, researchers, and practitioners working in relevant areas. Chalmers University of Technology Gothenburg, Sweden Georgi N. Gaydadjiev vii
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9 Preface Energy efficiency is a widely acknowledged design objective in electronic systems research and development. With continued technology scaling reliability is an emerging concern in these systems due to increased device-level vulnerability in the presence of electromagnetic inductions and process variability. Achieving high reliability and energy efficiency objectives jointly can, however, be challenging as energy minimization techniques exacerbate the reliability further. Hence, energyefficient fault-tolerant (i.e. reliable) design is currently of high interest to both industry and academia to address these challenges effectively. The aim of this book is to introduce state-of-the-art and emerging issues in energy-efficient faulttolerant design techniques as applied or prototyped for current or future generations of system-on-chip (SoC). Although necessary brief background has been provided in each chapter, fundamental theories have been omitted or avoided. The reader is expected to have preliminary background of electronic circuits and systems design and synthesis. The book consists of nine chapters; five chapters (Chaps. 1 5) are dedicated towards systems modeling and design techniques, while four other chapters (Chaps. 6 9) delve into emerging systems architectures and design challenges. The individual chapter outlines are given below. Chapter 1 (Introduction to Energy-Efficient Fault-Tolerant Systems) provides the necessary background relevant to this book. Low-power design aspects are briefly revisited, and concepts related to faults and reliability are reviewed. Underpinning these basics, challenges of energy-efficient fault-tolerant systems design are highlighted showing various techniques. Chapter 2 (Reliability Evaluation Techniques) gives a comprehensive review of the reliability models. In particular, methods for evaluating system reliability with stochastic modeling and other combinatorial methods are discussed in details. Chapter 3 (Energy-Efficient Design Techniques) presents an overview of power minimization and power management techniques. The impact of energy-efficient design techniques on the system reliability is also investigated. Extensive case studies are presented addressing energy-efficient fault-tolerant design techniques. ix
10 x Preface Chapter 4 (Error Correction Coding for Electronic Circuits) discusses various existing and emerging error detection and correction (EDAC) codes mainly used in sequential circuits. Implementation and suitability of various EDAC codes are detailed with examples, followed by their analyses in terms of fault detection and tolerance capabilities, overheads, and circuit complexities. Chapter 5 (System-Level Design Methodology) introduces system-level design methodology, particularly suitable for multiprocessor system-on-chip (MPSoC). Various MPSoC design challenges are discussed, highlighting ways to effectively address them using system-level design methodology. Later, an extensive systemlevel design optimization case study is presented investigating into the impact of application task mapping on MPSoC applications. Chapter 6 (Fault-Tolerant Reconfigurable On-Chip Network) presents faulttolerant reconfigurable on-chip networks, which are infrastructure communication architectures for future computing platforms. The impact of workload variations on the fault-tolerance of reconfigurable on-chip network is also studied in details through a number of case studies. Chapter 7 (Bio-Inspired Online Fault Detection in NoC Interconnect) deals with bio-inspired online and low-cost fault detection capabilities for emerging scalable network-on-chip-based multiprocessor systems. In particular, a novel real-time strategy for detecting faults in NoC interconnectis demonstratedthat uses biological synapses and neurons to detect temporal and spatial faults effectively. Analysis of different fault scenarios and results from real-time experiments on an example FPGA implementation are also provided. Chapters 8 (Power-Efficient Fault-Tolerant Finite Field Multiplier) and 9 (Low- Cost C-Testable Finite Field Multiplier Architectures) investigate into emerging low-complexity techniques for secure and fault-tolerant hardware design. To solve the problem of an attacker injecting faults into the hardware and then analyzing the incorrect outputs, different detection and correction mechanism are studied in detail. The aim is to ensure that the effect of injected errors is not visible at the outputs for the attacker to be able to intercept and compromise the security and fault-tolerance of the system. Moreover, new methods for secure error detection and correction using various type of codes are investigated for scan-based attacks during testing. We would like to acknowledge the outstanding contributions from our chapter contributors. Without their valued efforts, this book would not have been possible. We would also like to gratefully appreciate the efforts of our expert panel of reviewers, who helped with their useful feedback to improve the overall quality and coherence of the book. Bristol, UK Jimson Mathew Rishad A. Shafik Dhiraj K. Pradhan
11 Contents 1 Introduction to Energy-Efficient Fault-Tolerant Systems... 1 Rishad A. Shafik, Jimson Mathew, and Dhiraj K. Pradhan 2 Reliability Evaluation Techniques Rong-Tsorng Wang 3 Energy-Efficient Design Techniques Rong Ye and Qiang Xu 4 Error Correction Coding for Electronic Circuits Juan A. Maestro, Pedro Reviriego, and Mark F. Flanagan 5 System-Level Design Methodology Rishad A. Shafik, Bashir M. Al-Hashimi, and Krishnendu Chakrabarty 6 Fault-Tolerant Reconfigurable On-Chip-Network Mohammad Hosseinabady and Jose L. Nunez-Yanez 7 Bio-Inspired Online Fault Detection in NoC Interconnect Malachy McElholm, Jim Harkin, Liam McDaid, and Snaider Carrillo 8 Power-Efficient Fault-Tolerant Finite Field Multiplier Jimson Mathew, A.M. Jabir, R.A. Shafik, and D.K. Pradhan 9 Low Cost C-Testable Finite Field Multiplier Architectures Jimson Mathew, H. Rahaman, and D.K. Pradhan Index xi
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13 Acronyms ABB AHB AMBA APB ASA ASB ASIC AXI BILP DCT DRAM DSP DTU DUT DVS EDA ESL FER FI FIFO FIR FIT FLIT FPGA HDL HW HW/SW IDCT ILP ISQ MC Adaptive base bias Advanced high-performance bus Advanced microprocessor bus architecture Advanced peripheral bus Adaptive simulated annealing Advanced system bus Application-specific integrated circuit Advanced extensible interface Binary integer linear programming Discrete cosine transformation Dynamic random access memory Digital signal processor Data transaction unit Device under test Dynamic voltage scaling Electronic design automation Electronic system level Frame error ratio/rate Fault injection First-in first-out Fault injection rate Failures in time Flow control unit Field programmable gate array Hardware description language Hardware Hardware/software Inverse discrete cosine transformation Integer linear programming Inverse scan and quantisation Motion compensation xiii
14 xiv Acronyms MCU MPARM MPEG MPSoC MTBF MTTF MTTR NI NoC OSCI P2P PE PSNR RAM RHEL RTEMS RTOS RTL SA SER SEU SoC SRAM SW VLD VLSI Microcontroller unit Multiprocessor ARM Moving picture experts group Multiprocessor system-on-chip Mean time between failure Mean time to failure Mean time to repair Network interface Network-on-chip Open SystemC initiative Point-to-Point Processing element Peak signal-to-noise ratio Random access memory Red Hat Enterprise Linux Real-time executive for embedded systems Real-time operating system Register transfer level Simulated annealing Soft error rate Single-event upset System-on-chip Static random access memory Software Variable length decoder Very large-scale integration
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