Development of Algorithm and Architecture of Demodulator for Processing Satellite Data Communication

Transcription

1 i Development of Algorithm and Architecture of Demodulator for Processing Satellite Data Communication THESIS Submitted by K. R. NATARAJ For the award of the degree Of DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING Dr. M.G.R EDUCATIONAL AND RESEARCH INSTITUTE UNIVERSITY (Declared U/S 3 of the UGC Act, 1956) CHENNAI February 2010

2 ii BONAFIDE CERTIFICATE Certified that this theses Titled Development of Algorithms and Architectures of Demodulator for Processing Satellite Data Communication is the bonafide work of Mr. K. R. NATARAJ, who carried out the Research under my Supervision. Certified further, that to the best of my Knowledge the work reported herein does not form part of any other thesis or dissertation of the basis of which a degree or award was conferred on an earlier occasion on this or any other candidate. Signature of the supervisor

3 iii DEDICATED TO MY BELOVED PARENTS

4 iv DECLARATION I declare That the thesis entitled Development of Algorithms and Architectures of Demodulator for Processing Satellite Data Communication Submitted By me for the Degree of Doctor of Philosophy is the record of work carried out by me during the period from Jan to Jan under the guidance of Dr B. S. Nagabhushana and Dr S. Ramachandran and has not formed the basis for the award of any degree, diploma, associate-ship, fellowship, titles in this or any other university or other similar institution of higher learning. Signature of the candidate

5 v ABSTRACT This Research is focused on the development of a new algorithms and architectures for a QPSK demodulator used for on-board satellite data communication. In satellite communication, carrier frequency offsets are large due to the Doppler Effect and various other factors. An algorithm for carrier frequency offset estimation is developed. Recursive Least Squares algorithm is employed to find the slope of the best fit line through the unwrapped phase of the received symbols under training. This gives an estimate of the frequency offset. Timing recovery is performed by making use of modified Peak Average Energy Criterion, which is an approximation to the Maximum likelihood estimation. Phase tracking and detection are done using the Least Mean Square algorithm. The algorithms are made computationally efficient in order to reduce the computational load on the processing engines, without impairing the performance. Further, this Research proposes a novel VLSI architecture for the demodulator for processing satellite communication data. The overall receiver algorithm is divided into two parts: The first part is proposed for implementation on an FPGA and the second part is proposed for implementation on a DSP. A new Sampling Rate Converter is also proposed based on Distributed Arithmetic. The main advantage of this architecture is that it does not employ any MAC unit, whose operational speed is, generally, a bottleneck for high filter throughput. Instead, it makes extensive use of LUTs and hence is ideally suited for FPGA implementation. Further, a new Architecture is proposed and developed for Digital Frequency Synthesizer, which provides 60 db spectral purity, and is adequate for the proposed implementation.

6 vi The developed FPGA core consists of a Mixer and two filters (each being an RRC filter with 193 taps). This logic shall accept modulated, 12-bit, signed ADC output at a sampling frequency of MHz and convert it into In-phase (I) and Quadrature-phase (Q) channel outputs, each of size 16 bits, signed, at half the sampling frequency. The performance related goal in this Research work is to maintain low system complexity, reduce power consumption and optimize chip area requirements. The proposed architecture is coded in Verilog HDL and implemented on a Xilinx FPGA. The design was synthesized with XCV600-4 FPGA/3S400pq208-5 and occupies about 2360 slices with an equivalent gate count of about and operating at a maximum frequency of 19.8 MHz. The entire modulator and demodulator have also been coded in MATLAB in order to validate the hardware results. The hardware and MATLAB results compare favorably. Keywords: Algorithm, Distributed Arithmetic Architecture, Demodulator, Digital Frequency Synthesizer, Field Programmable Gate Array, Linear algebra, Quadrature Phase Shift Keying, Sampling Rate Converter, Transponder, Verilog and Matlab.

7 vii ACKNOWLEDGEMENTS I am highly indebted to Dr. B. S. Nagabhushana, Director Sanlab Infotech Pvt. Limited and formerly from Indian Instate of Science Bangalore for having been my Research supervisor. I wish to express my deep sense of gratitude for his valuable guidance, encouragement and thought provoking interactions. I would like to appreciate his nature of providing freedom and appreciation to students, having confidence in students and utmost patience, by which I am benefited to a maximum extent. I am also grateful to all the Research group of Sanlab Infotech Pvt. Limited Bangalore for their encouragement and advice throughout the course of this research work. I am grateful to Dr. S. Ramachandran, joint supervisor, Director, NAE and formerly from Indian Institute of Technology Madras for making available all the facilities of the Lab. and also for his constant encouragement, advice and moral support. I am also grateful to all the Research group of NAE for their encouragement and advice throughout the course of this Research work. I wish to record my thanks to Dr. P Aravindan, Dean (Research), and Dr. Ravi, Prof. and HOD, Department of Electronics and Communication, Dr MGR University, Chennai, for their valuable suggestions during the research work. I am highly grateful to his holiness Jagadguru, Sri Sri Sri Padma Bhushan Dr. Balagangadharanatha Maha Swamiji President Sri Adichunchangiri trust and Sri Sri Prakashanatha Swamiji, the Managing Director of our college for their blessings.

8 viii I am also grateful to Dr. Puttaraju, Principal, SJBIT Kengeri, Bangalore for his valuable suggestions, affection and encouragement to carry out my Research work. I take this opportunity to thank the technical and administrative staff of the Deportment of E&C for helping me in many respects during the course of my Research work. Also, I am Thankful to Mr. Vinay, librarian and other library staff for helping me in utilizing the library facilities during the course of my Research work. I am highly thankful to Mrs. Nagarathna, Librarian, IISc for helping me in utilizing the IISc library facilities. I wish to express my deep sense of gratitude to my parents K.R. Ramaswamy and H. M. Sharadhamma, wife G.L. Bhagyalakshmi, Sister Prof. K. R. Rekha and brother in- law Udayakumar for supporting me in my Research work. My special thanks are due for my daughters K. N. Thanmaya, K. N. Sukhi and Niece Varsha U and Nephew Surya U, who innocently watched and missed me many times due to my pre-occupation with my research work. Finally, I am Thankful to all those who have helped me directly or indirectly during the course of my Research work. Bangalore February 2010 K. R. Nataraj

9 ix TABLE OF CONTENTS CHAPTER NO. TITLE BONAFIDE CERTIFICATE DECLARATION ABSTRACT ACKNOWLEDGEMENTS TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATION PAGE NO. i iii iv vi viii xiii xiv xvii 1 INTRODUCTION ADVANCED ON-BOARD PROCESSING (OBP) SATELLITE SYSTEMS EXISTING SATELLITE RECEIVER LITERATURE REVIEW Distributed Arithmetic (DA) Historical Perspective of DA Digital Frequency Synthesizer MOTIVATION AND OBJECTIVE OF THIS WORK Motivation Objectives ORGANIZATION OF THE THESIS 14

10 x 2 DEVELOPMENT OF ALGORITHMS FOR DEMODULATOR CARRIER FREQUENCY OFFSET ESTIMATION Review Signal Model Recursive Least Squares Based Estimation Unwrapping the Angles TIMING RECOVERY Modified Peak Average Energy Criterion Effect of Frequency offset Estimate on Timing Recovery TRACKING AND SYMBOL DETECTION Least Mean Square Algorithm 29 3 RECEIVER STRUCTURE AND TASK PARTITIONING IF TO BASE BAND CONVERSION BASIC DIGITAL APPROACH TO QUADRATURE DEMODULATION Sampling Frequency Selection In-phase and Quadrature Digital Filters DOWN-CONVERSION OF FREQUENCY PROPOSED SYSTEM ARCHITECTURE FOR DEMODULATOR PERFORMANCE TASK PARTITIONING Introduction FPGA-Based DSP Accelerator 43

11 xi Digital Filter Design FPGA Based Filters A RE-LOOK AT THE PROPOSED DEMODULATOR SYSTEM ARCHITECTURE 47 4 IMPLEMENTATION OF SAMPLING RATE CONVERTER 4.1 WORD-LENGTH ISSUES 4.2 DISTRIBUTED ARITHMETIC (DA) Convolutional Distributed Arithmetic Distributed Arithmetic With offset-binary Coding (DA-OBC) Modified DA-OBC Architecture 4.3 ROM DECOMPOSITION FOR DISTRIBUTED ARITHMETIC 4.4 SAMPLING RATE CONVERTER ARCHITECTURE Detailed Design Description of I-Channel Block 4.5 RESULTS IMPLEMENTATION OF DIGITAL FREQUENCY SYNTHESIZER INTRODUCTION BASIC IDEA OF DFS 73

12 xii 5.3 MODULATION CAPABILITY OF DFS BLOCKS OF DIGITAL FREQUENCY SYNTHESIZER Phase Accumulator Phase to Amplitude Converter EXPLOITATION OF SINE FUNCTION SYMMETRY 5.6 ANALYSIS CONCEPT OF THE ARCHITECTURE USED DESCRIPTION OF THE ARCHITECTURE 5.9 RESULTS IMPLEMENTATION OF FPGA PART OF THE DEMODULATOR 6.1 INTRODUCTION 6.2 IMPLEMENTATION OF MIXER AND RRC FILTERS USING VERILOG ON XILINX FPGA Design Hierarchy RESULTS OF HARDWARE DEMODULATOR 7.1 VERIFICATION 93 93

13 xiii 8 CONCLUSION AND SCOPE FOR FUTURE WORK CONCLUSION CONTRIBUTIONS OF THE PRESENT WORK SCOPE FOR FUTURE WORK 127 APPENDIX A 129 REFERENCES LIST OF PUBLICATIONS VITAE

14 xiv LIST OF TABLES TABLE NO. TITLE PAGE NO. 4.1 Contents of ROM for N = Contents of ROM with DA (N = 4) Contents of ROM with DA OBC Coding (N = 4) Modified DA-OBC ROM Contents (N = 4) Linear Segment Coefficients for 60 db Purity Signal Description Xilinx Place and Route Results 88

15 xv LIST OF FIGURES FIGURE NO. TITLE PAGE NO Basic repeater (bent-pipe) satellite link elements Existing System Received symbols when receiver demodulates (a) with constant Phase error and (b) with a wrong frequency ' Phase trajectory of θ ( k ) versus k (a) in the absence of noise and (b) in the presence of noise 2.3 Phase wrapping (a) in the absence of noise and (b) in the presence of noise 2.4 Structure to calculate the phase angle between two adjacent Samples 2.5 (a) Training Sequence (b) Absolute of training Sequence Absolute of training sequence when 2.7 (a) τ 6 0 min < (b) τ 6 0 min > Rotating Constellation Points LMS Structure Analog Quadrature Demodulator Block Diagram Spectra for Analog Quadrature Demodulation 34

16 xvi 3.3 Digital Quadrature Demodulator IF to Base-band Converter System Overview of Architecture for Demodulator Modified System Structure BER curves Basic DSP Device Task Partitioning for Implementation of the Demodulator on FPGA and DSP Eye-Pattern Measurement Effect of Filter Coefficient Word Length on Eye- Pattern Architecture for Computing inner Product of two Length N vectors using Distributed Arithmetic Architecture for Computing inner Product of two Length-N vectors using Distributed Arithmetic 58 with Offset Binary Coding 4.5 Modified DA-OBC Architecture (n=4) Decomposing 2n Sized ROM into n/k ROMs of size 2K words In-Phase Channel for Decimation by two Quadrature-Phase Channel for Decimation by two Combined Simplified Structure Telescopic View of I-Channel Block Implementation Internal Organization of Module A Internal Organization of Scaling Accumulator Demodulator out put 69

17 xvii 4.14 Response of I-Channel Block in MATLAB and VERILOG to (a) Impulse input (b) Random Input Sequence 5.1 DFS Block Diagram and Wave Shapes DFS Architecture with Modulation Capabilities Detailed Diagram of DFS Phase Addresses with ½ LSB phase offset DFS Architecture Output Spectrum Block Diagram of FPGA part of the Demodulator Synthesis RTL View of FPGA part of the Demodulator 7.1 Blocks of the part of the Demodulator implemented using Verilog and the Matlab modules for its verification 7.2 To 21 Matlab and Verilog Response of I and Q Channels at 2 KHz to 20 KHz 7.22 Top Level of the FPGA Part of the Demodulator Internal of top level Synthesis RTL View of FPGA Part of the Demodulator Clock Generator Internal Synthesis RTL View of 112 FPGA 7.25 ROM Internal level ROM Internal level ROM Internal level ROM Internal level Internal View of Mixer Design summary of Demodulator

18 xviii LIST OF ABBREVIATIONS AWGN ASIC ADC BET BB BPSK CMOS CLB CORDIC DCT DSP DA DFS DFT FFT FPGA FIR HPA ISI IF I I R IC LUT LSB LNA LPF Additive White Gaussion Noise Application Specific Integrated Circuits Analog to Digital Converter Bit Error Rate Base Band Binary Phase Shift Keying Complementary Metal Oxide Semiconductor Configurable Logic Blocks Coordinate Rotation Digital Computer Discrete Cosine Transforms Digital Signal Programming Distributed Arithmetic Digital Frequency Synthesizer Discrete Fourier Transform Fast Fourier Transform Field Programmable Gate Array Finite Impulse Response High Power Amplifier Inter Symbol Interference Intermediate Frequency Infinite Impulse Response Integrated Circuit Look up Table Least Significant Bit Low Noise Amplifier Low Pass Filter

19 xix LMS MAC MF MPU MSB OBP OBC PAEC QOS QPSK ROM RRC RLS RTL VLSI PLL Least Mean Square Multiply and Accumulate Matched Filter Microprocessor Units Most Signifying Bit On Board Processing Offset-Binary Coding Peak Average Energy Criterion Quality of Service Quadrature Phase Shift Keying Read Only Memory Root Raised Cosine Recursive Least Square Algorithm Resister Transistor Logic Very Large Scale Integrated Circuit Phase Locked Loop