High speed all digital phase locked loop (DPLL) using pipelined carrier synthesis techniques

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1 High speed all digital phase locked loop (DPLL) using pipelined carrier synthesis techniques T.Kranthi Kiran, Dr.PS.Sarma Abstract DPLLs are used widely in communications systems like radio, telecommunications, computers and other electronic applications. Digital PLLs are a type of PLL used to synchronize digital signals. While DPLLs input and outputs are typically all digital, they do have internal functions which are dependent on analog signals. This project deals with the design of pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex Digital Phase Locked Loop (DPLL). For on-chip application, the area reduction in proposed design can is achieved through optimization in the number of micro rotations. For better loop performance of second order complex DPLL and to minimize quantization error, the numbers of iterations are also optimized. Modelsim Xilinx Edition (MXE) and Xilinx ISE will be used simulation and synthesis respectively. The Xilinx Chipscope tool will be used to test the FPGA inside results while the logic running on FPGA. The Xilinx Spartan 3 Family FPGA development board will be used this project. Index Terms CORDIC, Digital Signal Processing, Pipelined Architecture, DPLL, Micro-rotation, Loop performance. I. INTRODUCTION CORDIC algorithm was first developed by Jack E. Volder in 1959 [1]. CORDIC algorithm is extremely useful in efficient and effective implementation of DSP systems [2]. This algorithm allows implementation of trigonometric functions like sine, cosine, magnitude and phase with great precision by using just simple shift and adding operations [1-4]. Although the same functions can be implemented using multipliers, variable shift registers or Multiply Accumulator (MAC) units, but CORDIC can implement these functions efficiently while saving enough silicon area which is considered to be primary design criteria in VLSI technology. This paper designs first order complex DPLL using CORDIC which functions as a FSK demodulator [6]. In digital PLL, an adjustable local sine wave generator and phase detector is required. The sine and cosine terms can be calculated using Manuscript received jan2, T.Kranthi Kiran, M.Tech VLSI-SD, Aurora Technological and Research Institute, JNTUH, Hyderabad, India, Mobile No: Dr.PS.Sarma, professor of ECE Department & Dean of Academics, Aurora Technological and Research Institute, JNTUH, Hyderabad, India, Mobile No: polynomial approximation, e.g. Taylor series. But it requires a considerable amount of hardware space on the silicon substrate. Interpolation method using table look-up may be the other solution. But it also requires large number of gates and ROM memory. The CORDIC offers the opportunity to calculate the desired functions in a simple and efficient way. Due to the simplicity of the involved operations, the CORDIC realization of complex DPLL is very well suited in VLSI hardware design and its implementation. This paper first describes the CORDIC algorithm and then pipelined architecture design [7]. Thereafter, implementation with adjustment of micro- rotation has been described. Finally CORDIC realization of a complex phase locked loop is described. II. CORDIC ALGORITHM The Volder s CORDIC algorithm [1] is derived from the general equations of vector rotation. The theory of CORDIC computation is to decompose the desired rotation angle into the weighted sum of a set of predefined elementary rotation angles. Each of them can be accomplished with simple shift add operation for a desired rotational angle θ. It can be represented for M iterations of an input vector (x,y) T setting initial conditions: x 0 =x, y 0 =y,and z 0 = θ as If zf=0 holds, then i.e. the total accumulated rotation angle is equal to θ. δ i, 0 1 M-1denote a sequence of ±1s that determine the direction of each elementary rotation. When M is the total number of elementary rotation angles, i-th angle α i is given 11

2 by: where m=0, 1 and -1 correspond to the rotation operation in linear, circular, and hyperbolic coordinate system respectively. For a given value of θ, the CORDIC iteration is given by: where α i = tan i. In case of counter clockwise rotation of a vector, the recursively updated equations are CORDIC architecture [4] only adder/ subtractor is used. The shift operations are hardwired using permanent oblique bus connections to perform multiplications by 2 -i. The precomputed values, as given in Table I, of i-th iteration angle α i required at each module is stored at a ROM memory location. The delay is adjusted by using proper bit-length in the shift register. Since no sign detection is needed to force zf=0, the carry save adders are well suited in this architecture. The use of these adders reduces the stage delay significantly. With the pipelining architecture, the propagation delay of the multiplier is the total delay of a single adder. So ultimately the throughput of the architecture is increased to many folds as the throughput is given by: 1/(delay due to a single adder). If an iterative implementation of the CORDIC is used, the processor would take several clock cycles to give output for a given input. But in the pipelined architecture, each pipeline stage takes exactly one clock cycle to pass one output [5]. The equations can be simplified in the form of : Here, tan α i is restricted to ± 2 -i. Thus, multiplication is transformed to an arithmetic right shift. Since cosine is an even function, therefore cos(α )= cos( α ) The iterative equation can be reduced to- Where is known as gain factor for each iteration. If M iterations are performed, then scale factor, K, is defined as the multiplication of every Ki. So, The elementary functions sine and cosine can be computed using the rotation mode of the CORDIC algorithm if the initial vector starts at ( K,0) with unit length. The most recurrent problem for a CORDIC implementation is overflow. Since the first tangent value is 2 0 =1 then rotation range will be [ π /2,π/ 2]. The difference in binary representation between these two angles is one bit.overflow arises when a rotational angle crosses a positive right angle to a negative one. To avoid overflow, an overflow control is added. It checks for the sign of the operands involved in addition or subtraction and the result of the operation. If an overflow is produced, the result keeps its last sign without affecting the final result. In the overflow control, the sign of z i determines whether addition or subtraction is to be performed. III. PIPELINED ARCHITECTURE OF CORDIC In Pipelined CORDIC architecture, number of rotational modules are incorporated and each module is responsible for one elementary rotation. The modules are cascaded through intermediate latches (Fig. 1). Every stage within the pipelined 12

3 ( a ) ( c ) Fig 2 : Simulation Results of All DPLL ( b ) 13

4 IV. BLOCK DIAGRAM OF ALL DPLL Fig 3: Top Level Block Diagram All DPLL Proposed All DPLL consists of: 1. DDS 2. Filters 3. Arc tan estimator 4. Loop Filter (PID controller) 1. DDS Fig 4: Basic Block Diagram of DDS DDS is used for carrier generation. All the blocks are connected with common clock and reset signals. The delta phase value decides the phase increment for each clock pulse. Hence decides the resulting signal frequency. The Frequency modulating instantaneous value is added to the delta phase value which causes instantaneous change in frequency. Due to the digital nature of the modulator only at each clock tick the modulating signal value shall affect the resulting frequency. The phase accumulator produces accumulated phase value for each clock pulse. In case if the DDS is used for phase modulation then instantaneous phase modulating signal value is added to the phase output of phase accumulator. This resulting phase value is given to the four Look Up Tables. Each Look Up Table is configured to produce a specific waveform. The outputs of four Look Up Tables are given to the input lines a 4 to 1 Multiplexer. This multiplexer connects one of the inputs to the output depending on the select lines. The output of Multiplexer consists the 8 amplitude bits which is the final output in case required modulation schemes are FM or PM. In case of Amplitude modulation, the output of Multiplexer is multiplied with instantaneous modulating signal. In three modulation schemes if modulating signal is analog in nature then an appropriate Analog to Digital converter is required to convert into 8 bit digital output. From the figure 4 the basic blocks in DDS can be identified as PIPO registers, adders, Look Up Tables and other combinational circuits. The ModelSim tool from Mentor Graphics is used, for simulation and functional verification of DDS. VHDL has been used as design entry method for all these blocks. Xilinx ISE (Integrated Software Environment) XST (Xilinx Synthesis Tool) is used as a synthesis tool to implement the design on Spartan-3E FPGA. Chipscope pro is used for analyzing the implemented design. 14

5 a.pipo n bit generic register: The Parallel in Parallel Out shift register cells are required in phase accumulator block to hold frequency and phase values. Synchronization is required between the phase increment register and phase register. This is achieved by connecting a common clock signal. Generic is used in VHDL implementation which allows to instantiate the PIPO component any bit size. b. N bit generic adder: The N-bit generic adder is implemented in VHDL with simple ripple carry adder logic. The adder is tested with inputs A=011001, B= and output observed is Z = c. Phase Accumulator: The phase accumulator consists of phase increment register, adder and phase register. four look up tables are same. The output of modulator is given to the demodulator. 2. FILTERS The carrier waves (Cosine and Sine) that are generated by DDS core is given as input to the filter. The direct form of FIR filter is standard linear convolution, which described the output as convolution of input and impulse response of the filter. y[n] = x[n]*c[n] = x[k]c[n-k] = c[k]x[n-k]. Where c[n] values represent filter coefficients, and x[n] represents the input samples. Fig 5: Phase Accumulator The phase increment register stores the instantaneous phase increment values resulting from frequency modulation control block. This is fed to a 8 bit adder as one of its input. The other input for adder is phase register output. The phase register holds the instantaneous phase for each clock pulse. The accumulated phase also is represented by 8 bits, which limits the maximum phase by , and addition by 1 to maximum value causes the phase to become This is expected and desired since the Look Up Tables are programmed to consider 255 as highest phase value and phase increment by one results next cycle of waveform. Since 8 bits are used to represent the 0 O to 360 O the increment in digital phase value by one causes effective increment of O (results by dividng 360 O with 256 maximum possible combinations of 8 bits). This also implies that outputs can t have more that 256 samples for one cycle. The output of phase accumulator when the phase increment value is (decimal four) is given in figure 3.5. It can be observed that the resulting phase value after each clock pulse is four added to the previous phase value. In the following figure initial phase is 0 and further with clock pulses resulting in 4,8,12,16... d. Look up Tables: Four Look up Tables are implemented to produce four different output waveforms, namely sine wave, square wave, triangular wave and arbitrary waveform. As a standard practice these LUTs are implemented using VHDL CASE statement. Matlab is used for calculating the amplitude bits from the corresponding phase bits. Since the generation of square wave requires producing only two amplitude levels in one cycle, it can be implemented without Look up Table. It is possible to implement any arbitrary waveform, by appropriately changing the content of LUT. The ports of all Fig 6: Direct form 6-tap FIR filter Finite impulse response (FIR) filters are the most popular type of filters implemented in software. Filters are signal conditioners. Each functions by accepting an input signal, blocking prespecified frequency components, and passing the original signal minus those components to the output. A digital filter takes a digital input, gives a digital output, and consists of digital components. In a typical digital filtering application, software running on a digital signal processor (DSP) reads input samples from an A/D converter, performs the mathematical manipulations dictated by theory for the required filter type, and outputs the result via a D/A converter. 3. ARC TAN ESTIMATOR The outputs of filters are given to this module. atan(y / x) returns in radians. The result is between -pi and pi. The vector in the plane from the origin to point (x, y) makes this angle with the positive X axis. The point of atan2 () is that the signs of both inputs are known to it, so it can compute the correct quadrant for the angle. For example, atan (1) and atan2 (1, 1) are both pi/4, but atan2 (-1, -1) is -3*pi/4. The ATAN function returns the angle, expressed in radians, whose tangent is X (i.e., the arc-tangent). If two parameters are supplied, the angle whose tangent is equal to Y/X is returned. For real input, the range of ATAN is between -/2 and /2 for the single argument case and between - and if two arguments are given. In the single argument case with a complex number, Z = X + iy, Syntax: Result = ATAN(X [, /PHASE] ) 15

6 4.LOOP FILTER A proportional integral derivative controller (PID controller) is a generic control loop feedback mechanism (controller) widely used in industrial control systems a PID is the most commonly used feedback controller. A PID controller calculates an "error" value as the difference between a measured process variable and a desired set point. The PID controller calculation (algorithm) involves three separate constant parameters, and is accordingly sometimes called three-term control: the proportional, the integral and derivative values, denoted P, I, and D. Histically, these values can be interpreted in terms of time: P depends on the present error, I on the accumulation of past errors, and D is a prediction of future errors, based on current rate of change. The weighted sum of these three actions is used to adjust the process via a control element such as the position of a control valve or the power supply of a heating element. Table-2: Effects of increasing a parameter independently The response from arctan estimator is given to Loop filter. This helps in minimizing the error. The output is given to filter block. V. CONCLUSION The proposed VLSI implementation of high performance digital phase locked loop based FM receiver has been designed so that it can meet the constraint for the application in personal wireless communication, very high frequency signal processing field. The circuit requires only 3.5K slices for implementation and it can operate at maximum frequency of 50 MHz. Xilinx xc3s500e-5fg320 devices has been used as the target device for FPGA implementation and XST has been used as a synthesis tool. Here it is concluded that the designed high performance FM receiver can be easily fitted into the next generation communication receiver circuit where low-power and minimum hardware utilization with the maximum clock. frequency is the key concern. As future work, This work can be extended in order to increase the accuracy by increasing the speed of modem. The cost also can be reduced by simplifying the circuit complexity by making simple design. REFERENCES Fig 7: PID Block Diagram In theory, a controller can be used to control any process which has a measurable output (PV), a known ideal value for that output (SP) and an input to the process (MV) that will affect the relevant PV. Controllers are used in industry to regulate temperature, pressure, flowrate, chemical compositi on, speed and practically every other variable for which a measurement exists. The loop filter/loop controller used is PID Controller. The transfer function of the PID controller looks like the following: The values are Kp = Proportional gain KI = Integral gain Kd = Derivative gain [1] J.E. Volder. "The CORDIC Trigonometric Computing Technique". IRE Transactions on Electronic Computing, vol EC-8, pp , Sept [2] Y.H. Hu. "CORDIC-Based VLSI Architectures for Digital Signal Processing" IEEE Signal Processing Magazine, Vol. 9, No. 3, pp , [3] Andraka R.A., "Survey of CORDIC Algorithms for FPGA Based Computers, Proceedings of the 1998 ACM/SIGDA 6 th International Symposium on FPGAs, pp , Monterey, California, Feb.22-24, [4] S.Wang, V.Piuri, E.E.Swartzlander. Jr.,"Granularly-pipelined CORDIC processors for sine and cosine generators, IEEE International Conference on Acoustics, Speech, and Signal Processing ICASSP, vol. 6, pp , [5] M. Chakraborty, A. S. Dhar and Moon Ho Lee, A Trigonometric Formulation of the LMS Algorithm for Realisation of Pipelined CORDIC, IEEE Trans. Circuits and Systems, vol. 52, no. 9, pp , Sep [6] Vuori J., Implementation of a Digital Phase-Locked Loop Using CORDIC Algorithm, IEEE International Symposium on Circuit and Systems, Atlanta, USA 1996, pp.iv [7] A. Mandal, K.C. Tyagi, B.K. Kaushik, VLSI Architecture Design and Implementation for Application Specific CORDIC Processor, 2nd IEEE International Conference on Advances in Recent Technologies in Communicaion and Computing (ARTCom),pp , Oct 16-17, kp is " " with Q7 format ki is " " -- in Q7 format kd is " " with Q7 format 16