FINITE IMPULSE RESPONSE (FIR) FILTER

Transcription

1 CHAPTER 3 FINITE IMPULSE RESPONSE (FIR) FILTER 3.1 Introduction Digital filtering is executed in two ways, utilizing either FIR (Finite Impulse Response) or IIR (Infinite Impulse Response) Filters (MathWorks products Simulink, A FIR Filter is a crucial sort of channel that is utilized as a part of DSP (Digital Signal Processing) over IIR channel. The reaction of such a channel is limited in view of the non -attendance of criticism (J. G. Proakis, D. G. Manolakis 1996). Applications of FIR filter includes video and communication systems because of guaranteed stability, absence of overflow oscillations, ability to implement filters with linear phase response, ease of implementation, computational efficiency achieved to great level, possible to implement filters with coefficients less than one. Also FIR filters are the key ingredient of DSP which are used in the applications such as signal pre-processing, antialiasing, band selection, interpolation (increasing the sampling rate) and low pass filtering. FIR filter becomes the best choice when there should not be any noise in the filter as there is no necessity of truncation or rounding of the bits after multiplication (Xilinx system generator, DSP user guide, MATLAB based Simulink Tool outlines the model based chart and reproduction, mechanized code era and check of relating configuration on top of the line FPGA's. Channel Design and Analysis (FDA) Tool is an effective device in MATLAB Signal Processing Tool box, with the assistance of which we can outline and break down various sorts of filters.(mathworks products Simulink, /products/simulink/). The late advance in programming apparatus improvement is to bolster DSP applications broadly in FPGA's. Framework Generator for DSP is the Industry's driving abnormal state apparatus for planning elite DSP frameworks utilizing FPGA's 20

2 (Xilinx system generator, DSP user guide, Generator instrument gives Simulink libraries to outline Arithmetic, Logical, Mathematical, Memory squares and DSP capacities (James Hwang,Jonathan Ballagh). The DSP capacities incorporate FIR Filters and Transforms. The outlining of a Filter basically involves two fundamental strides that finish the configuration procedure. The initial step is the era of coefficients and the second step constitutes the re-enactment of channel utilizing the created coefficients. In spite of the fact that FIR Filter outline is confound, the focal points persevering permits them to be broadly utilized for sifting applications when contrasted with IIR channels. IIR channels don't give security at higher requests while the FIR partners are constantly steady and are especially valuable for applications which require definite direct stage reaction (Ritu Saroha, Surender Dhiman 2013: ). The FIR filter represented by Eqn (3.1) has a general structure as shown in Fig 3.1. (3.1) Where the output of the filter is, is the input data, are the filter coefficients and N represents number of filter coefficients or taps. The filter structure requires N multipliers and (N-1) adders for the implementation. An FIR Filter structure of Fig 3.1 consists of multipliers, adders and delay elements. Implementation of multipliers on FPGA consumes large area; also the design of multipliers is a complex task which requires large resources resulting in high cost. (n-1) (n-2) (n-n+1) Z -1 Z -1 Z -1 Z -1, Fig 3.1 General FIR Filter structure. 21

3 The main operation involved in the design of digital FIR filter is the estimation of transfer functions of filter coefficients which finalise the filter response (Anurag Aggarwal,Astha Satija, Tushar Nagpal 2013:37-41). Pipelining and parallel processing techniques is used in FIR filter where pipelining is implemented using delay elements. Although the techniques result in increase of the overall speed of the system, it marks increased hardware requirement due to insertion of delay elements and latency. Multiple inputs are processed for every clock cycle providing multiple outputs (parallel processing) which would again grade in increased hardware complexity. The output of the FIR filter is the unit convolution sample answer by a system along with the signal input. Hence multiplication is one of the strongest operations that are performed in FIR filter. Traditional DSP based FIR filter implementation constituted a MAC (Multiply and Accumulate) unit. Multiplier implementation on FPGA (Field Programmable Gate Array) fundamentally requires large chip area with increased power consumption. Implementation of FIR filter with reduced chip area with faster response and reduced power consumption was a challenge to be addressed (M. Yazhini,R. Ramesh 2013: ).The design of FIR filters with MAC unit based on multipliers has a reduction in throughput as the number of filter tap increases and also, with increase in filter length, the sampling rate decreases. The challenge now is to implement an FIR filter operation without the use of multipliers because of the above mentioned drawbacks. Several methods have been proposed for multiplier less implementation of FIR filter, as detailed below: Canonic Sign Digit method: Coefficients are spoken to by a blend of forces of two in a manner that increase, can be essentially actualized with adders/subtractors and shifters. Dempster-Mcleod method: The method is similar to Canonic Sign Digit method but with usage of less number of adders. LUT based approach Distributed Arithmetic (DA) method: Use of (RAMs, ROMs) memories or (LUTs) Look-Up Tables to store precomputed values of filter coefficient for operations. 22

4 Designing an FIR filter using Distributed Arithmetic is one of the feasible solutions for the above mentioned challenges as it is a multiplier less technique. 3.2 FIR Filter Design Using System Generator Framework generator is an abnormal state framework outline device for making custom DSP hinders on FPGA effortlessly. Framework generator essentially gives two key devices: 1. Blocks for building the model. 2. Equipment generator model. Simulink gives a test domain to the outline (Evan Everett and Michael Wu 2013) TAP Filter Design Fig 3.2 demonstrates the model of 3-Tap Filter plan. The information is a Chirp sign which surrenders the frequency or down frequency with time and yield sign which is a straight Chirp signal (sine wave whose frequency changes directly with time).the configuration is a Low Pass 3-Tap FIR Filter utilizing Least Square technique as appearing in the Fig 3.2. Minimum Mean Square (LMS) calculation is utilized as part of versatile channels to discover the channel coefficients that identify with creating the slightest mean squares of the mistake signal (contrast between the sought and the genuine sign). It is one of the ideal channel plan techniques for planning a FIR Filter. The essential thought is to create the channel coefficients over and over until a specific blunder is minimized. The reason for large portion of the channel is to isolate the sought sign from undesired flag or commotion. As the vitality of the sign is identified with square of the sign, a squared blunder guess model is proper to upgrade the outline of FIR channels. The decision of LMS calculation lies in its effortlessness of usage, steady and powerful execution against various sign conditions. Fig 3.2 gives the general structure of basic 3-TAP FIR Filter based on the general equation of the filter consisting of four multipliers, three adders and three delay elements. 23

5 Fig 3.2 Model of 3-TAP Filter Design using System Generator. The information signal frequency is 100MHZ and the frequency particulars of Filter are as per the following: Fs(Sampling Frequency)=48000 Hz, Fpass(Pass band Frequency) =9600Hz, Fstop (Stop band Frequency) =12000Hz.The coefficients are produced by utilizing FDA instrument. The coefficient qualities are sent out to MATLAB workspace and stocked up in variable named Num. Num contains 4 coefficients as given below in Table 3.1. Table 3.1 Coefficient values of 3-TAP Filter Design. Coefficient values

6 Parameters selected for the input signal for the design is as given in Table 3.2. Table 3.2 Input signal Parameters for 3 -Tap filter. Input signal: chirp signal Initial frequency (Hz): Target time (secs): 500 Frequency at target time (Hz): 1 Parameters selected for the Coefficient generation of 3-TAP Filter design is as presented in Table 3.3. Table 3.3 Parameters for the Coefficient generation for 3-TAP Filter Design. Response Type Low Pass Design Method FIR-Least Squares Filter Order 3 Frequency spec(hz): Fs Fpass 9600 Fstop Magnitude Spec: Wpass 1 Wstop 1 The result of 3-TAP Filter Design using System Generator is as given in Fig

7 Fig 3.3 Result of 3-TAP Filter design using System Generator. The Top graph in the Fig 3.3 represents input signal, the figure in the bottom graph shows the filtered output, where only low frequency signals are passed to the output with all the high frequency signals suppressed (from 0 to 260(approximately) in time scale on the graph above). Fig 3.4 represents Magnitude v/s Frequency response for 3-TAP Filter design. Fig 3.4 Magnitude v/s frequency response for 3-TAP Filter Design. 26

8 Fig 3.5 presents the simulation results of 3- TAP Filter design using Verilog code. Fig 3.5 Simulation results using auto generated Verilog code by System Generator for 3- TAP Filter Design. The digital simulation result consists of input clock signal(clk_net), four filter coefficients(gateway_in1_net[15:0],gateway_in2_net[15:0], gateway_in3_net[15:0], gateway_in4_net[15:0]), input signal (gateway_in_net[15:0]),output signal (gateway_out_net[34:0]). Input is applied on positive edge of the clock (205ns) where as output is obtained at 235ns on positive edge of the clock with a delay of 30 ns. The hardware device utilisation of developed 3-TAP filter on FPGA is represented in Fig 3.6. It is observed that 204 slices and 227 LUT s with zero Block Ram s (BRAMS) is utilised by the design. 27

9 Fig 3.6 Design utilization for the 3-TAP Filter using System Generator. (Device Selected: XC3S400-3PQ208) TAP Filter Design Fig 3.7 gives the general structure of basic 6 - TAP FIR Filter consisting of seven multipliers, six adders and six delay elements. Two input signals (Sine Wave, Sine Wave1) of different frequencies are applied as inputs with output obtained on Chip scope. Fig 3.7 Model of 6-TAP Filter design using System Generator. 28

10 Parameters selected for the input signals for the design is as given in Table 3.4 below. Table 3.4 Input signal Parameters for 6 - Tap filter. Input signal 1 Sine type Time (t) Time Based Simulation Time Amplitude 1 Bias 0 Frequency (rad/sec) (2*pi)/100 Phase (rad) 0 Sample time Input signal 2 Sine type Time Based Time (t) Simulation Time Amplitude 1 Bias 0 Frequency (rad/sec) (2*pi)/200 Phase (rad) 0 Sample time Coefficient values selected for 6-TAP Filter design is as given in Table 3.5. Table 3.5 Coefficient values for 6-TAP Filter design. Coefficients

11 Fig 3.8 Results of 6-TAP Filter design using System Generator. In the figure above, top graph is one of the input signals, middle graph represents combination of both the inputs and bottom graph represents the output of the 6 -Tap filter which is same as the combined signal graph. Since the frequencies of both the signals are within the range of specification of the filter design (Table 3.4), output follows the input. Parameters selected for the Coefficient generation for 6 -TAP Filter design is as given in Table 3.6. Table 3.6 Parameters for the Coefficient generation for 6-TAP Filter Design. Response Type: Design Method Low Pass FIR-Equi ripple Filter Order 6 Frequency spec(hz): Fs Fpass 9600 Fstop Magnitude Spec: Wpass 1 Wstop 1 30

12 The Magnitude versus Frequency response is as shown in Fig 3.9 below. Fig 3.9 Magnitude v/s frequency response for 6-TAP Filter design. Fig 3.10 Simulation Results using auto generated Verilog code by System Generator for 6- TAP Filter Design. 31

13 The hardware device utilisation of developed 6-TAP filter on FPGA is represented in Fig 3.11 below. It is observed that 380 slices and 431 LUT s with zero Block Ram s (BRAM s) is utilised by the design TAP Filter Design Fig 3.11 Design utilization for the 6-TAP Filter using System Generator. (Device Selected: XC3S400-3PQ208) General structure of basic 8 Tap FIR Filter is as given in Fig 3.12 below. Fig 3.12 Model of 8-TAP Filter design using System Generator. 32

14 The Top module of Basic 8-tap filter is as given below in Fig Fig 3.13 Top Module of Basic 8-Tap filter. Fig 3.14 Simulation Results using auto generated Verilog code by System Generator for 8 - TAP Filter Design. In the figure above, the filter is sensitive for positive edge of the clock (clk), and negative edge of reset (rst). data_in represents input data to the filter, mem_addr represents filter coefficients and output data is in data_out. The output is obtained with a delay of 20 ns. The RTL Schematic of basic 8-tap filter is as shown in Fig 3.15 below. 33

15 Fig 3.15 RTL Schematic of Basic 8-Tap filter. Table 3.7 Design Summary of Basic 8-Tap filter. Logic Utilization Device Utilization Summary (Estimated values) Used Available Utilization Number of slices % No. of slice Flip- Flops No. of 4 input LUTs No. of bonded IOB s No. of MULT 18X18s % % % % No. of GCLKS % Table 3.7 provides the simulation device utilization of 8-Tap filter. From the Table, it is clear that the design has zero percent utilization of slices, slice Flip-Flops, LUT s there by providing area efficient design. 34

16 Timing Analysis of Basic 8-Tap filter is tabulated as given below in Table 3.8. Table 3.8 Timing Analysis of Basic 8-Tap filter. Speed Grade -5 Minimum period Minimum input arrival time before clock Maximum output required time after clock Maximum combinational path delay 4.019ns (Maximum Frequency: MHz) 7.138ns 6.216ns No path found Fig 3.16 gives the Routed design area. Fig 3.16 Routed Design Area of Basic 8-Tap filter. Static Power analysis from figure below shows that the complete design utilizes only 0.06 watts of power. Fig 3.17 Static Power Analysis of Basic 8-Tap filter. 35

17 Fig 3.18 gives both Simulation and Hardware implemented result. The top part of the graph represents simulation result and bottom graph represents hardware implemented result, which matches with the simulation results. Fig 3.18 Hardware verified results using chip scope-pro tool. Table 3.9 below gives the device utilization of the design on different FPGA s such as Spartan3 (XC3S400-5 PQ208), Virtex5 (5VLX110T-3 FF1136), Atrix 7(7A100T-3CSG324). Table 3.9 Different FPGA s Design utilization summary of Basic 8-Tap filter. Logic Utilization XC3S400-5 PQ208 5VLX110T- 3 FF1136 7A100T- 3CSG324 Number of Slice Registers Number of Slice LUTs Number of fully used LUT-FF pairs Number of bonded IOBs Number of MULT18X18s Number of BUFG/BUFGCTRLs

18 The timing analysis of the design on various FPGA s is as given in the Table Table 3.10 Different FPGA s Timing analysis summary of Basic 8-Tap filter. Timing parameters XC3S400-5PQ208 5VLX110T- 3FF1136 7A100T- 3CSG324 Minimum period (ns) 4.019ns Maximum Frequency (MHz) Setup time (ns) Hold Time (ns) TAP Filter Design Fig 3.19 Model of 12-TAP Filter design using System Generator. Fig 3.19 gives the general structure of basic 12-TAP FIR Filter consisting of thirteen multipliers, twelve adders and twelve delay elements. Two input signals (Sine Wave1, Sine Wave2) of different frequencies are applied as inputs with output obtained on Chip scope. 37

19 Parameters selected for the input signals for the design is as given in Table 3.11 below. Table 3.11 Input signal Parameters for 12 - Tap filter. Input signal 1 Sine type Time Based Time (t) Simulation Time Amplitude 1 Bias 0 Frequency (rad/sec) (2*pi)/100 Phase (rad) 0 Sample time Input signal 2 Sine type Time (t) Time Based Simulation Time Amplitude 1 Bias 0 Frequency (rad/sec) (2*pi)/1 Phase (rad) 0 Sample time Coefficient values of 12-TAP Filter design is chosen as mentioned in Table 3.12 below. Table 3.12 Coefficient values of 12-TAP Filter Design. Coefficients

20 Parameter selected for the Coefficient generation for 12-TAP Filter design is as given in Table Table 3.13 Parameters for the Coefficient generation for 12-TAP Filter Design. Response Type: Design Method Low Pass FIR-Equi ripple Filter Order 12 Frequency spec(hz): Fs Fpass 9600 Fstop Magnitude Spec: Wpass 1 Wstop 1 Fig 3.20 below gives the system generator results of 12-Tap filter. The top graph is a low frequency input signal, middle high frequency signal and bottom is low frequency output signal, which is same as the low frequency input signal there by implementing a low pass filter design. Fig 3.20 Results of 12-TAP Filter design using System Generator. 39

21 Fig 3.21 Magnitude v/s frequency response for 12-TAP Filter Design. Figure below gives the simulation results of 12-Tap filter. The digital simulation result consists of input clock signal(clk_net), filter coefficients(gateway_in1_net[15:0],gateway_in2_net[15:0], gateway_in3_net[15:0], gateway_in4_net[15:0] in the program), input signal (gateway_in_net[15:0]),output signal (gateway_out_net[34:0]). Input is applied on positive edge of the clock (205ns) where as output is obtained at 235ns on positive edge of the clock with a delay of 30 ns. Fig 3.22 Simulation Results using auto generated Verilog code by System Generator for 12-TAP Filter Design. 40

22 Figure below gives the hardware device utilisations of developed 12-TAP filter on FPGA. It is observed that 746 slices and 866 LUT s with zero Block RAM s is utilised by the design. Fig 3.23 Design utilization for the 12-TAP Filter using System Generator. (Device Selected: XC3S400-3 PQ208) 41