Real-time FPGA realization of an UWB transceiver physical layer

Transcription

1 University of Wollongong Research Online University of Wollongong Thesis Collection University of Wollongong Thesis Collections 2005 Real-time FPGA realization of an UWB transceiver physical layer Darryn W. Lowe University of Wollongong Recommended Citation Lowe, Darryn W, Real-time FPGA realization of an UWB transceiver physical layer, M. Eng. thesis, School of Electrical, Computer and Telecommunications Engineering, University of Wollongong, Research Online is the open access institutional repository for the University of Wollongong. For further information contact the UOW Library:

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3 REAL-TIME FPGA REALIZATION OF AN UWB TRANSCEIVER PHYSICAL LAYER A thesis submitted in fulfilment of the requirements for the award of the degree MASTER OF ENGINEERING RESEARCH from UNIVERSITY OF WOLLONGONG by Darryn W. Lowe, BEng (Hons 1) School of Electrical, Computer and Telecommunications Engineering 2005

4 I, Darryn W. Lowe, declare that this thesis, submitted in partial fulfilment of the requirements for the award of Master of Engineering Research, in the School of Electrical, Computer and Telecommunications Engineering, University of Wollongong, is wholly my own work unless otherwise referenced or acknowledged. The document has not been submitted for qualifications at any other academic institution. Darryn W. Lowe 14 November 2005 iii

5 Contents 1 Introduction Design Methodology Contributions A Novel UWB PHY MCIDS CCDM Specification Preamble SFD PHY Header Definition HCS Scrambling Symbol Mapping Prespreading CCDM Pilot Insertion MCIDS Spreading Spectral Mask Transmitter Top-Level Architecture v

6 3.2 Bus Interfacing Control Word Status Word Packet Buffer Header Preparation Header Timing Header Check Sum Scrambler Symbol Creation Symbol Buffer Constellation Mapping CCDM Spreading Architecture Control Separating I/Q Components MCIDS Buffering Pilot Insertion Preamble Generation Interleaving Spreading Transmitted Signal Receiver MCIDS Despreading MCIDS RAKE Frame Detection Equalization Automatic Gain Control DetectSFD vi

7 4.2 CCDM Demodulation Removing Pilots Buffering Despreading Constellation Demapping I/Q Buffer Demapping Header Processing Data Rate Management Descrambling Header Validation Bus Packet Buffer Control Registers Analysis Test Environment RF Front-end Models Channel Models MAC Models Performance AWGN Multipath Channel Sensitivity to Word Length Complexity Device Selection Synthesis Results Conclusions 167 A Transmitter Models 171 vii

8 B Receiver Models 187 C Parametrization Scripts 209 C.1 Constants C.1.1 Global Constants C.1.2 Parameters C.2 ROMs C.2.1 Transmitter CCDM Codeset ROM C.2.2 Receiver CCDM Codeset ROM C.2.3 Receiver MCIDS Codeset ROM C.2.4 Receiver Synchronization Codeset ROM C.2.5 Receiver RAKE Correlator Interleaver D Simulation 219 D.1 Functional Blocks D.1.1 CRC D.1.2 Scrambler D.1.3 Constellation Mapping D.1.4 CCDM D.1.5 Pilots D.1.6 Preamble D.1.7 MCIDS D.2 Simulation Framework D.2.1 Top-Level Simulation D.2.2 End-to-End Link Model D.2.3 Packet Constructor D.2.4 Transmitter Baseband Model D.2.5 Multipath Channel Model D.2.6 Receiver Front-end Model D.2.7 Receiver Baseband Model viii

9 List of Tables 2.1 Example of an MCIDS Spread Signal for M = N = Example of MCIDS Despreading for M = Preamble Sequence SFD Sequence PHY Header Definition Data Rate Mappings for PHY Header Initial Values for PRBS Normalization Constants for Symbol Constellations Prespread Codes Transceiver Spectral Mask Example of Buffer Signal Mask Generation Derivation of Header Control Signal Constants Data Bits for Modulation Types Relationship between Symbol Density and FIFO Reads Constellation Mapping for BPSK & QPSK Construction of Out Code Calculation of MCIDS Buffer Read Address BPSK Modulation of Preamble Bits Adder Coefficient Modification for RAKE Finger Correlator MCIDS Code ROM Synchronization Constants for RAKE Finger Correlators ix

10 4.4 State Machine in CCDM Control CCDM Despreading States for Delay Line Registers Adder Coefficients for 8-Chip CCDM Correlators CCDM 8-Chip Code ROM Summary of IEEE UWB Channel Model Properties Main Features of XC2VP70 FPGA Summary of Utilization of XC2VP70 FPGA Detailed Synthesis Results x

11 List of Figures 1.1 Transceiver Development Methodology Transceiver Block Diagram Example of CCDM Sequence Set for L=28 and K= PHY Frame Format Example of Spreading Process for PHY Header Bits-to-Symbol Mappings for BPSK, QPSK, 16-QAM and 64-QAM Codeset Definitions for CCDM and MCIDS Insertion of Pilots FCC Emissions Limit on UWB and Transceiver Spectral Mask Tx Overall Timing Transmitter Scrambler & HCS Timing TxMap Timing of Tx-Map-Buffer-Group A.22 Block FIFO Refilling Counter Synchronization Impact of Pre-spreading on Symbol Timing Timing of Transmitter s CCDM Spreading Architecture of CCDM Spreading Tx CCDM Spreader Timing Load Cycle Tx CCDM Spreader Timing Write Cycle Tx MCIDS Buffer Addressing xi

12 3.13 Impact of Pilots on Tx MCIDS Addressing Tx MCIDS Interleaver ASR Control Tx MCIDS Interleaver ASR Addressing Transmitted Signal for a QPSK packet with a payload of 384 bits Receiver State Machine Top-Level MCIDS Despreading Timing Architecture of RAKE Receiver Worst-Case 64-Finger RAKE Buffer Register Requirements Buffer Register Requirements for 32 RAKE Fingers Architecture of RAKE Finger Correlator MCIDS Despreading Control Timing RAKE Buffer for Preamble Correlation Frame Detection and Synchronization Timing Initialization of Channel Coefficient Timing Update of Channel Coefficient Timing Pilot Removal in Rx-CCDM-RemovePilots B Pilot Removal in Rx-CCDM-Buffer B Timing of Rx-CCDM B Control of Load Cycle in Rx-CCDM-Control B Architecture of CCDM 8-Chip Correlator Address Generation in Rx-DeMap-Addr B Compensating for Sub-rate Modulations Receiver Packet Buffer Writes in Rx-Bus-Parallel-BitCnt B Example RLC Circuit for Transmit Butterworth Filter Spectral Mask and Transmitted Power Spectral Density Matched Filter Performance Transmitter MAC State Machine Model OPB Bus Transactions During Transmission of a Packet xii

13 5.6 Receiver State Machine Eb Theoretical BER vs. N0 5.8 Eb Simulated BER vs. N0 5.9 Eb Simulated BER vs. in CM N0 Eb 5.10 Simulated BER vs. in CM N0 Eb 5.11 Simulated BER vs. in CM N0 Eb 5.12 Simulated BER vs. in CM N0 Eb 5.13 Simulated BER vs. for QPSK in all channels. N Simulated PER vs. ADC Bit Width xiii

14 List of Abbreviations ADC AGC ASR BER CCDM DAC DSSS FCC FCS FIFO FPGA HCS I ISI LNA LOS LSB LUT MAC MCIDS MPDU MRC Analog to Digital Convertor Automatic Gain Control Addressable Shift Register Bit Error Rate Complementary Code Division Multiplexing Digital to Analog Convertor Direct Sequence Spread Spectrum Federal Communications Commission Frame Check Sequence First-In First-Out Field Programmable Gate Array Header Check Sequence In-Phase Inter-Symbol Interference Low Noise Amplifier Line Of Sight Least Significant Bit Look Up Table Medium Access Control Multicode Interleaved Direct Sequence MAC Protocol Data Unit Maximal Ratio Combining xv

15 MSB NLOS OPB PAR PER PHY PRBS PSD Q RAM RF ROM RTL S-V SFD SIFS TDM UWB Most Significant Bit Non-Line Of Sight On-chip Peripheral Bus Place and Route Packet Error Rate Physical Layer Pseudo-Random Binary Sequence Power Spectral Density Quadrature Random Access Memory Radio Frequency Read Only Memory Register Transfer Level Saleh-Valenzuela Start Frame Delimiter Short Inter-Frame Spacing Time Division Multiplex Ultra-WideBand xvi

16 Abstract An original ultra-wideband (UWB) physical layer (PHY) specification is developed and implemented in digital logic. The novelty of this UWB PHY is based on a combination of complementary code division multiplexing (CCDM), which yields a low-interference signal with a variable process gain, and multicode interleaved direct sequence (MCIDS) spreading, which provides an additional fixed process gain as well as multipath robustness. To operate at the high sample rates needed for UWB, the digital logic, realized in a Virtex-II field programmable gate array (FPGA), has a highly-pipelined architecture for real-time signal processing. In addition, the gate count is minimized by avoiding the use of explicit buffer memory wherever possible. The performance of the transceiver is analyzed under a variety of UWB channels and impairments. It is concluded that the proposed UWB PHY offers robust performance in real-world environments and that it is viable for use in future communication systems. xvii

17 Acknowledgements Cry havoc! And let slip the dogs of war. Thanks to my supervisor, my family and my friends. xix