An FPGA Case Study: Narrowband COFDM Video Transceiver for Drones, UAV, and UGV. Produced by EE Times

Transcription

1 An FPGA Case Study: Narrowband COFDM Video Transceiver for Drones, UAV, and UGV #eelive Produced by EE Times

2 An FPGA Case Study System Definition Implementation Verification and Validation

3 CNR1 Narrowband COFDM Video Receiver for Surveillance and Law Enforcement CNT1 Narrowband COFDM Video Transmitter for Surveillance and Law Enforcement

4 Transmitter VAD COFDM Transmitter I/Q DAC Receiver Filter ADC I/Q COFDM Receiver VAD V = Analog NTSC or PAL Standard Definition Composite Video A = 2 Channels 25kHz 16 bit Audio D = up to 115.2kbps RS-232 type Data I/Q = complex baseband signal 4

5 Target Applications Close range, Non-LOS, Multipath Rapid Deployment Video Surveillance Body Worn Video Urban Environments Unmanned Ground Vehicle Systems Long range, Directional LOS Unmanned Air Vehicle Systems Low power, small form factor, low weight Commercial Off The Shelf (COTS)

6 COFDM Advantage over Legacy Coded Orthogonal Frequency Division Modulation (COFDM) Security 256 bit AES and proprietary Transmission Scheme Bandwidth Conservation Video, Audio and Data in 10% occupied bandwidth Multipath Immunity Leading Technology for Digital Broadcast DVB-T, DAB, WiMax (802.16)

7 Advantage over Competition Size and Power Efficiency Cost Security Scalability Bandwidth Conservation Sensitivity

8 COFDM VAD FEC Mapper IFFT FFT Prefix & Preamble I/Q Reed Solomon Encoder Symbol Interleaver Convolutional Encoder Viterbi Decoder Bit Interleaver

9 Transmitter / Receiver V SD Video P JPEG J Codec Codec Audio Codec A D COFDM Transmitter / Receiver I/Q DAC / ADC V = Analog NTSC or PAL Standard Definition Composite Video P = ITU-R BT.656 Pixel Video at 216Mbps J = JPEG 2000 compressed video 300 to 5500 Mbps A = 0-2 channels 16 bit Audio at 4 to 25 Khz (0 to 400 Mbps) D = UART data at 0 to BAUD (0 to 115 kbps) I/Q = complex baseband signal

10 COFDM Transmitter / Receiver J A D Application Layer Medium Access Controller PHY Layer I / Q External Interfaces J = 32 bit DMA A = 3 Wire Serial Slave D = UART Frame Buffers Overflow and Underflow Audio Compression Packetization Data Identification Data Protection Throttling Encryption

11 Carrier Frequency Offset Correction COFDM Receiver PHY Packet Detection Timing Training Symbol Data Training Symbol FFT Channel Estimation Data FFT Channel Equalization Pilot Tracking Demapper FEC

12 RF Requirements IF - I/Q Filter DAC Digital Down Converter Baseband - I/Q AGC Antenna Diversity Filter DAC Digital Down Converter AGC

13 An FPGA Case Study System Definition Implementation Verification and Validation

14 IP Sources Altera MegaCores FFT, Reed Solomon, Viterbi, Down Convert Filters Open Source Cordic Other Open Source AES, UART, I2C (opencores.org), CRC (easics.com) Literature and Matlab Modeling Convolutional Encoder, DPCM, CRC, Interleavers, AGC, Timing Correlation, Carrier Frequency Offset Correction, MRC Equalizer, Pilot Tracking, MLM Demapper

15 Sustainable and Extensible Design Modular Architecture PHY(COFDM,CDR1,CDR2) MAC (network capable) Applications(JAD,SPI,Ethernet) Consistent Hierarchical Schematics and Code Meaningful Variable Names, Parameterization and Text Macros Retarget Coding Schemes Bandwidth Optimization Internal Interfaces Common, Simple, Standard Altera IP uses Avalon Plan for managed Clock Domains to optimize power

16 Design Challenges Complex and Matrix Mathematics In Phase (I) QuadraturePhase (Q) FFT / IFFT Real (Re) Imaginary(Im) 64 QAM Constellation

17 Design Challenges Complex and Matrix Mathematics

18 Design Challenges Fixed Point Arithmetic = = = = = = = * 0.5 = * = * = * 2.0 = * = =

19 Design Challenges Cordic Usage (Re, Im) M A Re = M*COS(A) Im = M*SIN(A)

20 Design Challenges Fast Divide Reciprocal Multiplication, a tutorial, Douglas W. Jones, THE UNIVERSITY OF IOWA Department of Computer Science, 1999 A 24 bit reciprocal is estimated in 7 clock cycles using 795 registers

21 Design Challenges Optimizing Throughput and Resources Pipelining Resource Sharing

22 Design Challenges IP integration Black box IP FFT Did not follow Avalon Interface Viterbi Open Source IP 128 bit AES extended to 256 bit Cordic Scaling UART Page/Device Addressing Extensions ASIC IP JPEG Codec Functional sensitivity to reads and writes, both order and timing Frame creation and delivery had finicky flow control

23 Design Challenges Packet Error and Flow Control Video Audio Data Throttling Bandwidth Compression Rate Frames Per Second Handling Frame Loss at Delivery Synchronization to Video Handling Data Loss Application Must Support Data Loss

24 Not a Design Challenge Remote Design Team 2 Quad Core Workstations 8 Processes concurrently (Simulations or Compiles) VPN and VNC Dedicated LAB PCs for Evaluation LogmeIn and RDP Remote File access and desktop sharing Skype Inexpensive personal and conference style communications with additional desktop and file sharing Webcams Bench Evaluation and improved communications Ethernet Connected Instrumentation

25 An FPGA Case Study System Definition Implementation Verification and Validation

26 Validation of Coded Algorithms Using Excel to Develop Signal Processing Models (Analysis ToolPak)

27 Matlab vs Modelsim vs Bench Continuous Repeatable Transmission Mode Intermediate Data Capture Multiple Receiver Processing Points Stimulus and Results Comparison Conduit between all 3 Methods Captured Data Insertions to Matlab and/or Modelsim Simulations Matlab Generated Data Insertions into Modelsim

28 Regression Testing Targeted Testing AGC, Down Convert, Timing, CFO Application Layer MAC Layer PHY Layer Comprehensive Testing Rates, Modes, Configuration Stress Testing Randomized Stimulus Generated by Matlab Channel Models Modulation Scheme vs SNR, CFO, Delay Spread Automated Comparison of Quality of Results (QOR) Bit Error Rate (BER) Error Vector Magnitude (EVM)

29 Error Vector Magnitude (EVM)

30 Advanced Use of Signaltap Signaltap is a soft Logic Analyzer for Altera FPGA Xilinx has Chipscope with similar capabilities State Based Trigger and Sample Complex Trigger and Sample Conditions Segmented Captures Multiple Instances Simultaneous Capture at Different Rates

31 Advanced Use of Signaltap

32 Bench Instrumentation