Device Modeling for Analog and RF CMOS Circuit Design

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1 Device Modeling for Analog and RF CMOS Circuit Design Trond Ytterdal Norwegian University of Science and Technology Yuhua Cheng Skyworks Solutions Inc., USA Tor A. Fjeldly Norwegian University of Science and Technology

3 Device Modeling for Analog and RF CMOS Circuit Design

5 Device Modeling for Analog and RF CMOS Circuit Design Trond Ytterdal Norwegian University of Science and Technology Yuhua Cheng Skyworks Solutions Inc., USA Tor A. Fjeldly Norwegian University of Science and Technology

6 Copyright 2003 John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone (+44) (for orders and customer service enquiries): Visit our Home Page on or All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or ed to permreq@wiley.co.uk, or faxed to (+44) This publication is designed to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding that the Publisher is not engaged in rendering professional services. If professional advice or other expert assistance is required, the services of a competent professional should be sought. Other Wiley Editorial Offices John Wiley & Sons Inc., 111 River Street, Hoboken, NJ 07030, USA Jossey-Bass, 989 Market Street, San Francisco, CA , USA Wiley-VCH Verlag GmbH, Boschstr. 12, D Weinheim, Germany John Wiley & Sons Australia Ltd, 33 Park Road, Milton, Queensland 4064, Australia John Wiley & Sons (Asia) Pte Ltd, 2 Clementi Loop #02-01, Jin Xing Distripark, Singapore John Wiley & Sons Canada Ltd, 22 Worcester Road, Etobicoke, Ontario, Canada M9W 1L1 Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic books. British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library ISBN Typeset in 10/12pt Times by Laserwords Private Limited, Chennai, India Printed and bound in Great Britain by Antony Rowe Ltd, Chippenham, Wiltshire This book is printed on acid-free paper responsibly manufactured from sustainable forestry in which at least two trees are planted for each one used for paper production.

7 Contents Preface xi 1 MOSFET Device Physics and Operation Introduction The MOS Capacitor Interface Charge Threshold Voltage MOS Capacitance MOS Charge Control Model Basic MOSFET Operation Basic MOSFET Modeling Simple Charge Control Model The Meyer Model Velocity Saturation Model Capacitance Models Comparison of Basic MOSFET Models Basic Small-signal Model Advanced MOSFET Modeling Modeling Approach Nonideal Effects Unified MOSFET C V Model 37 References 44 2 MOSFET Fabrication Introduction Typical Planar Digital CMOS Process Flow RF CMOS Technology 60 References 67 3 RF Modeling Introduction Equivalent Circuit Representation of MOS Transistors High-frequency Behavior of MOS Transistors and AC Small-signal Modeling 78

8 vi CONTENTS Requirements for MOSFET Modeling for RF Applications Modeling of the Intrinsic Components HF Behavior and Modeling of the Extrinsic Components Non-quasi-static Behavior Model Parameter Extraction RF Measurement and De-embedding Techniques Parameter Extraction NQS Model for RF Applications 113 References Noise Modeling Noise Sources in a MOSFET Flicker Noise Modeling The Physical Mechanisms of Flicker Noise Flicker Noise Models Future Work in Flicker Noise Modeling Thermal Noise Modeling Existing Thermal Noise Models HF Noise Parameters Analytical Calculation of the Noise Parameters Simulation and Discussions Induced Gate Noise Issue 138 References Proper Modeling for Accurate Distortion Analysis Introduction Basic Terminology Nonlinearities in CMOS Devices and Their Modeling Calculation of Distortion in Analog CMOS Circuits 149 References The BSIM4 MOSFET Model An Introduction to BSIM Gate Dielectric Model Enhanced Models for Effective DC and AC Channel Length and Width Threshold Voltage Model Enhanced Model for Nonuniform Lateral Doping due to Pocket (Halo) Implant Improved Models for Short-channel Effects Model for Narrow Width Effects Complete Threshold Voltage Model in BSIM Channel Charge Model Mobility Model Source/Drain Resistance Model 169

9 CONTENTS vii 6.8 I V Model I V Model When rdsmod = 0(R DS (V ) 0) I V Model When rdsmod = 1(R DS (V ) = 0) Gate Tunneling Current Model Gate-to-substrate Tunneling Current I GB Gate-to-channel and Gate-to-S/D Currents Substrate Current Models Model for Substrate Current due to Impact Ionization of Channel Current Models for Gate-induced Drain Leakage (GIDL) and Gate-induced Source Leakage (GISL) Currents Capacitance Models Intrinsic Capacitance Models Fringing/Overlap Capacitance Models High-speed (Non-quasi-static) Model The Transient NQS Model The AC NQS Model RF Model Gate Electrode and Intrinsic-input Resistance (IIR) Model Substrate Resistance Network Noise Model Flicker Noise Models Channel Thermal Noise Model Other Noise Models Junction Diode Models Junction Diode I V Model Junction Diode Capacitance Model Layout-dependent Parasitics Model Effective Junction Perimeter and Area Source/drain Diffusion Resistance Calculation 204 References The EKV Model Introduction Model Features Long-channel Drain Current Model Modeling Second-order Effects of the Drain Current Velocity Saturation and Channel-length Modulation Mobility Degradation due to Vertical Electric Field Effects of Charge-sharing Reverse Short-channel Effect (RSCE) SPICE Example: The Effect of Charge-sharing Modeling of Charge Storage Effects Non-quasi-static Modeling 218

10 viii CONTENTS 7.8 The Noise Model Temperature Effects Version 3.0 of the EKV Model 220 References Other MOSFET Models Introduction MOS Model The Drain Current Model Temperature and Geometry Dependencies The Intrinsic Charge Storage Model The Noise Model The MOSA1 Model The Unified Charge Control Model Unified MOSFET I V Model Unified C V Model 241 References Bipolar Transistors in CMOS Technologies Introduction Device Structure Modeling the Parasitic BJT The Ideal Diode Equation Nonideal Effects 246 References Modeling of Passive Devices Introduction Resistors Well Resistors Metal Resistors Diffused Resistors Poly Resistors Capacitors Poly poly Capacitors Metal insulator metal Capacitors MOSFET Capacitors Junction Capacitors Inductors 260 References Effects and Modeling of Process Variation and Device Mismatch Introduction The Influence of Process Variation and Device Mismatch The Influence of LPVM on Resistors The Influence of LPVM on Capacitors The Influence of LPVM on MOS Transistors 269

11 CONTENTS ix 11.3 Modeling of Device Mismatch for Analog/RF Applications Modeling of Mismatching of Resistors Mismatching Model of Capacitors Mismatching Models of MOSFETs 273 References Quality Assurance of MOSFET Models Introduction Motivation Benchmark Circuits Leakage Currents Transfer Characteristics in Weak and Moderate Inversion Gate Leakage Current Automation of the Tests 285 References 286 Index 287

13 Preface We are fortunate to live in an age in which microelectronics still enjoy an accelerating growth in performance and complexity. Fortunate, since we are experiencing a remarkable progress in science, in communication technology, in our ability to acquire new knowledge, and in the many other wonderful amenities of modern society, all of which are permeated by and made possible by modern microelectronics. This exponential evolutionary trend, as described by Moore s Law, has now lasted for more than three decades, and is still on track, fueled by a seemingly unending demand for ever better performance and by fierce global competition. A driving force behind this fantastic progress is the long-term commitment to a steady downscaling of MOSFET/CMOS technology needed to meet the requirements on speed, complexity, circuit density, and power consumption posed by the many advanced applications relying on this technology. The degree of scaling is measured in terms of the half-pitch size of the first-level interconnect in DRAM technology, also termed the technology node by the International Technology Roadmap for Semiconductors. At the time of the 2001 ITRS update, the technology node had reached 130 nm, while the smallest features, the MOSFET gate lengths, were a mere 65 nm. Within a decade, these numbers are expected to be close to 40 nm and 15 nm, respectively. Very important issues in this development are the increasing levels of complexity of the fabrication process and the many subtle mechanisms that govern the properties of deep submicrometer FETs. These mechanisms, dictated by device physics, have to be described and implemented into circuit design tools to empower the circuit designers with the ability to fully utilize the potential of existing and future technologies. Hence, circuit designers are faced with the relentless challenge of staying updated on the properties, potentials, and the limitations of the latest device technology and device models. This is especially true for designers of analog and radio frequency (RF) integrated circuits, where the sensitivity to the modeling details and the interplay between individual devices is more acute than for digital electronics. A deeper insight into these issues is therefore crucial for gaining the competitive edge needed to ensure first-time-right silicon and to reduce time-to-market for new products. Existing textbooks on analog and RF CMOS circuit design traditionally lack a thorough treatment of the device modeling challenges outlined above. Our primary objectives with the present book is to bridge the gap between device modeling and analog circuit design by presenting the state-of-the-art MOSFET models that are available in analog and SPICEtype circuit simulators today, together with related modeling issues of importance to both circuit designers and students, now and in the future.

14 xii PREFACE This book is intended as a main or supplementary text for senior and graduate-level courses in analog integrated circuit design, as well as a reference and a text for self or group studies by practicing design engineers. Especially in student design projects, we foresee that this book will be a valuable handbook as well as a reference, both on basic modeling issues and on specific MOSFET models encountered in circuit simulators. Likewise, practicing engineers can use the book to enhance their insight into the principles of MOSFET operation and modeling, thereby improving their design skills. We assume that the reader already has a basic knowledge of common electronic devices and circuits, and fundamental concepts such as small-signal operation and equivalent circuits. The book is organized into twelve chapters. In Chapter 1, the reader is introduced to the basic physics, the principles of operation, and the modeling of MOS structures and MOSFETs. This chapter also discusses many of the issues that are important in the modeling of modern-day MOSFETs. Chapter 2 walks the reader through the fabrication steps of modern MOSFET and CMOS technology. In Chapter 3, the special concerns and the challenges of accurate modeling of MOSFETs operating at radio frequencies are discussed. Chapter 4 deals with modeling of noise in MOSFETs. Distortion analysis, discussed in Chapter 5, is of special concern for analog MOSFET circuit design. In Chapters 6, 7, and 8, we present the state-of-the-art MOSFET models that are commonly used by the analog design community today. The models covered are BSIM4, EKV, MOS Model 9 and MOSA1. These chapters are written in a reference style to provide quick lookup when the book is used like a handbook. Chapters 9 and 10 are devoted to the modeling of other devices that are of importance in typical analog CMOS circuits, such as bipolar transistors (Chapter 9) and passive devices, including resistors, capacitors, and inductors (Chapter 10). The remaining two chapters deal with essential industry-related issues of circuit design. Chapter 11 discusses the important topic of modeling of process variations and device mismatch effects and Chapter 12 deals with the quality assurance of the device models used by the design houses. The book is accompanied by two software application tools, AIM-Spice and MOSCalc. AIM-Spice is a version of SPICE with standard SPICE parameters, very familiar to many electrical engineers and electrical engineering students. Running under the Microsoft Windows family of operating systems, it takes full advantage of the available graphics user interface. The AIM-Spice software will run on all PCs equipped with Windows 95, 98, ME, NT 4, 2000, or XP. In addition to all the models included into Berkeley SPICE (Version 3e.1), AIM-Spice incorporates BSIM4, EKV, and MOSA1, which were covered in Chapters 6, 7, and 8. A limited version of AIM-Spice can be downloaded from The second tool, MOSCalc, is a Web-based calculator for rapid estimates of MOSFET large- and small-signal parameters. The designer enters the gate length and width, and a range of biasing voltages and/or the transistor currents, whereupon quantities such as gate overdrive voltage, effective threshold voltage, drain-source saturation voltage, all terminal currents, transconductance, channel conductance, and all small signal intrinsic capacitances are calculated. MOSCalc is available at ngl.fysel.ntnu.no. These dedicated software tools allow students to solve real engineering problems, which brings semiconductor device physics and modeling home to the user at a very practical level, bridging the gap between theory and practice. AIM-Spice and MOSCalc can be used routinely by practicing engineers during the design phase of analog integrated circuits.

15 PREFACE xiii We are grateful to the following colleagues for their suggestions and/or for reviewing portions of this book: Matthias Bucher and Bjørnar Hernes. We would also like to express our appreciation to the staff at Wiley, UK, and in particular to Kathryn Sharples, for making possible the timely production of the book. Finally, we would like to thank our families for their great support, patience, and understanding provided throughout the period of writing.

Device Modeling for Analog and RF CMOS Circuit Design

Device Modeling for Analog and RF CMOS Circuit Design Device Modeling for Analog and RF CMOS Circuit Design Trond Ytterdal Norwegian University of Science and Technology Yuhua Cheng Skyworks Solutions