Low Distortion 1.0 GHz Differential Amplifier AD8350

Transcription

1 a FEATUE High Dynamic ange Output IP3: 28 dbm: 2 MHz Low Noise Figure:.9 2 MHz Two Gain Versions: AD83-: db AD83-2: 2 db 3 db Bandwidth:. GHz ingle upply Operation: V to V upply Current: 28 ma Input/Output Impedance: 2 ingle-ended or Differential Input Drive 8-Lead OIC Package and 8-Lead microoic Package APPLICATION Cellular Base tations Communications eceivers F/IF Gain Block Differential A-to-D Driver AW Filter Interface ingle-ended-to-differential Conversion High Performance Video High peed Data Transmission PODUCT DECIPTION The AD83 series are high performance fully-differential amplifiers useful in F and IF circuits up to MHz. The amplifier has excellent noise figure of.9 db at 2 MHz. It offers a high output third order intercept (OIP3) of 28 dbm at 2 MHz. Gain versions of db and 2 db are offered. The AD83 is designed to meet the demanding performance requirements of communications transceiver applications. It enables a high dynamic range differential signal chain, with exceptional linearity and increased common-mode rejection. The device can be used as a general purpose gain block, an A-to-D driver, and high speed data interface driver, among other functions. The AD83 input can also be used as a singleended-to-differential converter. Low Distortion. GHz Differential Amplifier AD83 FUNCTIONAL BLOCK DIAGAM 8-Lead OIC and OIC Packages (with Enable) IN ENBL V CC OUT IN 7 GND 6 GND AD83 The amplifier can be operated down to V with an OIP3 of 28 dbm at 2 MHz and slightly reduced distortion performance. The wide bandwidth, high dynamic range and temperature stability make this product ideal for the various F and IF frequencies required in cellular, CATV, broadband, instrumentation and other applications. The AD83 is offered in an 8-lead single OIC package and µoic package. It operates from V and V power supplies, drawing 28 ma typical. The AD83 offers a power enable function for power-sensitive applications. The AD83 is fabricated using Analog Devices proprietary high speed complementary bipolar process. The device is available in the industrial ( 4 C to 8 C) temperature range. OUT Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA , U..A. Tel: 78/ Fax: 78/46-33 Analog Devices, Inc., 23

2 AD83 PECIFICATION 2 C, V = V, G = db, unless otherwise noted. All specifications refer to differential inputs and differential outputs unless noted.) Parameter Conditions Min Typ Max Unit DYNAMIC PEFOMANCE 3 db Bandwidth V = V, V OUT = V p-p.9 GHz V = V, V OUT = V p-p. GHz Bandwidth for. db Flatness V = V, V OUT = V p-p 9 MHz V = V, V OUT = V p-p 9 MHz lew ate V OUT = V p-p 2 V/µs ettling Time.%, V OUT = V p-p ns Gain (2) V = V, f = MHz 4 6 db Gain upply ensitivity V = V to V, f = MHz.3 db/v Gain Temperature ensitivity T MIN to T MAX.2 db/ C Isolation (2) f = MHz 8 db NOIE/HAMONIC PEFOMANCE MHz ignal econd Harmonic V = V, V OUT = V p-p 66 dbc V = V, V OUT = V p-p 67 dbc Third Harmonic V = V, V OUT = V p-p 6 dbc V = V, V OUT = V p-p 7 dbc Output econd Order Intercept 2 V = V 8 dbm V = V 8 dbm Output Third Order Intercept 2 V = V 28 dbm V = V 29 dbm 2 MHz ignal econd Harmonic V = V, V OUT = V p-p 48 dbc V = V, V OUT = V p-p 49 dbc Third Harmonic V = V, V OUT = V p-p 2 dbc V = V, V OUT = V p-p 6 dbc Output econd Order Intercept 2 V = V 39 dbm V = V 4 dbm Output Third Order Intercept 2 V = V 24 dbm V = V 28 dbm db Compression Point (TI) 2 V = V 2 dbm V = V dbm Voltage Noise (TI) f = MHz.7 nv/ Hz Noise Figure f = MHz 6.8 db INPUT/OUTPUT CHAACTEITIC Differential Offset Voltage (TI) V OUT V OUT ± mv Differential Offset Drift T MIN to T MAX.2 mv/ C Input Bias Current µa Input esistance eal 2 Ω CM f = MHz 67 db Output esistance eal 2 Ω POWE UPPLY Operating ange 4. V Quiescent Current Powered Up, V = V ma Powered Down, V = V ma Powered Up, V = V ma Powered Down, V = V ma Power-Up/Down witching ns Power upply ejection atio f = MHz, V = V p-p 8 db OPEATING TEMPEATUE ANGE 4 8 C NOTE ee Tables II III for complete list of -Parameters. 2 e: Ω. pecifications subject to change without notice. 2

3 AD83-2 PECIFICATION differential inputs and differential outputs unless noted.) AD83 2 C, V = V, G = 2 db, unless otherwise noted. All specifications refer to Parameter Conditions Min Typ Max Unit DYNAMIC PEFOMANCE 3 db Bandwidth V = V, V OUT = V p-p.7 GHz V = V, V OUT = V p-p.9 GHz Bandwidth for. db Flatness V = V, V OUT = V p-p 9 MHz V = V, V OUT = V p-p 9 MHz lew ate V OUT = V p-p 2 V/µs ettling Time.%, V OUT = V p-p ns Gain (2) V = V, f = MHz db Gain upply ensitivity V = V to V, f = MHz.3 db/v Gain Temperature ensitivity T MIN to T MAX.2 db/ C Isolation (2) f = MHz 22 db NOIE/HAMONIC PEFOMANCE MHz ignal econd Harmonic V = V, V OUT = V p-p 6 dbc V = V, V OUT = V p-p 66 dbc Third Harmonic V = V, V OUT = V p-p 66 dbc V = V, V OUT = V p-p 7 dbc Output econd Order Intercept 2 V = V 6 dbm V = V 6 dbm Output Third Order Intercept 2 V = V 28 dbm V = V 29 dbm 2 MHz ignal econd Harmonic V = V, V OUT = V p-p 4 dbc V = V, V OUT = V p-p 46 dbc Third Harmonic V = V, V OUT = V p-p dbc V = V, V OUT = V p-p 6 dbc Output econd Order Intercept 2 V = V 37 dbm V = V 38 dbm Output Third Order Intercept 2 V = V 24 dbm V = V 28 dbm db Compression Point (TI) 2 V = V 2.6 dbm V = V.8 dbm Voltage Noise (TI) f = MHz.7 nv/ Hz Noise Figure f = MHz.6 db INPUT/OUTPUT CHAACTEITIC Differential Offset Voltage (TI) V OUT V OUT ± mv Differential Offset Drift T MIN to T MAX.2 mv/ C Input Bias Current µa Input esistance eal 2 Ω CM f = MHz 2 db Output esistance eal 2 Ω POWE UPPLY Operating ange 4. V Quiescent Current Powered Up, V = V ma Powered Down, V = V ma Powered Up, V = V ma Powered Down, V = V ma Power-Up/Down witching ns Power upply ejection atio f = MHz, V = V p-p 4 db OPEATING TEMPEATUE ANGE 4 8 C NOTE ee Tables II III for complete list of -Parameters. 2 e: Ω. 3

4 AD83 ABOLUTE MAXIMUM ATING* upply Voltage, V V Input Power Differential dbm Internal Power Dissipation mw θ JA OIC () C/W θ JA µoic (M) C/W Maximum Junction Temperature C Operating Temperature ange C to 8 C torage Temperature ange C to C Lead Temperature ange (oldering 6 sec) C *tresses above those listed under Absolute Maximum atings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGUATION PIN FUNCTION DECIPTION Pin Function Description, 8 IN, IN Differential Inputs. IN and IN should be ac-coupled (pins have a dc bias of midsupply). Differential input impedance is 2 Ω. 2 ENBL Power-up Pin. A high level ( V) enables the device; a low level ( V) puts device in sleep mode. 3 V CC Positive upply Voltage. V to V. 4, OUT, OUT Differential Outputs. OUT and OUT should be ac-coupled (pins have a dc bias of midsupply). Differential input impedance is 2 Ω. 6, 7 GND Common External Ground eference. IN ENBL V CC OUT AD83 TOP VIEW (Not to cale) IN GND GND OUT CAUTION ED (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD83 features proprietary ED protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ED precautions are recommended to avoid performance degradation or loss of functionality. WANING! ED ENITIVE DEVICE 4

5 Typical Performance Characteristics AD V CC = V UPPLY CUENT ma V CC = V GAIN db V CC = V GAIN db TEMPEATUE C TPC. upply Current vs. Temperature k k TPC 2. AD83- Gain (2) vs. Frequency k k TPC 3. AD83-2 Gain (2) vs. Frequency OIC IMPEDANCE 2 2 V CC = V IMPEDANCE 2 2 V CC = V IMPEDANCE 3 2 OIC k TPC 4. AD83- Input Impedance k TPC. AD83-2 Input Impedance TPC 6. AD83- Output Impedance 8 OIC 6 IMPEDANCE 4 OIC IOLATION db V CC = V IOLATION db 2 V CC = V TPC 7. AD83-2 Output Impedance 2 k k TPC 8. AD83- Isolation (2) 3 k k TPC 9. AD83-2 Isolation (2)

6 AD V OUT = V p-p HD2 (V CC = V) 4 4 V OUT = V p-p HD2 () 4 F O = MHz HD3 () DITOTION dbc HD2 () HD3 () HD3 (V CC = V) DITOTION dbc HD2 (V CC = V) HD3 () HD3 (V CC = V) DITOTION dbc 6 7 HD2 () HD2 (V CC = V) HD3 (V CC = V) FUNDAMENTAL TPC. AD83- Harmonic Distortion FUNDAMENTAL TPC. AD83-2 Harmonic Distortion OUTPUT VOLTAGE V p-p TPC 2. AD83- Harmonic Distortion vs. Differential Output Voltage 4 F O = MHz HD2 () HD3 () 6 6 DITOTION dbc 6 7 HD3 (V CC = V) HD2 (V CC = V) OIP2 dbm (e: ) V CC = V OIP2 dbm (e: ) V CC = V OUTPUT VOLTAGE V p-p TPC 3. AD83-2 Harmonic Distortion vs. Differential Output Voltage TPC 4. AD83- Output eferred IP TPC. AD83-2 Output eferred IP2 OIP3 dbm (e: ) V CC = V OIP3 dbm (e: ) V CC = V db COMPEION dbm (e: ) INPUT EFEED V CC = V TPC 6. AD83- Output eferred IP TPC 7. AD83-2 Output eferred IP TPC 8. AD83- db Compression 6

7 AD83 db COMPEION dbm (e: ) INPUT EFEED V CC = V NOIE FIGUE db V CC = V NOIE FIGUE db V CC = V TPC 9. AD83-2 db Compression TPC 2. AD83- Noise Figure TPC 2. AD83-2 Noise Figure GAIN db 2 2 AD83- AD83-2 OUTPUT OFFET mv 2 V OUT () V OUT () V OUT (V CC = V) V OUT (V CC = V) P db AD83-2 AD V CC Volts TPC 22. AD83 Gain (2) vs. upply Voltage TEMPEATUE C TPC 23. AD83 Output Offset Voltage vs. Temperature 9 k TPC 24. AD83 P 2 mv 3 4 AD83-2 V OUT P db 6 AD k TPC 2. AD83 CM ENBL V 3ns TPC 26. AD83 Power-Up/Down esponse Time 7

8 AD83 APPLICATION Using the AD83 Figure shows the basic connections for operating the AD83. A single supply in the range V to V is required. The power supply pin should be decoupled using a. µf capacitor. The ENBL pin is tied to the positive supply or to V (when V CC = V) for normal operation and should be pulled to ground to put the device in sleep mode. Both the inputs and the outputs have dc bias levels at midsupply and should be ac-coupled. Also shown in Figure are the impedance balancing requirements, either resistive or reactive, of the input and output. With an input and output impedance of 2 Ω, the AD83 should be driven by a 2 Ω source and loaded by a 2 Ω impedance. A reactive match can also be implemented. OUCE Z = C2. F AD83 C4. F Z = 2 L /2 L / /2 AD83 V C P C P / L /2 L /2. F ENBL (V) V (V TO V) Figure 3. eactively Matching the Input and Output L C V P L AD83 C P Z = C. F ENBL (V) V (V TO V) C3. F C. F Figure. Basic Connections for Differential Drive Figure 2 shows how the AD83 can be driven by a singleended source. The unused input should be ac-coupled to ground. When driven single-endedly, there will be a slight imbalance in the differential output voltages. This will cause an increase in the second order harmonic distortion (at MHz, with V CC = V and V OUT = V p-p, 9 dbc was measured for the second harmonic on AD83-). OUCE Z = 2 C2. F C. F ENBL (V) AD V (V TO V) C4. F C3. F C. F Z = 2 Figure 2. Basic Connections for ingle-ended Drive eactive Matching In practical applications, the AD83 will most likely be matched using reactive matching components as shown in Figure 3. Matching components can be calculated using a mith Chart or by using a resonant approach to determine the matching network that results in a complex conjugate match. In either situation, the circuit can be analyzed as a single-ended equivalent circuit to ease calculations as shown in Figure 4. 8 ENBL (V) F V (V TO V) Figure 4. ingle-ended Equivalent Circuit When the source impedance is smaller than the load impedance, a step-up matching network is required. A typical step-up network is shown on the input of the AD83 in Figure 3. For purely resistive source and load impedances the resonant approach may be used. The input and output impedance of the AD83 can be modeled as a real 2 Ω resistance for operating frequencies less than MHz. For signal frequencies exceeding MHz, classical mith Chart matching techniques should be invoked in order to deal with the complex impedance relationships. Detailed parameter data measured differentially in a 2 Ω system can be found in Tables II and III. For the input matching network the source resistance is less than the input resistance of the AD83. The AD83 has a nominal 2 Ω input resistance from Pins to 8. The reactance of the ac-coupling capacitors,, should be negligible if nf capacitors are used and the lowest signal frequency is greater than MHz. If the series reactance of the matching network inductor is defined to be X = 2 π f L, and the shunt reactance of the matching capacitor to be X P = (2 π f C P ), then: X = X P where X P = For a 7 MHz application with a Ω source resistance, and assuming the input impedance is 2 Ω, or = IN = 2 Ω, then X P =. Ω and X = 86.6 Ω, which results in the following component values: C P = (2 π 7 6.) = 9.7 pf and L = 86.6 (2 π 7 6 ) = 97 nh ()

9 AD83 For the output matching network, if the output source resistance of the AD83 is greater than the terminating load resistance, a step-down network should be employed as shown on the output of Figure 3. For a step-down matching network, the series and parallel reactances are calculated as: X = X P where X P = For a MHz application with the 2 Ω output source resistance of the AD83, = 2 Ω, and a Ω load termination, = Ω, then X P =. Ω and X = 86.6 Ω, which results in the following component values: C P = (2 π 6.) = 38 pf and L = 86.6 (2 π 6 ) =.38 µh The same results can be obtained using the plots in Figure and Figure 6. Figure shows the normalized shunt reactance versus the normalized source resistance for a step-up matching network, <. By inspection, the appropriate reactance can be found for a given value of /. The series reactance is then calculated using X = /X P. The same technique can be used to design the step-down matching network using Figure 6. NOMALIZED EACTANCE X P / OUCE X XP NOMALIZED OUCE EITANCE OUCE / Figure. Normalized tep-up Matching Components NOMALIZED EACTANCE X P / OUCE XP X (2) The same results could be found using a mith Chart as shown in Figure 7. In this example, a shunt capacitor and a series inductor are used to match the 2 Ω source to a Ω load. For a frequency of MHz, the same capacitor and inductor values previously found using the resonant approach will transform the 2 Ω source to match the Ω load. At frequencies exceeding MHz, the parameters from Tables II and III should be used to account for the complex impedance relationships. EIE L OUCE HUNT C Figure 7. mith Chart epresentation of tep-down Network After determining the matching network for the single-ended equivalent circuit, the matching elements need to be applied in a differential manner. The series reactance needs to be split such that the final network is balanced. In the previous examples, this simply translates to splitting the series inductor into two equal halves as shown in Figure 3. Gain Adjustment The effective gain of the AD83 can be reduced using a number of techniques. Obviously a matched attenuator network will reduce the effective gain, but this requires the addition of a separate component which can be prohibitive in size and cost. The attenuator will also increase the effective noise figure resulting in an N degradation. A simple voltage divider can be implemented using the combination of the driving impedance of the previous stage and a shunt resistor across the inputs of the AD83 as shown in Figure 8. This provides a compact solution but suffers from an increased noise spectral density at the input of the AD83 due to the thermal noise contribution of the shunt resistor. The input impedance can be dynamically altered through the use of feedback resistors as shown in Figure 9. This will result in a similar attenuation of the input signal by virtue of the voltage divider established from the driving source impedance and the reduced input impedance of the AD83. Yet this technique does not significantly degrade the N with the unnecessary increase in thermal noise that arises from a truly resistive attenuator network NOMALIZED OUCE EITANCE OUCE / Figure 6. Normalized tep-down Matching Components 9

10 AD83 HUNT AD83 L V HUNT L F ENBL (V) V (V TO V) Figure 8. Gain eduction Using hunt esistor FEXT The insertion loss and the resultant power gain for multiple shunt resistor values is summarized in Table I. The source resistance and input impedance need careful attention when using Equation. The reactance of the input impedance of the AD83 and the ac-coupling capacitors need to be considered before assuming they have negligible contribution. Figure shows the effective power gain for multiple values of HUNT for the AD83- and AD83-2. Table I. Gain Adjustment Using hunt esistor, = and IN = ingle-ended Power Gain db HUNT IL db AD83- AD V ENBL (V) AD V (V TO V) FEXT. F Figure 9. Dynamic Gain eduction Figure 8 shows a typical implementation of the shunt divider concept. The reduced input impedance that results from the parallel combination of the shunt resistor and the input impedance of the AD83 adds attenuation to the input signal effectively reducing the gain. For frequencies less than MHz, the input impedance of the AD83 can be modeled as a real 2 Ω resistance (differential). Assuming the frequency is low enough to ignore the shunt reactance of the input, and high enough such that the reactance of moderately sized ac-coupling capacitors can be considered negligible, the insertion loss, IL, due to the shunt divider can be expressed as: L L GAIN db AD83-2 AD HUNT Figure. Gain for Multiple Values of hunt esistance for Circuit in Figure 8 The gain can be adjusted dynamically by employing external feedback resistors as shown in Figure 9. The effective attenuation is a result of the lowered input impedance as with the shunt resistor method, yet there is no additional noise contribution at the input of the device. It is necessary to use well-matched resistors to minimize common-mode offset errors. Quality % tolerance resistors should be used along with a symmetric board layout to help guarantee balanced performance. The effective gain for multiple values of external feedback resistors is shown in Figure. IL( db) = 2 Log where IN HUNT = IN IN IN ( IN ) IN HUNT ( IN HUNT ) HUNT HUNT and = Ω single ended IN (3)

11 AD83 GAIN db AD83-2 AD83-2 FEXT Figure. Power Gain vs. External Feedback esistors for the AD83- and AD83-2 with = Ω and L = Ω The power gain of any two-port network is dependent on the source and load impedance. The effective gain will change if the differential source and load impedance is not 2 Ω. The singleended input and output resistance of the AD83 can be modeled using the following equations: and OUT IN F L = F L gm (4) L INT F INT = gm INT F g for k Ω m () Driving Lighter Loads It is not necessary to load the output of the AD83 with a 2 Ω differential load. Often it is desirable to try to achieve a complex conjugate match between the source and load in order to minimize reflections and conserve power. But if the AD83 is driving a voltage responding device, such as an ADC, it is no longer necessary to maximize power transfer. The harmonic distortion performance will actually improve when driving loads greater than 2 Ω. The lighter load requires less current driving capability on the output stages of the AD83 resulting in improved linearity. Figure 2 shows the improvement in second and third harmonic distortion for increasing differential load resistance. DITOTION dbc HD3 HD Figure 2. econd and Third Harmonic Distortion vs. Differential Load esistance for the AD83- with V = V, f = 7 MHz, and V OUT = V p-p where F = FEXT // FINT FEXT = Feedback External FINT = 662 Ω for the AD83- = Ω for the AD83-2 INT = 2 Ω g m =.66 mhos for the AD83- =. mhos for the AD83-2 = ource (ingle-ended) L = Load (ingle-ended) IN = Input (ingle-ended) OUT = Output (ingle-ended) The resultant single-ended gain can be calculated using the following equation: G V ( ) L gm F = g L F L m (6)

12 AD83 Table II. Typical cattering Parameters for the AD83-: V CC = V, Differential Input and Output, Z OUCE (diff) = 2, Z (diff) = 2 Frequency MHz Table III. Typical cattering Parameters for the AD83-2: V CC = V, Differential Input and Output, Z OUCE (diff) = 2, Z (diff) = 2 Frequency MHz

13 AD83 OUTLINE DIMENION. (.968) 4.8 (.89) 4. (.74) 3.8 (.497) (.244).8 (.2284).2 (.98). (.4) COPLANAITY. EATING PLANE.27 (.) BC.7 (.688).3 (.32). (.2).3 (.22) 8.2 (.98).7 (.67). (.96).2 (.99).27 (.).4 (.7) 4 COMPLIANT TO JEDEC TANDAD M-2-AA CONTOLLING DIMENION AE IN MILLIMETE; INCH DIMENION (IN PAENTHEE) AE OUNDED-OFF MILLIMETE EQUIVALENT FO EFEENCE ONLY AND AE NOT APPOPIATE FO UE IN DEIGN. Figure 4. 8-Lead tandard mall Outline Package [OIC_N] Narrow Body (-8) Dimensions shown in millimeters and (inches) 247-A PIN IDENTIFIE.6 BC COPLANAITY MAX 6 MAX.23.9 COMPLIANT TO JEDEC TANDAD MO-87-AA Figure. 8-Lead Mini mall Outline Package [MOP] (M-8) Dimensions shown in millimeters b ev. B Page 3

14 AD83 ODEING GUIDE Model Temperature ange Package Description Package Option Branding AD83AZ-EEL7 4 C to 8 C 8-Lead OIC_N -8 AD83AMZ 4 C to 8 C 8-Lead MOP M-8 QT AD83AMZ-EEL7 4 C to 8 C 8-Lead MOP M-8 QT AD83AMZ2 4 C to 8 C 8-Lead MOP M-8 QU AD83AMZ2-EEL7 4 C to 8 C 8-Lead MOP M-8 QU AD83AM2-EEL7 4 C to 8 C 8-Lead MOP M-8 J2P AD83AZ2-EEL7 4 C to 8 C 8-Lead OIC_N -8 Z = oh Compliant Part. EVIION HITOY /3 ev. A to ev. B Deleted Evaluation Board ection... 2 Updated Outline Dimensions... 3 Changes to Ordering Guide / ev. to ev. A 23 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D4--/3(B) ev. B Page 4