Low Distortion Differential RF/IF Amplifier AD8351

Transcription

1 FEATURES db Bandwidth of. GHz for A V = 1 db Single Resistor Programmable Gain db A V 6 db Differential Interface Low Noise Input Stage.7 nv/ A V = 1 db Low Harmonic Distortion 79 dbc 7 MHz 81 dbc 7 MHz OIP of 1 7 MHz Single-Supply Operation: V to. V Low Power Dissipation: 8 V Adjustable Output Common-Mode Voltage Fast Settling and Overdrive Recovery Slew Rate of 1, V/ s Power-Down Capability 1-Lead MSOP Package APPLICATIONS Differential ADC Drivers Single-Ended-to-Differential Conversion IF Sampling Receivers RF/IF Gain Blocks SAW Filter Interfacing Low Distortion Differential RF/IF Amplifier FUNCTIONAL BLOCK DIAGRAM PWUP RGP1 RGP + WITH 1 db OF GAIN DRIVING THE AD66 (R L = 1k ) ANALOG INPUT: 7MHz ENCODE : 8MHz SNR : 69.1dB FUND : 1.1dBFS HD : 78.dBc HD : 8.7dBc THD : 7.9dBc SFDR : 78.dBc BIAS CELL RG VOCM VPOS OPHI 1nF OPLO COMM 1nF AD66 1-BIT ADC GENERAL DESCRIPTION The is a low cost differential amplifier useful in RF and IF applications up to. GHz. The voltage gain can be set from unity to 6 db using a single external gain resistor. The provides a nominal 1 Ω differential output impedance. The excellent distortion performance and low noise characteristics of this device allow for a wide range of applications. The is designed to satisfy the demanding performance requirements of communications transceiver applications. The device can be used as a general-purpose gain block, an ADC driver, and a high speed data interface driver, among other functions. The can also be used as a single-ended-to-differential amplifier with similar distortion products as in the differential configuration. The exceptionally good distortion performance makes the an ideal solution for 1-bit and 1-bit IF sampling receiver designs. Fabricated in ADI s high speed XFCB process, the has high bandwidth that provides high frequency performance and low distortion. The quiescent current of the is 8 ma typically. The amplifier comes in a compact 1-lead MSOP package and will operate over the temperature range of C to +8 C. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA 6-916, U.S.A. Tel: 781/9-7 Fax: 781/6-87 Analog Devices, Inc. All rights reserved.

2 SPECIFICATIONS (V S = V, R L = 1, = 11 (A V = 1 db), f = 7 MHz, T = C, parameters specified differentially, unless otherwise noted.) Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth GAIN = 6 db, V OUT 1. V p-p, MHz GAIN = 1 db, V OUT 1. V p-p, MHz GAIN = 18 db, V OUT 1. V p-p 6 MHz Bandwidth for.1 db Flatness db GAIN db, V OUT 1. V p-p MHz Bandwidth for. db Flatness db GAIN db, V OUT 1. V p-p MHz Gain Accuracy Using 1% Resistor for, db A V db ± 1 db Gain Supply Sensitivity V S ± %.8 db/v Gain Temperature Sensitivity C to +8 C.9 mdb/ C Slew Rate R L = 1 kω, V OUT = V Step 1, V/ s R L = 1 Ω, V S = V Step 7, V/ s Settling Time 1 V Step to 1% < ns Overdrive Recovery Time V IN = V to V Step, V OUT ±1 mv < ns Reverse Isolation (S1) 67 db INPUT/OUTPUT CHARACTERISTICS Input Common-Mode Voltage Adjustment Range 1. to.8 V Max Output Voltage Swing 1 db Compressed.7 V p-p Output Common-Mode Offset mv Output Common-Mode Drift C to +8 C. mv/ C Output Differential Offset Voltage mv Output Differential Offset Drift C to +8 C.1 mv/ C Input Bias Current ±1 A Input Resistance 1 kω Input Capacitance 1.8 pf CMRR db Output Resistance 1 1 Ω Output Capacitance 1.8 pf POWER INTERFACE Supply Voltage. V PWUP Threshold 1. V PWUP Input Bias Current PWUP at V 1 A PWUP at V A Quiescent Current 8 ma

3 Parameter Conditions Min Typ Max Unit NOISE/DISTORTION 1 MHz Second/Third Harmonic Distortion R L = 1 kω, V OUT = V p-p 9/ 9 dbc R L = 1 Ω, V OUT = V p-p 86/ 71 dbc Third-Order IMD R L = 1 kω, f1 = 9. MHz, f = 1. MHz, V OUT = V p-p Composite 9 dbc R L = 1 Ω, f1 = 9. MHz, f = 1. MHz, V OUT = V p-p Composite 7 dbc Output Third-Order Intercept f1 = 9. MHz, f = 1. MHz dbm Noise Spectral Density (RTI).6 nv/ Hz 1 db Compression Point 1. dbm 7 MHz Second/Third Harmonic Distortion R L = 1 kω, V OUT = V p-p 79/ 81 dbc R L = 1 Ω, V OUT = V p-p 6/ 66 dbc Third-Order IMD R L = 1 kω, f1 = 69. MHz, f = 7. MHz, V OUT = V p-p Composite 8 dbc R L = 1 Ω, f1 = 69. MHz, f = 7. MHz, V OUT = V p-p Composite 69 dbc Output Third-Order Intercept f1 = 69. MHz, f = 7. MHz 1 dbm Noise Spectral Density (RTI).7 nv/ Hz 1 db Compression Point 1. dbm 1 MHz Second/Third Harmonic Distortion R L = 1 kω, V OUT = V p-p 69/ 69 dbc R L = 1 Ω, V OUT = V p-p / dbc Third-Order IMD R L = 1 kω, f1 = 19. MHz, f = 1. MHz, V OUT = V p-p Composite 79 dbc R L = 1 Ω, f1 = 19. MHz, f = 1. MHz, V OUT = V p-p Composite 67 dbc Output Third-Order Intercept f1 = 19. MHz, f = 1. MHz 9 dbm Noise Spectral Density (RTI).7 nv/ Hz 1 db Compression Point 1 dbm MHz Second/Third Harmonic Distortion R L = 1 kω, V OUT = V p-p 6/ 66 dbc R L = 1 Ω, V OUT = V p-p 6/ dbc Third-Order IMD R L = 1 kω, f1 = 9. MHz, f =. MHz, V OUT = V p-p Composite 76 dbc R L = 1 Ω, f1 = 9. MHz, f =. MHz, V OUT = V p-p Composite 6 dbc Output Third-Order Intercept f1 = 9. MHz, f =. MHz 7 dbm Noise Spectral Density (RTI).9 nv/ Hz 1 db Compression Point 1 dbm NOTES 1 Values are specified differentially. See Applications section for single-ended-to-differential performance. Specifications subject to change without notice.

4 ABSOLUTE MAXIMUM RATINGS* Supply Voltage VPOS V PWUP Voltage VPOS Internal Power Dissipation mw JA C/W Maximum Junction Temperature C Operating Temperature Range C to +8 C Storage Temperature Range C to +1 C Lead Temperature Range (Soldering 6 sec) C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION PWUP 1 RGP1 RGP TOP VIEW (Not to Scale) 1 VOCM 9 VPOS 8 OPHI 7 OPLO 6 COMM ORDERING GUIDE Model Temp. Range Package Description Package Option Branding ARM C to +8 C 1-Lead MSOP, 7" Tape and Reel RM-1 JDA ARM-R C to +8 C 1-Lead MSOP, 7" Tape and Reel RM-1 JDA ARM-REEL7 C to +8 C 1-Lead MSOP, 7" Tape and Reel RM-1 JDA -EVAL Evaluation Board PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1 PWUP Apply a positive voltage (1. V V PWUP VPOS ) to activate device. RGP1 Gain Resistor Input 1. Balanced Differential Input. Biased to midsupply, typically ac-coupled Balanced Differential Input. Biased to midsupply, typically ac-coupled. RGP Gain Resistor Input. 6 COMM Device Common. Connect to low impedance ground. 7 OPLO Balanced Differential Output. Biased to VOCM, typically ac-coupled. 8 OPHI Balanced Differential Output. Biased to VOCM, typically ac-coupled. 9 VPOS Positive Supply Voltage. V to. V. 1 VOCM Voltage applied to this pin sets the common-mode voltage at both the input and output. Typically decoupled to ground with a.1 µf capacitor. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

5 Typical Performance Characteristics (V S = V, T = C, unless otherwise noted.) GAIN (db) = 1 = 8 1 = GAIN (db) 1 1 = 1 = = TPC 1. Gain vs. Frequency for a 1 Ω Differential Load (A V = 6 db, 1 db, and 18 db) GAIN (db) 1 1 R L = 1 R L = OPEN R L = 1k k 1k ( ) TPC. Gain vs. Gain Resistor, (f = 1 MHz, R L = 1 Ω, 1 kω, and Open) TPC. Gain vs. Frequency for a 1 kω Differential Load (A V = 1 db, 18 db, and 6 db) GAIN FLATNESS (db) R L = 1k R L = 1 R L = 1.1 R L = 1k TPC. Gain Flatness vs. Frequency (R L = 1 Ω and 1 kω, A V =1 db) GAIN (R L = 1k ) (db) GAIN (RL = 1 ) (db) ISOLATION (db) TEMPERATURE ( C) TPC. Gain vs. Temperature at 1 MHz (A V = 1 db) TPC 6. Isolation vs. Frequency (A V = 1 db)

6 HARMONIC DISTORTION (VPOS = V) (dbc) HD HD HD DIFFERENTIAL INPUT HD HARMONIC DISTORTION (VPOS = V) (dbc) HARMONIC DISTORTION (dbc) SINGLE-ENDED INPUT HD HD HD TPC 7. Harmonic Distortion vs. Frequency for V p-p into R L = 1 kω (A V = 1 db, at V and V Supplies) TPC 1. Harmonic Distortion vs. Frequency for V p-p into R L = 1 kω Using Single-Ended Input (A V = 1 db) HARMONIC DISTORTION (VPOS = V) (dbc) HD HD HD HD DIFFERENTIAL INPUT HARMONIC DISTORTION (VPOS = V) (dbc) HARMONIC DISTORTION (dbc) SINGLE-ENDED INPUT HD HD TPC 8. Harmonic Distortion vs. Frequency for V p-p into R L = 1 Ω (A V = 1 db, at V and V Supplies) TPC 11. Harmonic Distortion vs. Frequency for V p-p into R L = 1 Ω Using Single-Ended Input (A V = 1 db). NOISE SPECTRAL DENSITY (nv/ Hz) NOISE SPECTRAL DENSITY (nv/ Hz) TPC 9. Noise Spectral Density (RTI) vs. Frequency (R L = 1 Ω, V Supply, A V = 1 db). 1 1 TPC 1. Noise Spectral Density (RTI) vs. Frequency (R L = 1 Ω, V Supply, A V = 1 db) 6

7 16 7 OUTPUT 1dB COMPRESSION (dbm) R L = 1 VPOS = V R L = 1k R L = 1 VPOS = V R L = 1k THIRD-ORDER IMD (dbc) TPC 1. Output Compression Point, P1 db, vs. Frequency (R L = 1 Ω and 1 kω, A V = 1 db, at V and V Supplies) TPC 16. Third-Order Intermodulation Distortion vs. Frequency for a V p-p Composite Signal into R L = 1 kω (A V = 1 db, at V Supplies) OUTPUT 1dB COMPRESSION (dbm) VPOS = V VPOS = V THIRD-ORDER IMD (dbc) GAIN RESISTOR ( ) TPC 1. Output Compression Point, P1 db, vs. (f = 1 MHz, R L = 1 Ω, A V = 1 db, at V and V Supplies) TPC 17. Third-Order Intermodulation Distortion vs. Frequency for a V p-p Composite Signal into R L = 1 Ω (A V = 1 db, at V Supplies) OUTPUT 1dB COMPRESSION (db) THIRD-ORDER INTERMODULATION DISTORTION (dbc) TPC 1. Output Compression Point Distribution (f = 7 MHz, R L = 1 Ω, A V = 1 db) TPC 18. Third-Order Intermodulation Distortion Distribution (f = 7 MHz, R L = 1 Ω, A V = 1 db) 7

8 IMPEDANCE MAGNITUDE ( ) PHASE (deg) GHz 1MHz MHz WITH GHz MHz TERMINATIONS WITHOUT TERMINATIONS 1MHz TPC 19. Input Impedance vs. Frequency TPC. Input Reflection Coefficient vs. Frequency (R S = R L = 1 Ω with and without Ω Terminations) 16 1 IMPEDANCE MAGNITUDE ( ) IMPEDANCE PHASE (deg) GHz MHz 1MHz TPC. Output Impedance vs. Frequency TPC. Output Reflection Coefficient vs. Frequency (R S = R L = 1 Ω) PHASE (deg) GROUP DELAY (ps) CMRR (db) R L = 1 R L = 1k TPC 1. Phase and Group Delay (A V = 1 db, at V Supplies) TPC. Common-Mode Rejection Ratio, CMRR (R S = 1 Ω) 8

9 .6 1. VOLTAGE (V)... pf pf pf 1pF VOLTAGE (V) TIME (ns) TPC. Transient Response under Capacitive Loading (R L = 1 Ω, C L = pf, pf, pf, 1 pf) TIME (ns) TPC 8. Large Signal Transient Response for a 1 V p-p Output Step (A V = 1 db, R IP = Ω)... OUTPUT (V)... SETTLING (%) TIME (ns) TPC 6. Output Overdrive Recovery (R L = 1 Ω, A V = 1 db) V OUT TIME (ns) TPC 9. 1% Settling Time for a V p-p Step (A V = 1 db, R L = 1 Ω) 1 VOLTAGE (V) 1 V IN 1 1 TIME (ns) TPC 7. Overdrive Recovery Using Sinusoidal Input Waveform R L = 1 Ω (A V = 1 db, at V Supplies) 9

10 BASIC CONCEPTS Differential signaling is used in high performance signal chains, where distortion performance, signal-to-noise ratio, and low power consumption is critical. Differential circuits inherently provide improved common-mode rejection and harmonic distortion performance as well as better immunity to interference and ground noise. BALANCED SOURCE 1 PWUP RGP1 RGP VOCM 1 VPOS 9 OPHI 8 OPLO 7 COMM 6 Figure 1. Differential Circuit Representation Figure 1 illustrates the expected input and output waveforms for a typical application. Usually the applied input waveform will be a balanced differential drive, where the signal applied to the and pins are equal in amplitude and differ in phase by 18. In some applications, baluns may be used to transform a singleended drive signal to a differential signal. The may also be used to transform a single-ended signal to a differential signal. GAIN ADJUSTMENT The differential gain of the is set using a single external resistor,, which is connected between Pins and. The gain can be set to any value between db and 6 db using the resistor values specified in TPC, with common gain values provided in Table I. The board traces used to connect the external gain resistor should be balanced and as short as possible to help prevent noise pickup and to ensure balanced gain and stability. The low frequency voltage gain of the can be modeled as A V where: RL RG( 6. )+ 9. RF RL = R R R + ( R + R ) 9+ R G L G L F G R F is Ω (internal). R L is the single-ended load resistance. is the gain setting resistor. R L A A ( ) = V V Table I. Gain Resistor Selection for Common Gain Values (Load Resistance Is Specified as Single-Ended) Gain, A V (R L = 7 ) (R L = ) db 68 Ω kω 6 db Ω 7 Ω 1 db 1 Ω Ω db Ω Ω A OUT IN COMMON-MODE ADJUSTMENT The output common-mode voltage level is the dc offset voltage present at each of the differential outputs. The ac signals are of equal amplitude with a 18 phase difference but are centered at the same common-mode voltage level. The common-mode output voltage level can be adjusted from 1. V to.8 V by driving the desired voltage level into the VOCM pin, as illustrated in Figure. BALANCED SOURCE 1 PWUP RGP1 RGP VOCM 1 VPOS 9 OPHI 8 OPLO 7 COMM 6 Figure. Common-Mode Adjustment R L.1 F V S V OCM C DECL 1.V.1 F TO.8V INPUT AND OUTPUT MATCHING The provides a moderately high differential input impedance of kω. In practical applications, the input of the will be terminated to a lower impedance to provide an impedance match to the driving source, as depicted in Figure. The terminating resistor, R T, should be as close as possible to the input pins in order to minimize reflections due to impedance mismatch. The 1 Ω output impedance may need to be transformed to provide the desired output match to a given load. Matching components can be calculated using a Smith Chart or by using a resonant approach to determine the matching network that results in a complex conjugate match. The input and output impedances and reflection coefficients are provided in TPCs 19,,, and. For additional information on reactive matching to differential sources and loads, refer to the Applications section of the AD8 data sheet. Figure illustrates a SAW (surface acoustic wave) filter interface. Many SAW filters are inherently differential, allowing for a low loss output match. In this example, the SAW filter requires a Ω source impedance in order to provide the desired center frequency and Q. The series L shunt C output network provides a 1 Ω to Ω impedance transformation at the desired frequency of operation. The impedance transformation is illustrated on a Smith Chart in Figure. It is possible to drive a single-ended SAW filter simply by connecting the unused output to ground using the appropriate terminating resistance. The overall gain of the system will be reduced by 6 db due to the fact that only half of the signal will be available to the input of the SAW filter. VPOS R S R T.1 F.1 F L S 7nF 19MHz SAW BALANCED SOURCE R S = R T.1 F 1 C P 8pF R S R T.1 F L S 7nF Figure. Example of Differential SAW Filter Interface (f C = 19 MHz) 1

11 SERIES L 1 SHUNT C 1 R F (k ) 1 R L = 1 R L = 1 R L = ( ) Figure 6b. Feedback Resistor Selection Figure. Smith Chart Representation of SAW Filter Output Matching Network.1 F.1 F R F.1 F.1 F Figure. Single-Ended Application SINGLE-ENDED-TO-DIFFERENTIAL OPERATION The can easily be configured as a single-ended-todifferential gain block, as illustrated in Figure. The input signal is ac-coupled and applied to the input. The unused input is ac-coupled to ground. The values of C1 through C should be selected such that their reactances are negligible at the desired frequency of operation. To balance the outputs, an external feedback resistor, R F, is required. To select the gain resistor and the feedback resistor, refer to Figures 6a and 6b. From Figure 6a, select an for the required db gain at a given load. Next, select from Figure 6b an R F resistor for the selected and load. Even though the differential balance is not perfect under these conditions, the distortion performance is still impressive. TPCs 1 and 11 show the second and third harmonic distortion performance when driving the input of the using a single-ended Ω source. GAIN (db) 1 1 R L = 1 R L = 1 R L = 1 1 ( ) R L ADC DRIVING The circuit in Figure 7 represents a simplified front end of the driving the AD66, which is a 1-bit, 1 MSPS A/D converter. For optimum performance, the AD66 and the are driven differentially. The resistors R1 and R present a Ω differential input impedance to the source with R and R providing isolation from the A/D input. The gain setting resistor for the is. The AD66 presents a 1 kω differential load to the and requires a. V p-p differential signal between AIN and AIN for a full-scale output. This circuit then provides the gain, isolation, and source matching for the AD66. The also provides a balanced input, not provided by the balun, to the AD66, which is essential for second-order cancellation. The signal generator is bipolar, centered around ground. Connecting the VOCM pin (1) of the to the VREF pin of the AD66 sets the common-mode output voltage of the at. V. This voltage is bypassed with a.1 µf capacitor. Increasing the gain of the will increase the system noise and thus decrease the SNR but will not significantly affect the distortion. The circuit in Figure 7 can provide SFDR performance of better than 9 dbc with a 1 MHz input and 8 dbc with a 7 MHz input at a gain of 1 db. BALANCE SOURCE 1nF 1nF OPHI OPLO VOCM AIN AD66 AIN VREF DIGITAL OUT Figure 7. ADC Driving Application Using Differential Input The circuit of Figure 8 represents a single-ended input to differential output configuration of the driving the AD66. In this case, R1 provides the input impedance. is the gain setting resistor. The resistor R F is required to balance the output voltages required for second-order cancellation by the AD66 and can be selected using a chart. (See the Single-Ended-to- Differential Operation section.) The circuit depicted in Figure 8 can provide SFDR performance of better than 9 dbc with a 1 MHz input and 77 dbc with a 7 MHz input. Figure 6a. Gain Selection 11

12 SINGLE- ENDED SOURCE R1 1nF 1nF R F OPHI OPLO VOCM 1nF AIN AD66 AIN VREF DIGITAL OUT Figure 8. ADC Driving Application Using Single-Ended Input ANALOG MULTIPLEXING The can be used as an analog multiplexer in applications where it is desirable to select multiple high speed signals. The isolation of each device when in a disabled state (PWUP pin pulled low) is about 6 dbc for the maximum input level of. V p-p out to 1 MHz. The low output noise spectral density allows for a simple implementation as depicted in Figure 9. The PWUP interface can be easily driven using most standard logic interfaces. By using an N-bit digital interface, up to N devices can be controlled. Output loading effects and noise need to be considered when using a large number of input signal paths. Each disabled presents approximately a 7 Ω load in parallel with the 1 Ω output source impedance of the enabled device. As the load increases due to the addition of N devices, the distortion performance will degrade due to the heavier loading. Distortion better than 7 dbc can be achieved with four devices muxed into a 1 kω load for signal frequencies up to 7 MHz. SIGNAL INPUT 1 RGP1 RGP BIT 1 PWUP OPHI N-BIT DIGITAL INTERFACE I/O CAPACITIVE LOADING Input or output direct capacitive loading greater than a few picofarads can result in excessive peaking and/or oscillation outside the pass band. This results from the package and bond wire inductance resonating in parallel with the input/output capacitance of the device and the associated coupling that results internally through the ground inductance. For low resistive load or source resistance, the effective Q is lower, and higher relative capacitance termination(s) can be allowed before oscillation or excessive peaking occurs. These effects can be eliminated by adding series input resistors (R IP ) for high source capacitance, or series output resistors (R OP ) for high load capacitance. Generally less than Ω is all that is required for I/O capacitive loading greater than ~ pf. The higher the C, the smaller the R parasitic suppression resistor required. In addition, R IP also helps to reduce low gain in-band peaking, especially for light resistive loads. C STRAY C STRAY R IP R IP R L 1k Figure 1. Input and Output Parasitic Suppression Resistors, R IP and R OP, Used to Suppress Capacitive Loading Effects Due to package parasitic capacitance on the ports, high values (low gain) cause high ac-peaking inside the pass band, resulting in poor settling in the time domain. As an example, when driving a 1 kω load, using Ω for R IP reduces the peaking by ~7 db for equal to Ω (A V = 1 db) (see Figure 11). R OP R OP C L C L OPLO BIT SIGNAL INPUT RGP1 RGP PWUP OPHI MUX OUTPUT LOAD OPLO BIT N SIGNAL INPUT N PWUP OPHI RGP1 RGP OPLO Figure 9. Using Several s to Form an N-Channel Analog MUX Figure 11. Reducing Gain Peaking with Parasitic Suppressing Resistors (R IP = Ω, R L = 1 kω) 1

13 It is important to ensure that all I/O, ground, and port traces be kept as short as possible. In addition, it is required that the ground plane be removed from under the package. Due to the inverse relationship between the gain of the device and the value of the resistor, any parasitic capacitance on the ports can result in gain-peaking at high frequencies. Following the precautions outlined in Figure 1 will help to reduce parasitic board capacitance, thus extending the device s bandwidth and reducing potential peaking or oscillation. ( de-q ) the resonant effects of the device bond wires and surrounding parasitic board capacitance. Typically, Ω series resistors (size ) adequately de-q the input system without a significant decrease in ac performance. Figure 1 illustrates the value of adding input and output series resistors to help desensitize the resonant effects of board parasitics. Overshoot and undershoot can be significantly reduced with the simple addition of R IP and R OP. 1. NO R IP OR R OP AGND R OP = COPLANAR WAVEGUIDE OR STRIP R T R T R IP R IP R OP R OP Hi-Z VOLTAGE (V).. R IP = R OP = AGND 1. Figure 1. General Description of Recommended Board Layout for High-Z Load Conditions TRANSMISSION LINE EFFECTS As noted, stray transmission line capacitance, in combination with package parasitics, can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking. R F transmission lines connecting the input and output networks should be designed such that stray capacitance is minimized. The output single-ended source impedance of the is dynamically set to a nominal value of 7 Ω. Therefore, for a matched load termination, the characteristic impedance of the output transmission lines should be designed to be 7 Ω. In many situations, the final load impedance may be relatively high, greater than 1 kω. It is suggested that the board be designed as shown in Figure 1 for high impedance load conditions. In most practical board designs, this requires that the printed-circuit board traces be dimensioned to a small width (~ mils) and that the underlying and adjacent ground planes are far enough away to minimize capacitance. Typically the driving source impedance into the device will be low and terminating resistors will be used to prevent input reflections. The transmission line should be designed to have the appropriate characteristic impedance in the low-z region. The high impedance environment between the terminating resistors and device input pins should not have ground planes underneath or near the signal traces. Small parasitic suppressing resistors may be necessary at the device input pins to help desensitize 1. 1 TIME (ns) Figure 1. Step Response Characteristics with and without Input and Output Parasitic Suppression Resistors CHARACTERIZATION SETUP The test circuit used for 1 Ω and 1 kω load testing is provided in Figure 1. The evaluation board uses balun transformers to simplify interfacing to single-ended test equipment. Balun effects need to be removed from the measurements in order to accurately characterize the performance of the device at frequencies exceeding 1 GHz. The output L-pad matching networks provide a broadband impedance match with minimum insertion loss. The input lines are terminated with Ω resistors for input impedance matching. The power loss associated with these networks needs to be accounted for when attempting to measure the gain of the device. The required resistor values and the appropriate insertion loss and correction factors used to assess the voltage gain are provided in Table II. Table II. Load Conditions Specified Differentially Conversion Total Factor Load Insertion log (S1) Condition R1 R Loss to log (A V ) 1 Ω. Ω 86.6 Ω.8 db 7.6 db 1 kω 7 Ω. Ω 1.9 db.9 db BALANCED SOURCE R S R S CABLE CABLE R T R T.1nF.1nF DUT 1nF 1nF R1 R LOAD R1 R R CABLE CABLE TEST EQUIPMENT Figure 1. Test Circuit 1

14 EVALUATION BOARD An evaluation board is available for experimentation. Various parameters such as gain, common-mode level, and input and output network configurations can be modified through minor resistor changes. The schematic and evaluation board artwork are presented in Figures 1, 16, and 17. P1 ENBL VCOM VPOS ACOM W1 R17 AGND R18 R6 OPEN C.1 F VPOS J1 RF_IN+ J RF_IN R OPEN R1 T1 R.9 1:1 ETC1-1-1 (MACOM) R.9 C 1nF R C R8 1nF R7 R1 1 1 PWUP RGP1 RGP VOCM 1 VPOS 9 OPHI 8 OPLO 7 COMM 6 1 PIN msoic R1 R16 C6 1nF C7 1nF C 1nF R R R T 1:1 ETC1-1-1 (MACOM) R1 OPEN R1 J RF_OUT+ J RF_OUT J TEST IN T C1 1nF T J6 TEST OUT 1:1 ETC1-1-1 (MACOM) C9 1nF 1:1 ETC1-1-1 (MACOM) Figure 1. Evaluation Board Schematic Figure 16. Component Side Layout Figure 17. Component Side Silkscreen 1

15 Table III. Evaluation Board Configuration Options Component Function Default Condition P1-1, P1-, Supply and Ground Pins. Not Applicable VPOS, AGND P1- Common-Mode Offset Pin. Allows for monitoring or adjustment of the Not Applicable output common-mode voltage. W1, R7, P1-, R17, R18 Device Enable. Configured such that switch W1 disables the device when W1 = Installed Pin 1 is set to ground. Device can be disabled remotely using Pin of R7 = Ω (Size 6) header P1. R17 = R18 = Ω (Size 6) R, R, R, R, R8, R1, Input Interface. R and R1 are used to ground one side of the differential R = R =.9 Ω (Size 8) T1, C, C drive interface for single-ended applications. T1 is a 1-to-1 impedance ratio R = Open (Size 6) balun used to transform a single-ended input into a balanced differential R = R8 = R1 = Ω signal. R and R are used to provide a differential Ω input termination. (Size 6) R and R8 can be increased to reduce gain peaking when driving from a high C = C = 1 nf (Size 6) source impedance. The Ω termination provides an insertion loss of 6 db. T1 = Macom TM ETC1-1-1 C and C are used to provide ac coupling. R9, R1, R11, R1, R1, Output Interface. R1 and R1 are used to ground one side of the differential R9 = R1 = 61.9 Ω (Size 6) R1, R16, T, C, C, output interface for single-ended applications. T is a 1-to-1 impedance ratio R11 = 61.9 Ω (Size 6) C6, C7 balun used to transform a balanced differential signal into a single-ended R1 = Open (Size 6) signal. R9, R1, and R11 are provided for generic placement of matching R1 = Ω (Size 6) components. R1 and R16 allow additional output series resistance when R1 = R16 = Ω (Size ) driving capacitive loads. The evaluation board is configured to provide a C = C = 1 nf (Size 6) 1 Ω to Ω impedance transformation with an insertion loss of 9.9 db. C6 = C7 = 1 nf (Size 6) C through C7 are used to provide ac coupling. T = Macom ETC1-1-1 R1 Gain Setting Resistor. Resistor R1 is used to set the gain of the device. R1 = 1 Ω (Size 6) Refer to TPC when selecting gain resistor. When R1 is 1 Ω, the overall system gain of the evaluation board will be approximately 6 db. C Power Supply Decoupling. The supply decoupling consists of a 1 nf C = 1 nf (Size 8) capacitor to ground. R6, C, P1- Common-Mode Offset Adjustment. Used to trim common-mode output R6 = Ω (Size 6) level. By applying a voltage to Pin of header P1, the output common- C =.1 µf (Size 8) mode voltage can be directly adjusted. Typically decoupled to ground using a.1 µf capacitor. T, T, C9, C1 Calibration Networks. Calibration path provided to allow for compensation T = T = Macom of the insertion loss of the baluns and the reactance of the coupling capacitors. ETC1-1-1 C9 = C1 = 1 nf (Size 6) 1

16 OUTLINE DIMENSIONS 1-Lead Mini Small Outline Package [MSOP] (RM-1) Dimensions shown in millimeters. BSC. BSC BSC C1 /(B) PIN BSC.7.17 COPLANARITY MAX SEATING PLANE..8 8 COMPLIANT TO JEDEC STANDARDS MO-187BA.8.6. Revision History Location Page / Data Sheet changed from REV. A to. Changes to ORDERING GUIDE Changes to TPC / Data Sheet changed from REV. to REV. A. Change to ORDERING GUIDE Change to Table III