An Integrated 60GHz Low Power Two- Chip Wireless System Based on IEEE802.11ad Standard

Transcription

1 An Integrated 60GHz Low Power Two- Chip Wireless System Based on IEEE802.11ad Standard 1 Kaixue Ma; 1 Kiat Seng Yeo; Francois Chin 2 Xiaoming Peng 2 ; Xianming Qing 2 ; Zhining Chen 2 ; etc. 1 Nanyang Technological University, Singapore, 2 Institute for Infocomm Research (I 2 R), A*STAR 1

2 Outline Introduction Design Target & Scheme System Architecture RFIC Chip Baseband Chip Results Demonstration Performance comparison with state-of-the-art Conclusion

3 Introduction: Standard Compliance Video streaming QoS Tri-band operation Fast session transfer in 60GHz, 2.4 GHz, 5 GHz

4 Introduction: Why be Popular recently? Smart City 1. Unlicensed 9GHz bandwidth worldwide 2. Huge Information exploration and exchange IOT 3. Wireless technology progress Speed become a driven factor 4. Low cost silicon for 60GHz radio is mature and matching to the applications

5 Design Constraint: 60GHz Product Definition WP1: Scenarios WP4:Front end NTU Bit Rate Range Coverage Power Operation WP3: Baseband Tx/Rx Power Max Bandwidth Channel/Phase Noise Linearity Spurious Temperature I/O interfaces Power Constraints Modulation Access Schemes Delay Constraints Ad hoc Constraints WP2: MAC/PHY Layer I2R Verification based WP1

6 Dual-Chip System Architecture Antenna ESD 60G LPF Ref 40MHz TX Chain 60G PA CP PFD 60G Balun 24GHz Synthesizer with LO network SHM 24G DQ VControl Programmable Clock Divider CAMP CAMP RFIC IF VGA 12GHz 24GHz QC Mixer 12G DQ CAMP CAMP DVGA_I DVGA_Q TX gain registers LO control registers CC LPF CC LPF RX gain registers I+ I- Q+ Q- SPI Slave DAC DAC PLL π/2- ROT RC Filter MCS 0 MOD PHY LDPC ENC De- Spreading BBIC PHY CTRL Differential DEMOD MPI LDPC DEC MicroP MEM MAC CTRL Encrypt/ Decrypt ESD Antenna 60G RX Chain 60G LNA 24GHz 60G Balun 24G DQ SHM 12GHz IF VGA 12G DQ QC Mixer CC LPF CC LPF DVGA_I DVGA_Q I+ I- Q+ Q- ADC ADC π/2- ROT MCS 1-9 FO Est. Sync. Phase Comp EQ Filter Channel Est. Symbol Tracking Phase Tracking DEMOD MAC Host Interface

7 RF Transceiver Architecture GND PAOUT VB_VCO VTUNE CPOUT REF_IN REF_DIV VB_BUF VDD_V GND VDD_ESD LNAIN GND 60G BPF 60G BPF VDD_PA VB_PA 60G PA TX Chain CP PFD RX Chain 60G LAN VB_LNA VDD_LNA Programmable Clock Divider IFA IFA Data Link to Analog Baseband 60GHz RF to/from antenna Power/Bias Supply Ground PLL VGB_RX VT_DN60G VDD_UP60_DC VDD_UP60_RF DVGA_I DVGA_I DVGA_Q VDD_DN60_DC VDD_DN60_RF VDD_DVGA_TX VB_DVGA_TX DVGA_Q TX gain registers LO control registers RX gain registers VB_DVGA_RX VDD_DVGAAMP_RX SPI slave Digital Control from MAC PLL related IO Test Pin BB_IN BB_IP BB_QN BB_QP RSTN SCLK SDI CSN SDO CLKOUT VDD VDDO DGND BBOUT_IM BBOUT_IP BBOUT_QM BBOUT_QP 1) Two time conversion with sliding IF and LO of 24GHz and 12GHz 2) Differential I/O IF for the BB processing 3) AGC for both Tx and Rx 4) SPI interface for setting and controlling 5) Sub-harmonic conversion for the second stage 6) Cross coupled LPF with cutoff frequency of 1.9GHz and stopband up to 110GHz 7) Power on/down setting for both Tx and Rx for power saving 8) Multiple coupled LC tanks for low phase VCO and ILFD

8 Summary about the VIRTUS-I VIRTUS-I 60GHz fully integrated transceiver SOC, 60GHz LTCC packaging with SOC assembled inside and fully integrated frontend developed by NTU. 60GHz fully integrated transceiver SOC Demonstration board Parted with I2R baseband team, 60GHz high definition video streaming has been successfully demonstrated in the Computex show hold in Taiwan June 2012.

9 VIRTUS-II 60GHz Transceiver SOC Full solution for 60GHz a) SOC b) Packaging: LTCC & board c) antenna d) different demo system Fully integrated Transceiver SOC a) Tx & Rx & synthesizer b) with SPI control and GUI c) with AGC and synthesizer set Fully ESD protected SOC: a) digital ESD b) analogy c) 60GHz ESD Low power based on the process <300mW Circuits and system innovative a) multiple coupled tank VCO b) Low loss Switch c) smallest electric tunable LPF

10 60GHz antipodal slot antenna design Fr Ga I/O RL GHz >15 dbi 50 Ω >10 db BW 12 o (Eplane)/24 o ( H-plane) Rad End-fire Pol Linear Sub 8 mil thick Roger4003 Dim 9mm 25mm 0.203mm Con MSP/CPW S 11 (db) Gain (dbi) Sim Mea Frequency (GHz) S 11 Gain Sim Mea Results E_co@60GHz 90 y Frequency (GHz) H_co@60GHz 90 y dB -20dB -10dB x 0= 0 0dB 180sim mea -30dB -20dB -10dB z 0= 0 0dB 180sim mea E-plane E_cx@60GHz y H-plane H_cx@60GHz 90 y GHz dB -20dB -10dB x f = 0 0 0dB 180sim mea -30dB -20dB -10dB z 0= 0 0dB 180sim mea

11 VIRTUS-II Transceiver Test Flip Chip to the board Loaded Validi Antenna MCU SPI control and setting USB control and power supply TDD operation Distance up to 3meter with output power of 100mVp-p 3meter Full automatic gain control with 60dB in total

12 VIRTUS-II Transmitter 16QAM Test Support: 4Gbp/s EVM=11.9%

13 VIRTUS-II Receiver 16QAM Test Support: 4Gbp/s EVM=9.8%

14 BBIC GHz baseband SOC 60GHz Baseband Solution DAC Media Access Control 60GHz RFIC PHY Security Encrypt CPU Host Interface Parallel Bus ADC LDPC Firmware

15 Comparison with the state of the art [1] T. Tsukizawa, et al., A Fully Integrated 60 GHz CMOS Transceiver Chipset Based on WiGiG/IEEE802.11ad with Built-In Self Calibration for Mobile Applications, ISSCC Dig. Tech. Papers, pp , Feb., [2] K. Okada et al., A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver with Low-Power Analog and Digital Baseband Circuitry, ISSCC Dig. Tech. Papers, pp , Feb [3]T. Mitomo, et al., A 2Gb/s-Throughput CMOS Transceiver ChipSet with In-Package Antenna for 60 GHz Short-Range Wireless Communication, ISSCC Dig Tech. Papers, pp , Feb [4]S. Reynolds, et al., 60GHz Transceiver Circuits in SiGe Bipolar Technology, ISSCC Dig. Tech. Papers, pp , Feb [5]B. Floyd, et al., A Silicon 60GHz Receiver and Transmitter Chipset for Broadband Communications, ISSCC Dig. Tech. Papers, pp , Feb [6] C.-H. Wang, et al. A 60GHz Transmitter with Integrated Antenna in 0.18μm SiGe BiCMOS Technology, ISSCC Dig. Tech. Papers, pp , Feb., 2006.

16 System Demonstration RFIC BBIC Antenna

17 System Implementation Results

18 Conclusion Dual chip solution based on IEEE802.11ad is developed. Two-time conversion sliding IF scheme is used to low the LO frequency to be ~24GHz. Time Division Duplex scheme for RFIC is selected for the operation and power saving. BBIC with MAC and PHY is developed by using TDE scheme and ADC/DAC. System level test and video streaming demonstration is done with communication distance up to 10 meters. Comparison with the state of the art for the low power and 60GHz applications

19 Thank You!