Barrier Engineering. Flash Memory. Rich Liu Macronix International Co., Ltd. Hsinchu, Taiwan, R.O.C. 1/ A*STAR/SRC/NSF Memory Forum

Transcription

1 Barrier Engineering g Scaling Limitations of Flash Memory Rich Liu Macronix International Co., Ltd. Hsinchu, Taiwan, R.O.C. 1/

2 Source Floating Gate NAND Device 1 Control gate ONO Floating gate Oxide Drain Program by channel FN tunneling Source Control gate ONO Oxide Erase by FN Drain STI Control Gate (Word Line) X Floating Floating Gate ONO Gate SiN Tunnel oxide Tunnel oxide STI Gate Coupling Ratio (GCR) = C(CG to FG) / C(FG total) Must be > 0.60 V(FG) = (GCR). Vg STI (Want most of the gate voltage drop across the tunnel oxide, not across the ONO.) 1. Program by FN electron tunneling 2/

3 Physical Limit for Floating Gate NAND IPD (Inter Poly Dielectrics) Control Gate FG X Not a physics limit. A physical (geometrical) limit. Device doesn t work w/o GCR. STI Si Charge trapping device (planar). 1. FG must be tall enough to give good GCR. 2. At < 20nm node, there is no space (X < 0) left for control gate after IPD filling. or Planar FG, resonant tunneling, or nano-crystal device with high-k/metal-gate 3/

4 SONOS Has It s Own Problems - 18V Poly-Si Gate SONOS device: Electrons are trapped in SiN. De-trapping is very slow. Must use hole tunneling to erase (hard). SiN Hole tunneling needs very thin tunnel oxide. Source P-well Drain Thin oxide cannot stop direct tunneling poor retention. SONOS is known for many years. There is no right thickness of tunnel oxide that can satisfy both erase and retention requirements. 4/

5 One Solution: Barrier Engineering BE-SONOS BE-SONOS SONOS P-Poly Gate P-Poly gate n-poly gate N-Poly Gate IPD SiN SiN Source P-well Drain SiN trapping layer Bandgap Engineered tunnel dielectric SiN Source P-well Drain Difference between BE-SONOS and SONOS: Composite ONO tunneling barrier allows both fast hole erasing and good data retention ti P-poly gate to reduce gate injection 5/

6 Barrier Engineering of Tunnel Oxide SONOS BE-SONOS Modulated tunneling barrier Achieves both erase and retention BE-SONOS Gate O3 N2 O2 N1 O1 Source P-well Modulated Drain Ba and Energy (ev) Band Diagram at High Electric Field N2 O2 N1 O1 Si-channel Col 3 vs Col 4 Band offset Position (Angstrom) Conduction Band Valence Band Band Energy (ev) Band Diagram at Retention N2 O2 N1 O1 Si-channel Conduction Band 1.9 ev Valence Band 4.5 ev No band offset Position (Angstrom) 6/

7 1x nm Nodes: Running out of Electrons The ultimate t scaling limit it for both FG and CT is the small number of storage electrons. mber Ne: Electron Nu 00 0 Electron number of FG GCR=0.7, Tono=15 nm, Tox=9nm GCR=0.65, Tono=13 nm, Tox=8nm 0 Technology Node: F (nm) lectron mber of E Ne: Nu Electron Number (Ne) Calculation N2/O3=60/60 Angstrom N2/O3=70/70 Angstrom Assume 3V V T shift T 0 F (nm) Number of electrons Number of electrons in FG device in SONOS device (~ 15 for nm device) ( ~ for nm device) 7/

8 Ne: Number of Electron Running out of Electrons Electron Number (Ne) Calculation Retention of Sub-30 nm BE-SONOS NAND ISPP Programming gstatistics N2/O3=60/60 Angstrom N2/O3=70/70 Angstrom Assume 3V V T shift 0 F (nm) Bit Coun nt (#) 0 Retention of Sub 30 nm BE SONOS NAND Before Baking After 24 hour After 0 hour After 300 hour 200 P/E cycled C arbi. unit) Cell Counts ( ISPP steps from V to +17V (0.4V increment) V V Number of electrons Retention for sub-30nm Program 20nm device in SONOS device 150C Identical pulse (~ 50 for 25nm device) (Quite good!) gives different Vt V T (V) V T (Vt shifts) For CT devices, retention is still good even when Ne < 50. Programming shots, however, have < electrons. Statistical limit for MLC first, eventually for SLC. 8/

9 Beyond 1x nm Node 3D Arrays Surround gate device is suitable for 3D layer stacking integration. BE-SONOS TFT device shows very good performance, approaching that for bulk device. Both geometrical and physics limits still exist. But 3D layering uses large (40nm) devices. Bit Co ounts (#) 9 8 As-Programmed State after 1K Cycling After 150C 24hr Baking 7 After 150C 1-week Baking T (V) V T V, 200 usec V msec P/E Cycling 4Mb evaluation V T (V) 9/

10 Summary Floating gate NAND Flash faces physical (geometrical) limit at ~ 20nm node. Charge trapping device can go further (being planar) Number of electrons decreases rapidly with node, even CT devices face statistical limit at nm node. Only known solution o is 3D layering. 3D does not solve physics and physical limitations. 3D by-passes these limits by using relatively large devices (~ 40nm). There is no perspective of using FG device for 3D. Must be CT devices. /