Trends in the Development of Nonvolatile Semiconductor Memories

Transcription

1

2 Trends in the Development of Nonvolatile Semiconductor Memories Torsten Müller, Nicolas Nagel, Stephan Riedel, Matthias Strasburg, Dominik Olligs, Veronika Polei, Stephano Parascandola, Hocine Boubekeur, Lars Bach, Thomas Mikolajick, Elard Stein von Kamienski, Karl-Heinz Küsters Infineon Technologies, TwinFlash Technology Development

3 OUTLINE State of the Art & Emerging Memory Technologies floating gate flash memory flash scaling & challenges Discrete Charge Trapping Cells TwinFlash TwinFlash 2 bit charge trapping cell TwinFlash scalability & device performance Conclusion

4 State of the Art & Emerging Memory Technologies ITRS roadmap, 2004 update

5 Floating Gate Memory I Drain no electrons floating gate electrons in floating gate gate floating gate programming source drain erase potential barrier required to secure 10 years of retention high voltage (10-20V), slow prog./erase (µs-ms), limited endurance V gate

6 Rapid Device Scaling (NAND) Floating Gate Memories as Technology Driver technology node & cell size 0.063µm µm 2 8G (MLC) Expected 2006 J.H. Park, IEDM 2004 The current cell sizes of the emerging memory technologies are more than an order of magnitude larger than that of leading edge Flash

7 Flash Scaling Challenges & Inovations thick gate stack (driven by required data retention) dielectric layer does not scale! high operation voltages (due to the thick gate stack) voltages don t scale source gate floating gate drain

8 Material Innovations (a) crested barriers Conv. Barrier Crested Barrier ev In practice SiO 2 has been combined with Al 2 O 3, Y 2 O 3, ZrO 2 and HfO 2 to achieve barrier modulation with electric field. ev (a) discrete charge trapping trap-rich layer (e.g. nitride) nanocrystals gate gate S D S D 2bit per transistor possible

9 A 2bit Charge Trapping Cell S gate D channel oxide - nitride - oxide e - e - gate Bit 1 Bit 2 NROM, MirrorBit, MicroFlash, NBit, MXVAND charge stored in nitride traps improved data retention tunnel (bottom oxide) can be reduced 2 physical bits per cell possible

10 How to Write & Erase 2 Bits per Cell? 9V Polysilicon 9V Oxide Nitride Bit1 Bit2 Oxide Prog bit 1 6V n + 0V Prog bit 2 6V n + 0V Programming: Hot Electron Injection Reverse Read to separate the bits -7V Bit1 p- silicon Polysilicon -7V Bit2 Erase: Hot Hole Injection 6V F n + n + 6V F p- silicon

11 TwinFlash Scalabilty & Device Characteristics 90nm node 70nm node 60nm node Metal 0 Metal 0 Metal 0 150nm 110nm 90nm

12 a) 90 nm node 1,E-04 1,E-05 2 nd bit effect 150 nm Gate Length c) 1,E-04 1,E-05 2 nd bit effect 60 nm node 90 nm Gate Length Drain current (A) Drain current (A) 1,E-06 1,E-07 1,E-08 Bit Bit A programmed 1,E-09 Bit Bit B at at prog. Bit Bit A 1,E ,E-04 1,E-05 1,E-06 1,E-07 1,E-08 Gate volatage (V) b) 70 nm node 110 nm Gate Length window Bit Bit A virgin 2 nd bit effect window Bit Bit A programmed 1,E-09 Bit Bit B at at prog. Bit Bit A 1,E Gate volatage (V) Bit Bit A virgin Drain current (A) 1,E-06 1,E-07 1,E-08 Bit Bit A programmed 1,E-09 Bit Bit B at at prog. Bit Bit A 1,E Gate volatage (V) window Bit Bit A virgin V d = 1.3V Excellent transfer characteristics down to gate length of 90nm. Even the 2nd bit effect increases with smaller gate length, a large window remains.

13 Data Retention 1,00 Program Window (between bit A and B) Window (V) 0,80 0,60 0,40 0,20 0,00 60 nm node 70 nm node 90 nm 110 nm 150 nm Gate Length 90 nm node For all gate lengths a large window 800mV between bit A and B is obtained after 10k cycles and 200 C, 1h (equal to 10y at 55 C) bake.

14 a) Endurance for 150nm Gate Length a) Max. drain voltage (V) nm node Cycles Program Erase c) Endurance for 90nm Gate Length c) Max. drain voltage (V) nm node Cycles Program Erase b) Endurance for 110nm Gate Length b) Max. drain voltage (V) nm node Program Erase Cycles Maximum drain voltage for program and erase maintaining a cycle window of 1.5V (increase V drain ar erase and decrease V drain at pgm) Programming improves with smaller gate length. The maximum voltage of erase remains approximately the same.

15 Conclusion Nonvolatile Semiconductor Memories: Despite of increasing challenges, Flash memories (esp. NAND) will remain the dominant nonvolatile semiconductor memory. Emerging memory technologies are forced to compete on this integration level, e.g. must deliver the same cell size and memory density. TwinFlash A 2bit Charge Trapping Cell 2bit per memory cell higher density possible at the same technology node improved reliability gate stack reduced TwinFlash Scalability: For the first time, TwinFlash devices of the 60nm technology node were demonstrated. An excellent performance were shown. opens the way for an attractive shrink roadmap (2 more generations)

16 Acknowledgement The author would like to thank all project members of the Infineon / Saifun development team for support and valuable discussions. This work was financially supported by the Federal Ministry of Education and Research of the Federal Republic of Germany (Project No. 01M 3160).