Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI

Transcription

1 Chinese Journal of Electronics Vol.20, No.4, Oct Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI ZHOU Jianhua 1,2,3,, S.K. PANG 1 and ZOU Shichang 1,2 (1.Grace Semiconductor Manufacturing Corporation, Shanghai , China) (2.Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai , China) (3.Graduate University of Chinese Academy of Sciences, Beijing , China) Abstract Two new structures with Very-shallowtrench-isolation (VSTI) for vertical bipolar transistors on thin top-si PD SOI are proposed and their characterization is studied by 2-D simulations. These bipolar structures are compatible with 0.13µm SOI-CMOS process. The two proposed transistors exhibit good device performance with current gain of and 89.7, f T of 24.04GHz and 22.8GHz, f max of 23.78GHz and 40.31GHz, respectively. Key words Silicon-on-insulator (SOI), Vertical bipolar transistor, Very-shallow-trench-isolation (VSTI), Current gain (β), Current gain cut-off frequency (f T ), Power gain cut-off frequency (f max). I. Introduction BiCMOS technology is widely used in low power, high-speed and RF/Analog applications, such as wireless circuits [1,2]. In SOI-CMOS mixed-signal systems, bipolar transistors are needed for RF and analog functions while the CMOS part basically supports digital parts, and this becomes an important technology platform for RF and high speed applications. There have been many reports about BiCMOS on SOI using lateral bipolar transistors [2 6] and vertical bipolar transistors on thick top-silicon SOI [7 10], but very few published on vertical bipolar transistor on thin top-silicon SOI [11,12]. Generally speaking, vertical bipolar transistor offers better performance than the lateral ones [13]. However, as the technology scaling-down in SOI-CMOS, the thickness of the top-si layer gets thinner and thinner that aggravates the difficulties for deep collector (including n + buried layer) of conventional vertical bipolar transistor to be implemented on SOI. In order to make vertical bipolar transistors on very thin top-si SOI, two novel structures with dual-sti approaches are proposed and comprehensive study on these two cases using 2-D device simulations [14] is described in details. II. Proposed Device Structures The schematic drawings of the two proposed SOI n-p-n bipolar transistors are shown in Figs.1 and 2, respectively. Dual-STI hereby is meant of two different STI trench depths used for the same device for different purposes. Here, standard STI is used for device isolation. Very-shallow-trench-isolation (VSTI) provides isolation between the heavily doping emitter and collector or extrinsic base regions inside the bipolar device. In Fig.1, there are two VSTI regions in the structure of Type- A. Left VSTI provides isolation between n + poly emitter and p + extrinsic base area. This design is used to n + /p + leakage. And the right one can isolate n + poly emitter and p + extrinsic base area, which can improvebreakdownvoltage and lower base-collector capacitance (C BC). Additional p-type implantation is implemented for inter-connection between intrinsic base and base leading-out. In the Type-B in Fig.2, there is only one VSTI which is used for isolation between n + poly emitter and n + extrinsic collector area. And the purpose of this VSTI is similar with the right VSTI in Type-A, which is used to improvebreakdownvoltage and lower C BC. Different from Type-A, the Type-B eliminates the additional p-type implantation. p + poly on the top of base is implemented as base leading-out. For both type A and B, no n + buried collector is used and arsenic pre-dope is needed for poly-emitter doping. Extrinsic base leading-out and collector leading-out implantation can respectively share with SOI-CMOS Source/Drain p + /n + implantations. Fig. 1. Schematic of dual-sti SOI BJT: Type-A The top-si thickness (T SOI) of the simulated SOI devices Manuscript Received Aug. 2010; Accepted Dec

2 Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI 613 is 100nm, with Buried oxide (BOX) thickness of 145nm, an n + poly emitter with poly thickness of 100nm and poly emitter stripe width (W E) of 200nm. For Type-A transistor in Fig.1, the clearance between the edge of the left side VSTI and p- type implantation edge for intrinsic and extrinsic base mentioned above is L OV L1, where the width of VSTI is W V ST I. In Type-B, the spacing between poly emitter and poly base leading-out is L ISO and the L OV L2 is the overlap of the base poly leading-out and the extrinsic base, as shown in Fig.2. All these parameters follow GSMC (Grace semiconductor manufacturing Corp.) 0.13µm SOI-CMOS design rules. N C of 7e17cm 3 can be obtained from Fig.4. By the way, the junction depth can be estimated as: X JEB = 4 5nm, X JBC = 36nm and W B = 32nm. The gummel plot of the transistor of Type-A with W E of 200nm, W V ST I of 200nm and L OV L1 of 100nm is illustrated in Fig.5. Fig. 3. Two-dimensional contours of the net carrier concentration for Type-A device in Fig.1 at V BE = 0.86V and V CE = 3V For any BJT, whether with vertical or lateral structure, the f T Eq.(1) and f max Eq.(2) is defined as follows: Fig. 2. Schematic of dual-sti SOI BJT: Type-B 1 2πf T =τ EC = τ E + τ B + τ C III. Device Characteristics 1. Type-A bipolar transistor characteristics Two-dimensional process and device simulations are conducted in simulator of Sentaurus S-process and S-device version [14]. The Philips unified mobility model, proposed by Klaassen [15], unifies the description of majority and minority carrier bulk mobility. It is well calibrated and used for the above proposed bipolar devices simulation. In addition to describing the temperature dependence of the mobility, the model takes into account electron-hole scattering, screening of ionized impurities by charge carriers, and clustering of impurities [14]. In addition, generation-recombination processes that exchange carriers between the conduction band and the valence band are very important in device physics, in particular, for bipolar devices. Shockley-Read-Hall (SRH) recombination, Auger recombination and band-to-band tunneling models are involved in the device simulation. Fig.3 shows the 2D contours of the net carrier concentration in the Type-A device and Fig.4 shows the 1D vertical profiles of doping concentration at the center of the intrinsic base of the n-p-n bipolar transistor. The simulated base doping level N B of 7e18cm 3 and collector doping level = W 2 B KD n + R C(C CS + C CB) + kt (C CB + C EB) + xc (1) qi C v sim ft f max = (2) 8πC BCR B where τ E, τ B and τ C are transit/delay time in emitter, base and collector, respective. And for f max, C BC and R B are the base-collector capacitance and base resistivity. In real f T and f max extraction, they re extracted using S-parameter extrapolation method. In the current gain (H 21 db) versus frequency plot, the H 21 curve has a slope of 20dB/decade and the extrapolated line will cross the frequency axis at 0dB for H 21 and the X-intercept is the estimated f T for the transistor. f max is extrapolated when power gain (GU db) reaches unity at higher frequency region. The impact of W V ST I and L OV L1 on DC performance is shown in Fig.6, where current gain (β) is plotted vs. V BE. From Fig.6, W V ST I seems no obvious influence on the current gain of Type-A transistor. Reducing W V ST I will improve f T and f max due to lower collector series resistor (r c) and base series resistor (r b ) in Figs.7 and 8. Compared to the transistor Fig. 4. One-dimensional vertical cuts of doping concentration at the center of base of the Type-A and Type-B transistor Fig. 5. Gummel plot of Type-A transistor Fig. 6. Current gain vs. V BE with different W V ST I and L OV L1

3 614 Chinese Journal of Electronics 2011 with W V ST I of 500nm, peak value of f T and f max of transistor with W V ST I of 200nm at I C = 8.48E-5A/µm improves 36% and 56%, respectively. However, the BV cbo of the transistor with W V ST I of 200nm is 8.82V. It is smaller than 9.08V BV cbo of the transistor with W V ST I of 500nm. That is because less impurities diffusion to collector due to widening W ST I. Smaller effective collector doping concentration leads to lager BV cbo. It also can be noted that current gain, f T and f max decrease significantly as the increase of L OV L1. When L OV L1 increases from 100nm to 300nm, the widening of L OV L1 could enhance boron diffusion from the higher doping level of extrinsic p-type implantation region into the intrinsic base to increase intrinsic base doping level, which decreases current gain. Meanwhile, r b increases as the widening of L OV L1. Moreover, the effective base width W B is also increased due to the reduction of the base depletion width because of higher base concentration. The increase of W B and r b results in the significant reduction of f T and f max, respectively. It is illustrated in Figs.6, 7 and 8 that the influence of L OV L1 on device performance seems more obvious than that of W V ST I. Decreasing L OV L1 can significantly improve the device performance. However, one concern of decreasing of L OV L1 is the alignment issue. L OV L1 cannot be too small due to the capability of the litho-scanner. Photoresist CD and overlay shift must be considered in the device design. base poly leading-out and base) of 100nm. Fig. 8. f max vs. I C with different W V ST I and L OV L1 Fig. 9. Two-dimensional contour of the net carrier concentration for the device in Fig.2 at V BE = 0.86V and V CE = 3V Fig. 7. f T vs. I C with different W V ST I and L OV L1 2. Type-B bipolar transistor characteristics In order to avoid the design issue and get more accurate control of L OV L1, we proposed another device structure Type- B. The p-type implantation for intrinsic base leading-out is no longer used here. Heavily doped p-type poly overlapping intrinsic base is used for base current leading-out as shown in Fig.2. In this case one mask layer can be saved. All the simulation conditions are the same except for p-type implantation in Type-A transistor. Fig.9 shows the 2D contour of the net carrier concentration for the Type-B device. The 1D vertical profile of doping concentration at the center of intrinsic base of this n-p-n bipolar transistor is shown in Fig.4. And the base doping profile (N B) of 7e18cm 3 and collector doping profile (N C) of 7e17cm 3 of Type-B device are similar to those of Type-A device. Type-B device basic size is with an emitter strip width (W E) of 200nm, W V ST I (the width of the VSTI) of 200nm, L ISO (the spacing between poly emitter and poly base leading-out) of 180nm and L OV L2 (the overlap between Fig. 10. Current gain vs. V BE with different W V ST I, L ISO and L OV L2 The impact of W V ST I, L ISO and L OV L2 on DC performance is shown in Fig.10, where current gain is plotted vs. V BE. It can be noted that current gain varies little with the change of the three factors. Figs.11 and 12 show the impact of these three factors on the RF performance of the transistor. Decreasing of the W V ST I can improve f T and f max by reducing r c. In addition, L ISO, the spacing between poly-emitter and top-poly-base, is an important factor. Extrinsic base impurities can diffuse less to intrinsic base as the increase of L ISO. Hence the overall intrinsic base concentration (N B) of transistor with smaller L ISO can be higher than that of the larger one. Higher N B can result in smaller current gain which is

4 Simulation Study of Novel Very-Shallow-Trench-Isolation Vertical Bipolar Transistors on PD SOI 615 shown but not very obvious in Fig.10. And higher N B leads to widen W B due to narrower depletion beside base. Furthermore, widening L ISO causes the increase of r b and C BC. As a result, increasing L ISO degrades f T and f max due to the increase of r b, W B and C BC shown in Figs.11 and 12. At last, reducing L OV L2 can improve f T and f max by reducing C BC. From the Figs.10, 11 and 12, it can be concluded that L ISO plays a very important role in determining the device RF performance than the other two factors. And some tradeoffs have to be made in the device design for different circuit applications. device performance. And it is necessary to use very strict high grade mask layer for this p-type implantation for Type-A transistor, which cost too much. However, there s no need to use this layer and make the process easier, more repeatable and stable for Type-B transistor. Table 1. Main device parameters comparison between Type-A and Type-B Parameter Type-A Type-B Current gain Peak f T (GHz) Peak f max (GHz) BV ceo(v) BV cbo (V) BV ebo (V) r I B = 4e-6 A / ko C 0 V / ff IV. Conclusion Two novel structures dedicated for vertical bipolar transistor on thin-film SOI are proposed and simulation study is carried out with good device performances following the existing 0.13µm SOI-CMOS design rules. These two bipolar structures are fully compatible with the current SOI-CMOS process and are promising for SOI-CMOS mix-signal applications. Fig. 11. f T vs. I C with different W V ST I, L ISO and L OV L2 Fig. 12. f max vs. I C with different W V ST I, L ISO and L OV L2 3. Transistor characteristics comparison, Type-A vs. Type-B Type-A and Type-B vertical bipolar transistors following 0.13µm SOI-CMOS design rule are compared in Table 1. Compare to Type-A transistor, Type-B transistor exhibits better device characteristics except for the peak f T value. The space between n + poly emitter and p + poly base leading-out causes C BC to increases in Type-B transistor, which slightly degrades f T. The process conditions are all the same except for p-type implantation for base interconnection in Type-A. L OV L1 cannot be too small due to the capability of the litho-scanner for the p-type base interconnection implantation, which leads to f max significant degradation because of the increase of r b shown in Table 1. So this implantation needs excellent photoresist CD and overlay control to prevent from degrading the References [1] L. Larson, Device and technology requirements for next generation communications systems, IEDM Tech. Digest, pp , [2] T.H. Ning, Why BiCMOS and SOI BiCMOS, IBM Journal of Research and Development, Vol.46, No.2/3, pp , Mar./May [3] G.G. Shahidi et al., A Novel High-performance Lateral Bipolar on SOI, IEDM 91 Technical Digest, pp.663, [4] Stephen Parke et al., A Versatile, SOI BiCMOS Technology with Complementary Lateral BJT s, IEDM 92 Technical Digest, pp , [5] T. Shino et al., A 31GHZ fmax Lateral BJT on SOI Using Self-Aligned External Base Formation Technology, IEDM 98 Technical Digest., pp , [6] Sun I-Shan Michael et al., Novel ultra-low power RF Lateral BJT on SOI-CMOS compatible substrate, 2005 IEEE Conference on Electron Devices and Solid-State Circuits, pp , [7] E.W. Greeneich, R.H. Reuss, Vertical n-p-n bipolar transistors fabricated on buried oxide SOI, IEEE Electron Device Letters, Vol.EDL-5, No.3, March [8] O.W. Purbo, C.R. Selvakumar, High-gain SOI polysilicon emitter transistors, IEEE Electron Device Letters, Vol.12, No.11, Nov [9] C. Davis et al., UHF-1: A high speed complementary bipolar analog process on SOI, IEEE Proceeding of BCTM 92, pp , Oct [10] S. Nigrin et al., A complementary bipolar technology on SOI featuring 50GHz NPN and 35GHz PNP devices for high performance RF applications, IEEE SOI Conference, pp , Oct [11] Qiqing Ouyang, Jin Cai, Tak H. Ning et al., A simulation study on thin SOI bipolar transistors with fully or partially depleted collector, IEEE BCTM.1, pp.28 31, [12] Jin Cai, Tak H. Ning, Bipolar transistors on thin SOI: Concept, status and prospect, Proc. of IEEE Int. Conf. on Solid State and IC Technology, pp , 2004.

5 616 Chinese Journal of Electronics 2011 [13] I-Shan Michael Sun, Wai Tung Ng et al., Lateral high-speed bipolar transistors on SOI for RF SoC applications, IEEE Trans. on Electron Devices, Vol.52, No.7, July [14] Sentaurus Device User Guide, Version A, [15] D.B.M. Klaassen, A unified mobility model for device simulation-i. Model equations and concentration dependence, Solid-State Electronics, Vol.35, No.7, pp , ZHOU Jianhua was born in Jiangsu Province, China in Jan He received the B.S. degree in microelectronics from Xidian University, Xi an, China in 2006 and now is a Ph.D. candidate in microelectronics of Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China. His research interest is in the process development of logic, RF, SOI and BiCMOS and the characterization of SOI devices. In 2007, he joined Grace Semiconductor Manufacturing Corporation, Shanghai, China. He is an internship engineer in the Memory Group, Technology Department at Grace in charge of SOI CMOS/BiCMOS process development and device characterization. ( jianhua.zhou@gracesemi.com) S.K. Pang received the B.S. degree in electrical engineering from the National Taiwan University, Taipei, Taiwan, in 1982, the M.S. degree in physics from Georgia State University in 1984, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in His research interests include silicon processing, characterization, and device modeling. He joined Grace Semiconductor Manufacturing Corporation, Shanghai, China in July 2006, and is an industry veteran with 17 years experience in the semiconductor industry. Prior to joining Grace, he held various engineering and management positions in foundry companies including TSMC, SMIC, and Chartered. ZOU Shichang materials scientist, and academician of the Chinese Academy of Sciences. He graduated from Tangshan Jiaotong University in 1952, and received the associate doctor s degree from Moscow Nonferrous Metals College in He was appointed as the visiting professor of Fraunhofer-Gesellschaft Solid Technological Research Institute from 1979 to 1980, and successively held roles of Director of Shanghai Institute of Microsystem and Information Technology, CAS (originally the Shanghai Institute of Metallurgy, CAS), Vice Chairman of Shanghai Hua Hong NEC Electronics Co., Ltd., Chairman of Shanghai Grace Semiconductor Manufacturing Corporation, and President of Shanghai Pudong Association for Science and Technology. Currently he serves as a Researcher and Ph.D. Supervisor of Shanghai Institute of Microsystem, Chief Director of Shanghai Integrated Circuit Industry Association, Science Consultant of Shanghai Grace Semiconductor Manufacturing Corporation, and also Honorary Member of International Committee of the International Ion Implantation Materials Modification Academic Conference. He was elected as an Academician of the Chinese Academy of Sciences in Prof. Zou won the 1st Prize of National Invention, as well as 14 awards of the CAS such as the Natural Science Award and the Scientific and Technological Progress Award, etc. He published more than 200 papers, and mentored over 30 Ph.D. students. Zou was elected Outstanding Talent in Shanghai Pudong Development and Construction in 2003; and awarded China Semiconductor Industry Pathfinder Award by the Semiconductor Equipment and Materials International (SEMI) in 2008.