Design of High Performance Lateral Schottky Structures using Technology CAD

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1 Design of High Performance Lateral Schottky Structures using Technology CAD A dissertation submitted in partial fulfillment of the requirement for the degree of Master of Science (Research) by Linga Reddy C Entry No. 2000EEM0 Under the Supervision of Dr. M. Jagadesh Kumar Department of Electrical Engineering, Indian Institute of Technology, Delhi May 5, 2003

2 Certificate This is to certify that the thesis entitled "Design of High Performance Lateral Schottky Structures using Technology CAD" being submitted by Linga Reddy C (2000EEM0), for the award of degree of Master of Science (Research) in Electrical Engineering to the Indian Institute of Technology, Delhi, is a record of bonafide work done by him under my guidance and supervision. It is further certified that this work has not been submitted anywhere else for the award of degree or diploma. Date: Dr. M. Jagadesh Kumar Associate Professor Dept. of Electrical Engineering Indian Institute of Technology, Delhi

3 Acknowledgement I wish to express my heartfelt gratitude to my supervisor Dr. M. Jagadesh Kumar for his invaluable guidance and advice during every stage of this endeavour. I am greatly indebted to him for his continuing encouragement and support without which, it would not have been possible for me to complete this undertaking successfully. I would like to thank Council of Scientific and Industrial Research (CSIR), Government of India, for supporting me in my research. I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory facilities at all points of time. I am thankful to Mr. Ritesh Kumar Sharma and Mr. K. C. Sharma for their valuable assistance during my project work. Sincere thanks to research students D. Venkateshrao, Vinod Parihar, Anurag Chaudhury and G. V. Reddy and also to research scholar S. D. Roy and M.Tech. student K. Pavan Kumar for their valuable suggestions and discussions during the project work. Finally, I am very thankful to those who directly or indirectly assisted me in completion of this work.

4 Abstract Schottky junctions are well known for their low forward drop and insignificant storage effects. Their application in both the two-terminal and three-terminal devices to enhance the high-speed performance has gained importance due to the technological ability to prepare extremely clean semiconductor surfaces. In the recent past, several novel rectifier as well as transistor structures have been reported using Schottky junctions. SiC Schottky rectifiers have several advantages in high temperature, high speed and high voltage applications. Although a number of vertical SiC Schottky rectifiers have been reported in literature, lateral Schottky rectifiers are increasingly becoming important because of their utility in power ICs. Due to it s excellent material properties of SiC, device designers have started using it as emitter in high-performance HBTs where as SiGe is an excellent semiconductor for RF applications. Replacing the collector-base p-n junction by a Schottky junction in BJTs has been proposed to reduce the collector resistance, base widening and to improve the transient response of the transistor. But all these proposed devices are vertical in nature and not compatible with standard CMOS processes, so they could not gain wider acceptability in VLSI BiCMOS applications. In the present work, to enhance the performance limits of Schottky rectifiers and HBTs, we have proposed four high performance BiCMOS compatible lateral Schottky devices in Silicon-On-insulator (SOI) technology namely, 1) A Novel high voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) rectifier, 2) Lateral Dual Sidewall Schottky (LDSS) concept for improved rectifier performance on SOI, 3) A Novel lateral N-SiC emitter P-SiGe base Schottky Metal-collector (NPM) HBT on SOI and 4) A New lateral dual bandgap P-emitter N-SiGe base Schottky Metalcollector (PNM) HBT on SOI with reduced collector emitter offset voltage. We have used carefully calibrated two-dimensional simulations to study the characteristics of the proposed devices in this work. Based on the simulated results, we have analyzed the reasons for the improved performance of the proposed structures over the conventional devices. We have also presented a BiCMOS compatible fabrication procedure for all our proposed devices. The results presented in our work are expected to be an incentive for further experimental exploration by other researchers.

5 Contents 1 Introduction Applications and the necessity of lateral devices on SOI Previous work Objectives of the thesis Thesis organization A Novel High Voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) Rectifier with Ideal Forward and Reverse Characteristics Introduction LDSS Structure and parameters Fabrication steps for the LDSS rectifier Simulation results and discussion (A) Barrier height lowering model (B) Forward and reverse characteristics Conclusions Application of Lateral Dual Sidewall Schottky (LDSS) Concept for Improved Rectifier Performance on SOI Introduction Device structure and parameters Simulation results and discussion Conclusions... 25

6 4 2D-Simulation and Analysis of Lateral SiC N-emitter SiGe P-base Schottky Metal-collector (NPM) HBT on SOI Introduction Proposed device structure and its parameters Fabrication steps for the proposed NPM HBT Simulation results and discussion (A) DC Performance (B) Dynamic behaviour analysis (C) Performance at high temperature Conclusions A New Lateral Dual bandgap P-Emitter N-SiGe base Schottky Metal-collector (PNM) HBT on SOI with Reduced Collector-Emitter Offset Voltage Introduction Comparison of V CE(Offset) problem in wide bandgap emitter NPN/PNP HBTs Dual bandgap approach to reduce the V CE(Offset) in SiC emitter PNP HBTs Application of SiGe base to the dual bandgap emitter PNP HBT Application of Schottky collector to the dual bandgap emitter SiGe base PNP HBT and its impact on device performance The effect of doping and Ge % in the base Proposed fabrication procedure Conclusions Conclusions Appendices References Publications from this work... 91

7 Chapter 1 Introduction 1.1 Applications and necessity of lateral devices on SOI Schottky junctions are well known for their low forward drop and insignificant storage effects. Though several vertical Schottky rectifiers with improved performance are reported [1-3] in the literature, lateral Schottky rectifiers are becoming more popular due to easy integration of these devices into CMOS and BiCMOS process technologies. For RF and mixed signal circuits, high performance (High current gain, high cut-off frequency and high transconductance) transistors are necessary. The RF performance of high-frequency transistors is limited by the parasitic RC time constants arising from the series resistances and shunting capacitances of the transistors. Control of these parasites is a key issue in the development of advanced transistors. In this context, the SOI technology has emerged as a best technology to alleviate the above problem and support the needs of VLSI applications. Recently, lateral bipolar transistors [4-] have been implemented on SOI technology by taking the full advantages of SOI technology. Although the conventional vertical HBTs on bulk substrate will meet most of the performance requirements for RF applications, complicated fabrication processes of these devices is the major drawback and this leads to uneasy integration of these device into BiCMOS technology subsequently which leads to the high cost of technological development and manufacturing. On the other hand, the present SOI lateral HBT is 1

8 easily integrable with SOI BiCMOS technology. In the most simplified process, SOI BiCMOS integration will be possible with few extra masks and ion implants with minor modification of standard CMOS process. SOI BiCMOS technology for mixed signal applications has been a very attractive alternative to its bulk counterpart as it offers the advantages such as (i) Reduced analog-to-digital crosstalk noise, (ii) Decrease of sensitivity to alpha particles, (iii) Reduction of substrate capacitance and (iv) Better device isolation. Therefore, the use of lateral HBTs in SOI BiCMOS should lead to realization of the above advantages with no added process complexity. 1.2 Previous work SiC Schottky rectifiers have several advantages in high temperature, high speed and high voltage applications [11]. Although a number of vertical SiC Schottky rectifiers have been reported in literature [12], lateral Schottky rectifiers are increasingly becoming important because of their utility in power ICs [13-15]. Recently, Kumar and Singh [15] have reported that Schottky rectifiers with sharp reverse breakdown can be achieved using the sidewall Schottky contact of a trench filled with a metal. Selecting a metal for this Lateral Trench Sidewall Schottky (LTSS) rectifier with a suitable work-function plays a vital role in deciding its forward and reverse characteristics. If a low-barrier metal is used for the Schottky contact in the LTSS rectifier, it will result in a low forward voltage drop but the reverse leakage current will be large and vice-versa for a high-barrier Schottky contact. Achieving both the low forward voltage drop and less reverse leakage current in LTSS rectifier is impossible without making a trade off between forward voltage drop and reverse 2

9 leakage current. In this work we propose a novel concept called Lateral Dual Sidewall Schottky (LDSS) for both SiC and Si to overcome the above problem. Replacing the collector-base p-n junction by a Schottky junction in BJTs has been proposed [16] to reduce the collector resistance, base widening and to improve the transient response of the transistor. But these Schottky structures are vertical in nature and not compatible with standard CMOS processes, so they could not gain wider acceptability in VLSI BICMOS applications. Recently, it has been shown that lateral Schottky BJTs which are compatible with BiCMOS technology can also be made [17]. Further, to improve the performance of BJTs, device designers have started recognizing the utility of wide bandgap emitter (e.g. SiC emitter [18]) and narrow bandgap base (e.g. SiGe base) in BJTs for high speed circuit applications. To combine the advantages of SiC-emitter and SiGe-base together with the combination of SOI technology and lateral Schottky collector, in this work we propose a novel SiC emitter SiGe base lateral NPM Schottky collector HBT on SOI. Wide bandgap HBTs are, however, prone to an increased collector-emitter offset voltage and this problem is more severe in PNP HBTs. As a result, making PNP HBTs which are compatible with NPN HBTs is very difficult. To overcome this problem, we propose a novel technique in which a dual bandgap emitter is used. 1.3 Objectives of the thesis The main objective of this thesis is to propose novel lateral Schottky structures for high speed applications. The structures we have studied are: i) A Novel high voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) rectifier, ii) Application of Lateral Dual Sidewall Schottky (LDSS) concept for improved rectifier performance on SOI, 3

10 iii) A Novel lateral N-SiC emitter P-SiGe base Schottky Metal-collector (NPM) HBT on SOI and iv) A New lateral dual bandgap P-emitter N-SiGe base Schottky Metalcollector (PNM) HBT on SOI with reduced collector emitter offset voltage. From our simulation study, we demonstrated that LDSS rectifier exhibits low forward drop as well less reverse leakage current and proposed HBTs exhibit excellent performance over its counterparts. We have also presented a BiCMOS compatible fabrication procedure for all our proposed devices. We have shown from our simulation results that the proposed LDSS rectifiers attractive for use in high-speed and low-loss power IC applications and proposed HBTs are attractive for high frequency and low power BiCMOS VLSI applications. 1.4 Thesis organization The dissertation is divided into six chapters and its outline is described as given below. Chapter One: Introduction. Fundamental concepts related to Lateral devices and SOI, previous work, objectives and organization of the thesis. Chapter Two: A Novel high voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) rectifier with ideal forward and reverse characteristics. This chapter introduces a new concept called Lateral Dual Sidewall Schottky (LDSS) to attain the low forward voltage drop which is close to that of a Schottky rectifier with low barrier metal as well as less reverse leakage current which is close to that of a Schottky rectifier with high barrier metal. 4

11 Chapter Three: Application of Lateral Dual Sidewall Schottky (LDSS) concept for improved rectifier performance on SOI. This chapter demonstrates the application of Lateral Dual Sidewall Schottky (LDSS) concept on SOI to get the improved performance over its equivalent devices namely Lateral Conventional Schottky (LCS) and Lateral Trench Sidewall Schottky (LTSS) rectifiers. Chapter Four: 2D-Simulation and analysis of a novel SiC N-emitter SiGe P- base lateral Schottky Metal-collector (NPM) HBT on SOI. This chapter describes the design and analysis of SiC wide bandgap N-emitter and P-SiGe base lateral Schottky Metal-collector (NPM) HBT on SOI. Chapter Five: A New dual bandgap P-emitter SiGe N-base lateral Schottky Metal-collector (PNM) HBT on SOI with reduced collector emitter offset voltage. This chapter presents a novel solution to deal with the offset voltage problem in wide bandgap emitter PNP/PNM HBTs. Chapter Six: Conclusions. 5

12 Chapter 2 A Novel High Voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) Rectifier with Ideal Forward and Reverse Characteristics 2.1 INTRODUCTION SiC Schottky rectifiers are now well known for their advantages in high temperature, high speed and high voltage applications [11]. Although several vertical SiC Schottky rectifiers have been reported in literature [12], lateral Schottky rectifiers are increasingly becoming important because of their utility in power ICs [13-15]. Recently, Kumar and Singh [15] have demonstrated that Schottky rectifiers with high breakdown voltage and PiN diode like sharp reverse breakdown can be achieved using the sidewall Schottky contact of a trench filled with a metal. Selecting a metal for this Lateral Trench Sidewall Schottky (LTSS) rectifier with a suitable workfunction plays a vital role in deciding its forward and reverse characteristics. If a lowbarrier metal is used for the sidewall Schottky contact in the LTSS rectifier, it will result in a low forward voltage drop but the reverse leakage current will be large and vice-versa for a high-barrier Schottky contact. However, it would be ideal if the Schottky rectifier has both low forward voltage drop as well as low reverse leakage current. This is impossible to obtain in a LTSS rectifier without making a trade-off between forward voltage drop and the reverse leakage current. In order to overcome this, for the first time, we propose a Lateral Dual Sidewall Schottky (LDSS) rectifier in which the low-barrier sidewall Schottky conducts during forward bias and the high- 6

13 barrier sidewall Schottky conducts during the reverse bias. Based on simulation results, we demonstrate that the forward characteristics of the proposed LDSS structure are close to that of the low-barrier LTSS rectifier and the reverse characteristics are close to that of the high-barrier LTSS rectifier resulting in a near ideal Schottky rectifier. The reverse breakdown of the LDSS structure is also very sharp and is similar to that of a PiN diode. In the following sections, we report the results on this unique and highly desired I-V characteristics of the proposed 4H-SiC LDSS rectifier and analyze the reasons for the improved performance. Anode Cathode L FP d l HBS LBS Field Oxide t ox d h 4H-SiC N-drift region t N + Semi-insulating 4H-SiC Substrate Fig. 2.1 Cross-sectional view of the 4H-SiC Lateral Dual Sidewall Schottky (LDSS). 2.2 LDSS STRUCTURE AND PARAMETERS Schematic cross-sectional view of the 4H-SiC LDSS rectifier implemented in the 2- dimensional device simulator MEDICI [19] is shown in Fig

14 The anode of the LDSS rectifier consists of a high barrier Schottky (HBS) metal (Nickel with φ BH = 1.50 ev) on top of the low barrier Schottky (LBS) metal (Titanium with φ BL = 0.85 ev). These two metals are commonly used in SiC Schottky rectifiers [11]. Electric field crowding at the trench edges is reduced by using a simple field plate termination. The ohmic cathode contact is taken from the N + region. To optimize the device parameters, we first fixed the thickness (t), doping (N D ) and drift region length (L) then varied the low-barrier Schottky trench depth (d l ) and highbarrier Schottky trench depth (d h ). The performance of the proposed device (LDSS) in terms of forward voltage drop (@0 A/cm 2 ) and Reverse Current density (@500 A/cm 2 ) are tabulated in Table-2.1 for various d l and d h. From this Table-2.1, we extracted the optimum value of the low-barrier Schottky trench depth (d l ) as 0.25 µm and the high-barrier Schottky trench depth (d h ) as 1.75 µm. Table 2.1: Forward voltage drop (@0 A/cm 2 ) and Reverse current density (@500 A/cm 2 ) for various d l and d h. t = 2 µm N D = 1 17 /cm -3 L = 5.5 µm t ox = 0.4 µm L FP = 4.5 µm d 1 + d h = 2 µm = t sic d l (µm) d h (µm) Forward voltage A/cm 2 Reverse current V E E E E E E E E E-01 8

15 To extract the optimum value of the field oxide thickness (t ox ), breakdown voltage and the reverse current density A/cm 2 ) of the proposed device (LDSS) are extracted from the simulation for various values of field oxide thickness and tabulated as shown in Table-2.2. From this Table-2.2, we extracted the optimum value of the field oxide thickness (t ox ), which is of 0.4 µm for the highest breakdown voltage. Table 2.2: Breakdown voltage and Reverse current density (@500 A/cm 2 ) for various t ox. Field oxide thickness, t ox (µm) t = 2 µm N D = 1 17 /cm -3 L = 5.5 µm L FP = 4.5 µm d 1 = 0.25 µm d h = 1.75 µm Breakdown voltage (V) Reverse Current A/cm E E E E E E E-05 Field plate length (L FP ), has been chosen to be of 4.50 µm such that the breakdown voltage of the proposed device is maximum. 9

16 The optimized device parameters used in the simulation for the 4H-SiC LDSS rectifier are given in Table-2.3. Table 2.3: Optimized MEDICI input parameters for the 4H-SiC LDSS rectifier. Parameter N + doping for ohmic contact Drift region doping, N D Drift region length, L Drift region thickness, t Field oxide thickness, t ox Field plate length, L FP Trench depth, d h Trench depth, d l Low Schottky barrier height (Ti), φ BL High Schottky barrier height (Ni), φ BH Richardson constant Value 20 cm cm µm 2.00 µm 0.40 µm 4.50 µm 1.75 µm 0.25 µm 0.85 ev 1.50 ev 140 A/cm 2 K FABRICATION STEPS FOR LDSS RECTIFIER The dual sidewall Schottky contact can be created in the 4H-SiC LDSS structure as shown in Fig We start with a semi-insulating 4H-SiC substrate with a 2.0 µm n- type 4H-SiC epitaxial layer doped at N D = 1 17 cm -3.

17 LBS Field Oxide 4H-SiC N-Drift region (a) Semi-insulating 4H-SiC Substrate LBS Field Oxide 4H-SiC N-Drift region (b) Semi-insulating 4H-SiC Substrate HBS Field Oxide LBS 4H-SiC N-Drift region (c) Semi-insulating 4H-SiC Substrate Fig. 2.2 Steps for creating dual metal sidewall Schottky contacts in 4H-SiC LDSS rectifier. The low-barrier Titanium metal of desired thickness can be first deposited in the trench as shown in Fig. 2.2(a). Using another mask and selective etch process, a second trench is made resulting in the low-barrier Schottky contact as shown in Fig. 2.2(b). Following this step, Nickel can be deposited to form the high-barrier Schottky 11

18 contact as illustrated in Fig. 2.2(c). The final structure will be as shown in Fig The proposed 4H-SiC LDSS rectifier is compared with the compatible 4H-SiC Lateral Conventional Schottky (LCS) and the Lateral Trench Sidewall Schottky (LTSS) rectifiers whose structures are similar to those reported in [15]. 2.4 SIMULATION RESULTS AND DISCUSSION 2.4 (A) Barrier height lowering model Simulation of SiC Schottky rectifiers is not easy because the measured reverse current density for 4H-SiC Schottky diodes has been reported to be much higher than predicted by thermionic emission theory and depends strongly on the applied voltage [20]. This discrepancy between measured and estimated reverse leakage current is due to the complex dependence of barrier height on image forces, surface inhomogeneities [21], depletion region generation [12], carrier tunneling [22] and also the barrier height fluctuations. Incorporating all these current flow mechanisms in the thermionic emission model is very difficult primarily because the fundamental physics taking place at the Schottky interface is not well understood. To overcome this problem, Singh and Kumar [11] have proposed a simple empirical model for the barrier height lowering ( φ B ) based on experimental results and have shown its application in twodimensional simulation of 4H-SiC Schottky rectifiers to accurately predict both the forward and reverse characteristics. The Singh-Kumar barrier height lowering model [11] for 4H-SiC Schottky structures can be expressed as φ B = a[e av ] 1/2 + b..eq (2.3) 12

19 where E av is the average electric field (V/cm) at the Schottky contact and a and b are constants. These constants have been reported to be a = V 1/2 cm 1/2 and b = V for Ti and a = V 1/2 cm 1/2 and b = V for Ni, the metals used in our study. We have implemented the above Singh-Kumar barrier lowering model for 4H-SiC in our 2-D numerical simulation and evaluated the performance of the proposed structure as discussed below. 2.4 (B) Forward and Reverse Characteristics Fig. 2.3 shows the simulated forward and reverse characteristics of the 4H-SiC lowbarrier and high-barrier LCS, low-barrier and high-barrier LTSS and the proposed Forward current density, J F [A/cm 2 ] Low-barrier LDSS LCS Low-barrier High-barrier LTSS LTSS High-barrier LCS Forward voltage drop, V F [V] Fig. 2.3 Forward conduction characteristics of the lowbarrier and high-barrier LCS, low-barrier and high-barrier LTSS and LDSS rectifiers. LDSS rectifiers. From Fig. 2.3, we observe that the forward characteristic of the LDSS rectifier is close to that of low-barrier LCS or LTSS rectifier as most of the current flows through low-barrier Schottky contact during forward bias as shown by 13

20 the current vectors in Fig The forward voltage drop of the proposed LDSS structure is approximately 0.55 V at a current density of 0 A/cm Distance, µm Distance, µm Fig. 2.4 Current flow vectors in the LDSS rectifier at a forward current density of 0A/cm 2. As it is clear from Fig. 2.4 that low-barrier Schottky metal in the proposed device (LDSS) plays a key role under forward bias. 14

21 From Fig. 2.5, we note that the reverse leakage current of the LDSS rectifier is very low and is close to that of the high-barrier LCS and LTSS rectifiers. This is because during the reverse bias the low-barrier Schottky is shielded by the depletion region and most of the reverse current flows through the high-barrier Schottky contact. Reverse current density, J R [A/cm 2 ] Low-barrier LCS Low-barrier LTSS High-barrier High-barrier LCS LTSS LDSS Reverse voltage, V R [V] Fig. 2.5 Reverse blocking characteristics of the lowbarrier and high-barrier LCS, low-barrier and high-barrier LTSS and LDSS rectifiers. This is because during the reverse bias the low-barrier Schottky is shielded by the depletion region and most of the reverse current flows through the high-barrier Schottky contact. This can be seen from the reverse current vectors of the LDSS rectifier shown in Fig We also note that the reverse current of both the lowbarrier and high-barrier LCS rectifiers increases very rapidly with increasing reverse voltage resulting in an extremely soft breakdown at 230 V. However, the breakdown voltage of the LDSS rectifier is very large at ~ 00 V (more than four times the breakdown voltage of LCS rectifiers.). This is because the breakdown of the LDSS 15

22 structure takes place below the right edge of the field plate (away from the Schottky contact) [15] Distance, µm Distance, ìm Fig. 2.6 Current flow vectors in the LDSS rectifier At a reverse bias of 500 V. To understand this behavior, the electric field is plotted in Fig. 2.7 along the horizontal line at the field-oxide / 4H-SiC interface of low-barrier and high-barrier LCS, low-barrier and high-barrier LTSS and LDSS rectifiers near the breakdown voltage of the LCS rectifier (230 V). We note from Fig. 2.7 that in the case of lowbarrier and high-barrier LCS rectifiers, the peak electric field occurs at the Schottky junction resulting in a large barrier lowering as shown in Fig This leads to a soft and low breakdown in the case of low-barrier and high-barrier LCS rectifiers. 16

23 Electric field [1 6 V/cm] LCS LDSS (Low & High-barrier) LTSS (Low & High-barrier) Distance, µm Fig. 2.7 Electric field variation along the horizontal line at the field-oxide / 4H-SiC interface of low-barrier and high-barrier LCS, low-barrier and high-barrier LTSS and LDSS rectifiers near its breakdown voltage. But, the proposed LDSS structure exhibits a very sharp breakdown similar to that of a PiN diode in spite of using only Schottky junctions in the structure. This is due to the reduced electric field at the Schottky contact which in turn results in a significantly diminished barrier lowering ( φ B ) for the LDSS structure as shown in Fig

24 Barrier lowering, φ B [ev] High-barrier LCS LDSS ( φ BH ) Low-barrier LCS High-barrier LTSS Low-barrier LTSS LDSS ( φ BL ) Reverse voltage, V R [V] Fig. 2.8 Barrier height lowering as a function of reverse bias voltage for the low-barrier and high-barrier LCS, low-barrier and high-barrier LTSS and LDSS rectifiers. A useful figure of merit for rectifiers which combines the current carrying capability under forward bias and blocking capability under reverse bias, is the on/off current ratio [20] defined at fixed forward (1 V) and reverse biases ( 500 V). Taking the J-V characteristics into consideration, the calculated on/off current ratio for the LDSS rectifier is of about at 1 V/-500 V for an epitaxial layer doping of 1 17 /cm 3, which is same as the on/off current ratio obtained by considering the forward characteristic of the low-barrier LTSS and reverse characteristic of the highbarrier LTSS. In other words, the LDSS structure combines the benefits of the lowbarrier LTSS and high barrier LTSS rectifiers resulting in an ideal Schottky rectifier. 18

25 2.5 CONCLUSION A novel high-voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) rectifier has been presented. Using 2-dimensional simulation, we have demonstrated that the forward characteristic of the proposed LDSS rectifier is close to that of a low-barrier LTSS rectifier and its reverse characteristic is close to that of a high-barrier LTSS rectifier, resulting in an on/off current ratio of An interesting feature of the proposed LDSS rectifier is that it exhibits a sharp breakdown similar to that of a PiN diode in spite of using only Schottky junctions in the LDSS structure. The combined low forward voltage drop, low reverse leakage current and excellent reverse blocking capability make the proposed LDSS rectifier attractive for use in low-loss, highvoltage and high-speed power IC applications. 19

26 Chapter 3 Application of Lateral Dual Sidewall Schottky (LDSS) Concept for Improved Rectifier Performance on SOI 3.1 INTRODUCTION SiC is a special material and still has problems with regard to the quality of the epitaxial films. However, silicon is a well understood material and it is not very difficult to get high quality silicon films on SOI. Therefore, to generalize the Lateral Dual Sidewall Schottky (LDSS) concept and to examine how a silicon based LDSS structure performs, we have studied the implementation of the LDSS rectifier on SOI. Based on simulation results, we demonstrate that the forward characteristics of the proposed LDSS rectifier on SOI are close to that of the low-barrier Lateral Trench Sidewall Schottky (LTSS) rectifier and its reverse characteristics are close to that of the high-barrier Lateral Trench Sidewall Schottky (LTSS) rectifier. The detailed analysis and the reasons for the improved performance of the proposed LDSS rectifier on SOI are presented by comparing its performance with the compatible Lateral Conventional Schottky (LCS) and Lateral Trench Sidewall Schottky (LTSS) rectifiers [15] on SOI in the following sections. 3.2 DEVICE STRUCTURE AND PARAMETERS Cross sectional view of the proposed Lateral Dual Sidewall Schottky (LDSS) rectifier on SOI implemented using two dimensional device simulator MEDICI [19] is shown in Fig

27 Anode Cathode HBS LBS d l L FP d h Field Oxide N Drift region Buried Oxide N + -Substrate tox N + t N + Fig. 3.1 Cross sectional view of the proposed Lateral- -Dual Sidewall Schottky (LDSS) rectifier on SOI. The anode consists of both the low-barrier Schottky contact as well as highbarrier Schottky contact. Nickel (φ BL = 0.57 ev) is chosen for the low-barrier Schottky contact and Tungsten (φ BH = 0.67 ev) is chosen for high-barrier Schottky contact as these two are the well studied and most commonly used metals for Schottky contacts. The cathode contact is taken from the N + region. Field plate with a length of 3.5 µm is used to avoid the electric field crowding at the Schottky contact. Drift region doping (N D ) is chosen to be 5 16 cm -3 and its thickness is 0.5 µm. Field oxide thickness is 0.2 µm and buried oxide thickness is 2 µm. High-barrier Schottky trench depth is chosen to be 0.4 µm and low barrier Schottky trench depth is chosen to be 0.1 µm as this combination gives the low forward voltage drop as well as less reverse leakage current. Most of these parameters are chosen based on the works reported in the literature [15]. 21

28 Fabrication procedure for making lateral dual sidewall Schottky contacts is same as that discussed in chapter SIMULATION RESULTS AND DISCUSSION Fig. 3.2 shows the simulated forward IV characteristics of the proposed Lateral Dual Sidewall Schottky (LDSS) rectifier on SOI and is compared with the compatible Lateral Conventional Schottky (LCS) and Lateral Trench Sidewall Schottky (LTSS) rectifiers on SOI. Forward current density, J F [A/cm 2 ] Low-barrier LCS Low-barrier High-barrier LTSS LTSS High-barrier LCS LDSS Forward voltage drop, V F [V] Fig. 3.2 Forward IV characteristics of the proposed LDSS rectifier and is compared with LCS and LTSS rectifiers. It can be observed from the figure that the forward characteristic of the proposed LDSS rectifier is close to that of low-barrier LCS and LTSS rectifiers as low-barrier Schottky contact plays an essential role in providing most of its current. 22

29 Simulated reverse IV characteristics of the proposed LDSS rectifier on SOI and its compatible Lateral Conventional Schottky (LCS) and Lateral trench Sidewall Schottky (LTSS) rectifiers on SOI are shown in Fig Reverse current density, J R [A/cm 2 ] Low-barrier Low-barrier High-barrier LCS LTSS LTSS High-barrier LCS LDSS Reverse voltage, V R [V] Fig. 3.3 Reverse IV characteristics of the proposed LDSS rectifier and is compared with LCS and LTSS rectifiers. From the above figure, we can observe that low-barrier and high-barrier LCS rectifiers exhibit a lower breakdown voltage due to large peak electric field at the Schottky contact as shown in Fig. 3.4 where as low-barrier and high-barrier LTSS rectifiers exhibit higher breakdown voltage. This improvement is due to the shifting of peak electric field from Schottky contact to the field plate edge [15] as shown in the Fig Further, it can be observed that the reverse leakage current of both the low-barrier LCS and LTSS rectifiers is quite high as compared to high-barrier LCS and LTSS rectifiers. 23

30 Electric field [1 5 V/cm] LCS (Low & High-barrier) LTSS (Low & High-barrier) LDSS Distance, µm Fig. 3.4 Electric field variation along the horizontal line at the Si/SiO 2 interface of LCS, LTSS and LDSS rectifiers near the breakdown voltage. The reverse leakage current of the proposed LDSS rectifier on SOI is close to that of high-barrier LCS and LTSS rectifiers as the low-barrier Schottky metal of the proposed LDSS rectifier is pinched off and high-barrier Schottky alone is responsible for the current conduction during the reverse bias. 24

31 3.4 CONCLUSION From our simulation analysis we conclude that the proposed Lateral Dual Sidewall Schottky (LDSS) rectifier on SOI behaves as a low-barrier Lateral Trench Sidewall Schottky (LTSS) rectifier on SOI and it behaves as a high-barrier Lateral Trench Sidewall Schottky (LTSS) rectifier on SOI under reverse bias conditions which makes it to achieve both the low forward voltage drop as well as less reverse leakage current. The combined low forward voltage drop, less reverse leakage current and excellent reverse blocking capability make the proposed LDSS rectifier attractive for use in high-speed and low-loss power IC applications. 25

32 Chapter 4 2D-Simulation and Analysis of Lateral SiC N-emitter SiGe P-base Schottky Metal-collector (NPM) HBT on SOI 4.1 INTRODUCTION Due to its excellent material properties such as wide bandgap, high thermal conductivity, high saturated electron drift velocity and ability to operate at high temperatures [23 25], silicon carbide (SiC) is an attractive choice in many applications such as military, satellite and intelligent control systems. Device designers have started recognizing the utility of SiC as an emitter in HBTs to take the full advantages of its excellent material properties together with its fabrication compatibility with silicon. In the past, several structures were reported in literature [18, 26] with SiC as emitter in HBTs. But all these were vertical in nature and not compatible with standard CMOS processes so they could not gain wider acceptability in VLSI BICMOS applications. SiGe is a promising semiconductor for the applications involved in high speed circuits such as RF circuits (PAs, LNAs, modulators, mixers, VCOs etc.), mixed signal circuits (Analog to digital converters, digital to analog converters, fractional N synthesizers etc.) and in the precision analog circuits (Op Amps, bandgap references, temperature bias control and current mirrors). In the literature, several SiGe HBTs were reported with the above advantages. While the SiC/Si and SiGe/Si based HBTs have several advantages, they also suffer from many non-ideal effects such as base widening at high collector currents and excessive base storage time. To overcome this problem, one can use a Schottky 26

33 collector either as a vertical structure [16] or as a lateral structure on SOI [17]. However, to combine the advantages of SiC and SiGe with the combination of SOI technology and lateral Schottky collector, for the first time, we propose a novel SiC emitter SiGe base lateral NPM Schottky collector HBT. To the best of our knowledge this is the first work to suggest the integration of SiC emitter SiGe base, lateral Schottky collector and SOI for BiCMOS applications providing an incentive for further experimental exploration. We evaluated the performance of the proposed NPM HBT and its equivalent NPN HBT and NPM BJT structures using two-dimensional device simulator ATLAS [27]. From our simulation results, we observe that the proposed NPM HBT exhibits improved performance in terms of high current gain, high cut-off frequency, suppressed Kirk effect, ability to operate at high temperatures and excellent transient response (with almost zero base storage time) over its compatible NPN HBT and NPM BJT structures. The proposed device structure, a feasible fabrication process compatible with BiCMOS process, steady state and dynamic behavior analysis are presented in the subsequent sections. 4.2 PROPOSED DEVICE STRUCTURE AND ITS PARAMETERS Top and cross-sectional view of the proposed NPM HBT (SiC emitter SiGe base lateral Schottky collector HBT), implemented in the two-dimensional device simulator ATLAS [27] is shown in Fig The emitter SiC region can be formed by well defined lateral growth processes [28-31]. The base region is converted into SiGe using Ge implantation. The Schottky metal collector is at the right edge of the base. A highly doped P + -poly is deposited on the p-type SiGe base region to take the base contact. 27

34 Base Emitter Collector 1µ m A A (a) E B C 0.20µ m 0.38µ m N + P 3.8µ m P N 0.4µ m Oxide N- substrate (b). Fig. 4.1 (a) Top and (b) cross-sectional view of the proposed NPM HBT (SiC emitter SiGe base lateral Schottky collector HBT on SOI). 28

35 Palladium silicide is chosen for the Schottky collector as it gives the highest barrier height (0.7 ev) with p-type SiGe (20% Ge) as reported in the literature [32 33] based on experimental results. The proposed NPM HBT is compared with compatible NPN HBT and NPM BJT devices, which have exactly the same dimensions and impurity profiles of the proposed NPM HBT except that to make the comparison more effective we set the collector doping of the NPN HBT to be 2 17 cm -3 such that collector breakdown voltage BV CEO matches approximately with that of NPM HBT for zero base current. The compared NPN HBT is same as that of the proposed NPM HBT except that its collector is of silicon material. The compared NPM BJT is same as that of proposed NPM HBT except that its emitter and base are of silicon material. Table 1: ATLAS input parameters for the proposed NPM HBT, NPN HBT and NPM BJT. Parameter Value SOI thickness t si (Initially) 0.20 µm Buried oxide thickness t box Field oxide thickness t ox Emitter length Base length Emitter region doping concentration Base region doping concentration Collector region doping concentration (Only for NPN HBT) Barrier height lowering coefficient SRH concentration parameter for electrons and holes NSRHN and NSRHP(Both for Si and SiGe) 0.38 µm 0.18 µm 3.80 µm 0.40 µm 5x 19 cm -3 5x 17 cm -3 2x 17 cm x -7 cm 1x 22 cm -3 29

36 The ATLAS [27] input parameters for the proposed NPM HBT and those of the compatible NPN HBT and NPM BJT are listed in table. 1. These parameters are chosen based on reported experimental results for lateral bipolar transistors on SOI [8]. 4.3 FABRICATION STEPS FOR THE PROPOSED NPM HBT We start with an SOI wafer having a p-type epitaxial layer of 0.2 µm thickness and a doping of 5 x 17 cm -3. We first deposit a thick CVD oxide and pattern as shown in Fig. 4.2(a). In the next step, we epitaxially grow the n + SiC on the vertical edge (at point A in Fig. 4.2(b)) of the silicon surface which acts as a seed for the lateral growth of SiC [28-31] as shown in Fig. 4.2(b). Subsequent to this step, CMP process is performed and then by depositing a thick CVD oxide, it is patterned as shown in Fig. 4.2(c). Following this step, a nitride film is deposited as shown in Fig. 4.2(d) and is etched using an unmasked RIE etch such that a nitride spacer is retained at the vertical edge of thick CVD oxide as shown in Fig. 4.2(e). Next, a thick CVD oxide is deposited as shown in Fig. 4.2(f) and by using CMP process, the surface is planarized. After this step, the nitride spacer is removed with selective etching to create a window in the oxide as shown in Fig. 4.2(g). To create the SiGe base region, we now need to implant Ge through this window. It has been shown in literature [34-37] that Ge implantation is a useful technique to create SiGe regions. Energies in the range of 130 KeV and fluences of the order of 3 x 16 cm -2 can be used for this purpose. This needs to be followed by a rapid thermal annealing for at least s to recrystallize the amorphous SiGe region [37]. In our simulations we have assumed a maximum Ge concentration of 20% which is the maximum limit for most practical applications [38-39]. 30

37 LTO Substrate P (a) N Substrate P (f) N SiC A Substrate P (b) N Substrate P (g) P + Poly N P (c) N P (h) Substrate Substrate N Si 3 N 4 Substrate P (d) N Substrate P (i) N Substrate P (e) N Substrate P (j) Fig. 4.2 Fabrication steps for the proposed NPM HBT. 31

38 After converting, silicon in the base region to SiGe, we then deposit p + -poly. Next, by using CMP process, the wafer is once again planarized. At the end of this step, only p + - poly will be present in the window as shown in Fig. 4.2(h). Following this step, a contact window is opened for metal Schottky collector as shown in Fig. 4.2(i) and subsequent to this step, n + emitter contact window is opened as shown in Fig. 4.2(j). Finally, palladium silicide is deposited to form the Schottky collector contact and ohmic contacts on the emitter and p + -poly base region. The final structure appears as shown in Fig. 4.1(b). 4.4 SIMULATION RESULTS AND DISCUSSION To explore the performance of the proposed NPM HBT (SiC emitter SiGe base lateral Schottky collector HBT), we used the two-dimensional device simulator ATLAS [27]. We incorporated suitable physical models such as concentration dependent mobility, field dependent mobility, bandgap narrowing, Shockley-Read-Hall, Auger recombination models and Klassens mobility model in the simulator to evaluate the performance of the proposed device. For the carrier statistics purpose, we used the Fermi-Dirac distribution. To account for the deep donor (N D ) and deep acceptor (N A ) levels in SiC emitter, we used the incomplete ionisation model. Standard thermionic emission model is incorporated including image force barrier lowering phenomenon [27] for the Schottky collector junction. Electrical properties of SiC are taken from the reported works in the literature [40]. The performance of the proposed NPM HBT compared with NPN HBT and NPM BJT is presented below in detail. 32

39 4.4 (A) DC Performance: Fig. 4.3 shows the simulated common-emitter output characteristics of the proposed NPM HBT (SiC emitter SiGe base lateral Schottky collector HBT) and its equivalent devices (NPN HBT and NPM BJT). As can be observed from the figure, the proposed NPM HBT shows high collector current for a given base current as compared to those of NPN HBT and NPM BJT which will result in a large transconductance. The proposed NPM HBT however shows a collector offset voltage which is more than that of the NPN HBT and NPM BJT structures. Collector offset voltage is commonly seen in the HBTs due to the bandgap offset [41] and in Schottky collector transistors due to the Schottky junction [42]. Since the proposed structure includes both the hetero junction on the emitter side and the Schottky junction on the collector side, its collector offset voltage is expected to be larger than that of NPN HBT and NPM BJT and this should be taken into account in the digital logic circuit design. The Gummel plot of the proposed NPM HBT, NPN HBT and NPM BJT for a fixed collector emitter voltage (V CE = 1 V) is plotted in Fig We can see from the figure that the NPM BJT shows high currents as compared to the proposed NPM HBT and NPN HBT because of low cut-in voltage which can be best observed from the band diagrams drawn at thermal equilibrium as shown in Fig An interesting point is that the base current of the proposed NPM HBT is less than that of the NPN HBT even at high level injection of carriers which clearly shows the suppression of the Kirk effect [43] in the proposed NPM HBT. 33

40 Collector current, I C [µa] N + PM HBT N + PN HBT N + PM BJT I B = 0 to 20 5 na Collector voltage, V C [V] Fig. 4.3 Common-emitter IV characteristics of the proposed NPM HBT compared with NPN HBT, NPM BJT. 34

41 Collector & base current, I C, I B [A] N + PM HBT N + PN HBT N + PM V BJT CE = 1 V Base - emitter voltage, V BE [V] Fig. 4.4 Gummel plot of the proposed NPM HBT compared with NPN HBT, NPM BJT for a fixed collector emitter voltage (V CE = 1 V). 35

42 2000 Current gain, β N + PM HBT N + PN HBT N + PM BJT V CE = 1 V Collector current, IC [A] Fig. 4.5 Gain versus collector current characteristics of the proposed NPM HBT compared with those of NPN HBT, NPM BJT for a fixed collector emitter voltage (V CE = 1 V). 36

43 qv n E g = 1.0 ev E C qφ BP E g = 3.2 ev qv p (a) E V E C qv n E g = 1.0 ev E g = 1.1 ev E g = 3.2 ev qv p (b) E V E C qv n E g = 1.1 ev (c) E g = 1.1 ev qv p E V qφ BP Fig. 4.6 Band diagrams drawn at thermal equilibrium (a) Proposed NPM HBT, (b) NPN HBT and (c) NPM BJT. 37

44 Fig. 4.5 shows the gain versus collector current of the NPM HBT which is compared with that of NPN HBT and NPM BJT. As it is clear from the figure, the gain of the proposed NPM HBT and NPN HBT is very high compared to that of NPM BJT due to the high emitter injection efficiency because of differing barrier heights for electrons and holes as shown in Fig Further, the gain of the proposed NPM HBT is more than that of NPN HBT because of the proficient collection of minority carriers by the metal collector injected into the base. The NPM HBT can also operate at higher collector currents than the NPN HBT because of the metal collector. We have also investigated the effect of base doping on peak gain and breakdown voltage BV CEO (for zero base current) for various germanium concentrations in the base (SiGe) for the proposed NPM HBT. Fig. 4.7 shows the peak gain versus base doping for various germanium concentrations in the base (SiGe) of the proposed NPM HBT. It can be observed from this figure that the peak gain decreases as we decrease the germanium concentration in the base (SiGe) for a given base doping and the gain also decreases as we increase the base doping for a given Ge concentration because of low emitter injection efficiency. Fig. 4.8 shows the breakdown voltage BV CEO (for zero base current) versus base doping for various germanium concentrations in the base (SiGe) of the proposed NPM HBT. We observe from this figure that for a given base doping, the breakdown voltage BV CEO (for zero base current) increases as we decrease the germanium concentration and for a given Ge concentration, the breakdown voltage increases as we increase the base doping which can be easily understood from the current gain variation shown in Fig

45 00 P + NM HBT(0% Ge) P + NM HBT(% Ge) P + NM HBT(20% Ge) Gain, β 0 5E17 5E18 5E19 Base doping, N D [cm -3 ] Fig. 4.7 Gain versus base doping for various germanium concentrations in the base (SiGe) of the proposed NPM HBT. 39

46 Breakdown voltage, [V] P + NM HBT(0% Ge) P + NM HBT(% Ge) P + NM HBT(20% Ge) Base doping, N D [ 17 cm -3 ] Fig. 4.8 Breakdown voltage BVCEO (for zero base current) Versus base doping for various germanium concentrations in the base (SiGe) of the proposed NPM HBT. 40

47 4.4 (B) Dynamic Behaviour Analysis: 6 Cutoff frequency, f T [GHz] N + PM HBT N + PN HBT N + PM BJT V CE = 1 V Collector current, I C [A] Fig. 4.9 Unity gain cut-off frequency versus collector current of the proposed NPM HBT and its counterparts (NPN HBT and NPM BJT). Fig. 4.9 shows the unity gain cut-off frequency versus collector current of the proposed NPM HBT (SiC emitter SiGe base lateral Schottky collector HBT) and is compared with NPN HBT, NPM BJT. For the cut-off frequency calculation, we have used the model given in ATLAS [27]. As can be observed, the cut-off frequency of the proposed NPM HBT is higher than those of NPN HBT and NPM BJT due to its metal collector and higher transconductance g m. The proposed NPM HBT exhibits an f T of 5.2 GHz at a collector current of 0.2 ma, whereas for the comparable NPN HBT and NPM BJT, f T falls to a negligible value at the above current due to Kirk effect and decrease in transconductance. 41

48 Fig. 4. shows the transient behaviour of the proposed NPM HBT which is compared with NPN HBT and NPM BJT structures. It is clear that the proposed NPM HBT and NPM BJT show excellent transient response with nearly zero base charge storage time due to its metal collector and suppressed Kirk effect while NPN HBT shows a higher storage time due to the Kirk effect and also the electron pile-up at the collector-base hetero-junction. 50 Base current, I B [µa] N + PM HBT N + PN HBT N + PM BJT Transient time, T[ns] Fig. 4. Transient behaviour of the proposed NPM HBT which is compared with NPN HBT and NPM BJT. 42

49 4.4 (C) Performance at High Temperature: Fig shows the gain versus collector current for various temperatures of the proposed NPM HBT which is compared with NPN HBT. As the temperature increases gain decreases which is in excellent agreement with the results reported experimentally for vertical SiC emitter HBT [40]. Further, it can be observed in spite of the Schottky collector, the NPM HBT exhibits a higher current gain (917) as compared to the NPN HBT (860) which is a clear indication of its ability to operate at high temperatures. Current gain, β N + PM HBT N + PN HBT V CE = 1 V Step = 25 K 400 K 300 K Collector current, I C [A] Fig Gain versus collector current for various temperatures of proposed NPM HBT and NPN HBT. 43

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