Proposal and Design of SALTran: A New Surface Accumulation Layer Transistor for Enhanced Current Gain

Transcription

1 Proposal and Design of SALTran: A New Surface Accumulation Layer Transistor for Enhanced Current Gain A dissertation submitted in partial fulfillment of the requirement for the degree of Master of Science (Research) By Vinod Parihar Under the Supervision of Dr. M. Jagadesh Kumar to the Indian Institute of Technology, Delhi April, 2004

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3 CERTIFICATE This is to certify that the thesis entitled Proposal and Design of SALTran: A New Surface Accumulation Layer Transistor for Enhanced Current Gain being submitted by Vinod Parihar with entry no EEM 002, to the Indian Institute of Technology Delhi, for the award of the degree of Master of Science (Research) in Electrical Engineering Department, is a bona fide work carried out by him under my supervision and guidance. The research reports and the results presented in this thesis have not been submitted in parts or in full to any other University or Institute for the award of any other degree or diploma. Date: April, 2004 Dr. M. Jagadesh Kumar Associate Professor Department of Electrical Engineering Indian Institute of Technology New Delhi iii

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5 ACKNOWLEDGEMENTS I wish to express my sincere gratitude to my supervisor Dr. M. Jagadesh Kumar for his invaluable guidance and advice during every stage of this endeavour. I am greatly indebted to him for his continuing encouragement and support without which, it would not have been possible for me to complete this undertaking successfully. His insightful comments and suggestions have continually helped me to improve my understanding. I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory facilities at all points of time. I would also like to express my heartfelt gratitude to Mr. K.C. Sharma for his help. I would like to thank Sukhendu,Venkateshwara Reddy, C. Linga Reddy and Anurag for their help throughout the course. My special thanks to my friends, Atul, Pankaj, Ashish, Alok and Ritesh for making my stay a very memorable one. My sincere thanks and acknowledgements are due to all of my family members who have constantly encouraged me for completing this project. Vinod Parihar v

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7 ABSTRACT Whether for driving highly capacitive loads using BiCMOS technology or in high voltage applications and in many mixed signal and precision analog applications, bipolar transistors are inevitable. To combine the high-density integration of MOS logic with the current-driving capabilities of BJT along with better device isolation of Silicon-on-Insulator (SOI), BiCMOS technology has opened up new avenues for the lateral bipolar transistors (LBT) on SOI. To meet the strict demand on device performance parameters such as β, g m and f T, many structures like HBTs and polysilicon BJTs are already in use. But these require complex process steps and also suffer from collector emitter offset voltage in the case of HBTs and high emitter resistance in the case of polysilicon emitter transistors. Surface Accumulation Layer Transistor (SALTran) is proposed for the first time to offer an alternative way of meeting the stringent performance parameters requirements, by just changing the emitter contact and emitter doping in conventional bipolar transistors. Using process and device simulations, we have demonstrated the SALTran concept both on NPN and PNP LBT on SOI structures to obtain high performance in terms of high current gain, better thermal stability, and less hot carrier degradation without significantly affecting the cut-off frequency. We have also implemented the SALTran concept on power SiC BJT and showed through our simulations the superiority of the power SALTran. Our simulations show that the SALTran concept is useful to both lateral and vertical bipolar transistors whether they are high speed or high voltage structures. In conclusion, we have demonstrated the superior attributes offered by the SALTran structure, supported by extensive simulation studies. The proposed structures should be very useful for VLSI and power applications. The results presented in this work are expected to provide incentive for further experimental applications. vii

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9 TABLE OF CONTENTS CERTIFICATE....iii ACKNOWLEDGEMENTS.. v ABSTRACT. vii TABLE OF CONTENTS....ix CHAPTER 1 1 Introduction The context Preceding efforts Objective of the project Organization of thesis. 3 CHAPTER 2 5 Surface Accumulation Layer transistor(saltran): A New Bipolar Transistor for Enhanced Current Gain Introduction The SALTran concept Design methodology of SALTran Profile design using the process simulator ATHENA Simulation results and discussion Device characteristics Emitter region optimization Hot carrier degradation Temperature effects on current gain Effect of interface traps on current gain Conclusions..28 CHAPTER Realizing high current gain PNP transistors on SOI for complementary bipolar technology Introduction The SALTran concept on PNP transistor Design methodology of PNP SALTran Profile design using the process simulator ATHENA Simulation results and discussions Device characteristics Emitter region optimization Hot carrier injection problem Temperature study on current gain Effect of interface traps on current gain.46 ix

10 3.6. Conclusions...47 CHAPTER 4.49 Implementation of SALTran concept on power SiC BJT Introduction Device structure and parameters Design methodology Simulation results Conclusions...60 CHAPTER Conclusions..63 APPENDICES.67 REFERENCES 89 List of Publications..93 x

11 CHAPTER 1 Introduction 1.1 The Context Bipolar transistors find their use in many high speed mixed signal applications. The problem with the conventional vertical BJTs is that they require complicated fabrication process in the case of BiCMOS integration and the cost of manufacturing is high. This process may be further complicated when CMOS on SOI substrate is integrated. Thus to avoid the complexity, lateral bipolar transistors have been implemented on SOI technology which makes SOI BiCMOS integration possible with a few additional masks and ion implants resulting in only a few minor changes in the standard CMOS process[1-4]. SOI BiCMOS technology offers many advantages as compared to its bulk counterpart such as reduced analog to digital cross talk, less sensitivity to alpha particles, reduction of substrate capacitance and better device isolation. However, bipolar transistors on SOI do suffer from significant base widening at higher collector current, large base charge storage time, lower cut-off frequency and lower current gain. In the case of PNP BJTs, the situation is much worse due to low hole mobility, whereas often we require identical performance as that of NPN BJT in many applications. On the other hand, SiC based power BJT and related devices like IGBT and GTOs are very attractive for high voltage applications because of high breakdown field and high band gap of SiC [5,6]. But SiC BJTs also suffer from low current gain due to small minority carrier lifetime of SiC. 1

12 1.2 Preceding efforts In order to improve the performance of lateral Bipolar transistor on SOI several techniques have been used. Both heterojunction bipolar transistors(hbts) and polysilicon emitter transistors have been used for realizing high current gains. However, this leads to V ce off-set voltage and complex process control in the case of HBTs and high emitter resistance and high 1/f noise current due to interfacial oxide in the case of polyemitter transistor [7-9]. Another method used to improve the current gain of bipolar transistors is the application of high-low emitter junction in which a lightly doped n-region is introduced between the n+region and the p-base region [10]. However, it has been observed experimentally that in such structures, although there is an improvement in current gain, the cut-off frequency of the transistor decreases [10]. Also the fabrication process of the high-low emitter structure is complex and is not suitable for VLSI transistors. It would be very beneficial if the current gain of a BJT can be enhanced using a simple emitter contact concept while averting the above difficulties. The aim of this work is therefore to present for the first time a new technique of increasing the current gain of a bipolar transistor using a structure called the Surface Accumulation Layer Transistor(or SALTran). We have applied this concept to both NPN and PNP transistors in this work. This concept is particularly important in the case of PNP transistors due to the difficulty in realizing high current gains due to poor hole mobility. Even the use of SiGe base [11] and polysilicon emitter [12] could not be of much help in realizing large gain PNP transistors. However, the presence of PNP BJTs in the output stage is crucial for improved driver performance. Also, active loads in many analog applications cannot be implemented without PNP transistors. We demonstrate in this thesis that a significant current 2

13 gain enhancement in PNP transistors can be obtained using proposed Surface Accumulation Layer Transistor(SALTran) concept. We have also examined the possibility of applying the SALTran concept to SiC Bipolar transistors [13] since they too suffer from poor current gain problems due to excessive base recombination. We have presented detailed simulation results and followed by discussions on the physical mechanisms responsible for the improved performance of SALTran. 1.3 Objective of the project The main objective of this work is to propose novel high gain transistor structures namely, (1) A New Surface Accumulation Layer Transistor(SALTran) concept for current gain enhancement in bipolar transistor, (2) A Novel High Current Gain Lateral PNP Transistor on SOI for Complimentary Bipolar Technology, (3) Implementation of the SALTran concept on SiC power bipolar transistor to increase its current gain. We have used two dimensional process and device simulations to study the characteristics of the above devices. Based on the simulated results, we have analyzed the reasons for the improved performance of the proposed structures over the conventional devices. The results presented in this work are expected to provide incentive for further experimental exploration by other researchers. 1.4 Organization of the thesis Chapter one: Introduction Brief overview of issues related to lateral BJTs on SOI and SiC power BJT. Objectives of the report and outline of the thesis. Chapter Two: Surface Accumulation Layer Transistor (SALTran): A New Bipolar Transistor for Enhanced Current Gain. This chapter introduces a new concept (SALTran) for increasing the current gain of the bipolar transistor without degrading the cut-off frequency. Also, its performance is 3

14 compared with standard LBT structure in terms of thermal stability and hot carrier degradation. Chapter Three: Realizing high current gain PNP transistors on SOI for complimentary Bipolar Technology. This chapter demonstrates the application of the SALTran concept on lateral PNP transistor on SOI to increase its gain significantly so that its performance can become comparable to that of an NPN bipolar transistor. Chapter Four: Implementation of SALTran concept on SiC power BJTs. This chapter implements the SALTran concept on SiC power BJT, to enhance its gain and also simultaneously obviating the need for high emitter doping which is difficult for SiC BJT. Chapter Five: Conclusions. 4

15 CHAPTER 2 Surface Accumulation Layer Transistor (SALTran): A New Bipolar Transistor for Enhanced Current Gain 2.1 Introduction In many analog applications, such as accurate current mirrors, variable gain amplifiers bandgap voltage references and other high speed mixed signal circuits, lateral bipolar transistors on SOI have been found to be of great interest with the advent of BiCMOS technologies [7,14]. The advantages of BJTs over MOSFETs and the inherent isolation possible with the SOI devices led to the emergence of SOI based BiCMOS technologies where both lateral BJTs and MOSFETs are fabricated on the same chip. One of the crucial design parameters in a bipolar transistor is the current gain. A large current gain can be traded off against increased base doping to alleviate the problems associated with elevated base sheet resistance commonly observed in high performance BJTs [15]. Current gain of a BJT can be increased using several techniques such as using a polysilicon emitter [9], [16-22] or a SiGe base [8], [23-32]. While both the techniques are widely used, they require complex process steps. Further, in a polysilicon emitter BJT, the emitter as well as the base are heavily doped which may lead to excessive emitter-base junction capacitance and emitter tunneling current. Also, the high emitter resistance due to the interfacial oxide may result in high 1/f noise. Likewise, in the case of HBTs, a finite collector offset voltage V CE(sat) [31] may result due to the dissimilarity in the emitter-base and base-collector junctions. Another technique which has been reported to increase the current gain of a bipolar transistor is the application of low-high emitter junction [10], [32-34]. Nonetheless, in these structures, the cut-off frequency deteriorates due to the increase of 5

16 minority carrier transit time caused by the presence of the high-low junction [34] and the need to create an additional junction within the emitter region makes it unfit for VLSI applications which use submicron transparent emitters. It would be of great practical importance, if the current gain of a BJT can be enhanced using a simple emitter contact concept while obviating the above difficulties. The aim of this chapter is, therefore, to present for the first time a new technique of increasing the current gain of a bipolar transistor using a structure called the Surface Accumulation Layer Transistor(or SALTran). The process steps in SALTran are similar to that of a conventional bipolar transistor except that in SALTran a lightly doped emitter with a metal contact whose workfunction is less than that of silicon is employed. This results in a Schottky-Ohmic emitter contact forming a reflecting boundary for the holes injected into the emitter from the base region leading to a significant reduction in the base current. We demonstrate using two-dimensional process and device simulation that the proposed SALTran is superior in performance compared to an equivalent lateral npn BJT on SOI in terms of high current gain and cut-off frequency. We further ascertain that unlike in the case of high-low emitter bipolar transistors, the cut-off frequency of SALTran does not degrade by the presence of the reflecting boundary in the emitter if pertinent emitter doping and length are used. The dependence of current gain on temperature and the surface states at the metalsemiconductor contact are analyzed and the reasons for the improved performance are explained in detail. 2.2 The Surface Accumulation Layer Transistor (SALTran) Concept The SALTran is based on a concept that when a metal of low work function is brought in contact with a lightly doped n-type semiconductor having a workfunction higher 6

17 φm φs E 0 E C E F E V (a) E C E F E V (b) n(x) x (c) E(x) x (d) Fig. 2.1 (a) Energy band diagram of metal and semiconductor before contact, (b) Energy band diagram after contact, (c) Electron accumulation near emitter contact and (d) Electric field due to accumulation. 7

18 than that of the metal, an accumulation of electrons will come about in the semiconductor near the metal-semiconductor interface [35] as shown in Fig This results in an electric field due to the electron concentration gradient from the metal-semiconductor interface towards the emitter-base junction. The direction of this field is such that it causes the reflection of minority holes injected from the base into the emitter resulting in a reduced hole concentration gradient in the emitter region. As a consequence, the application of such a Schottky-Ohmic contact to the emitter region should result in a reduced base current leading to a prodigious improvement in the current gain. We will establish in the following sections that the above forecasting is indeed genuine if a low emitter doping and an emitter metal contact of appropriate workfunction (e.g. titanium) are chosen so that it results in a Schottky Ohmic contact at the emitter. Knowing the electron affinity and the band gap of silicon to be χ s =4.05 ev and E G =1.12 ev respectively at room temperature and assuming that the metal work function φ m is greater thanχ s, we can show that the emitter doping concentration N D below which the contact becomes a reflecting boundary for minority carriers can be given as N D =n i exp[(χ s +(E C -E i )-φ m )/k B T]=n i exp[(4.61-φ m )/k B T] (1.1) where E i is the intrinsic Fermi level, n i is the intrinsic carrier concentration, k B is the Boltzmann constant and T is temperature in degrees Kelvin. For example, if aluminum is used for the metal contact, the emitter doping should be approximately 3.56x10 18 /cm 3 for realizing the Schottky-Ohmic contact at the emitter. In the following sections, we shall demonstrate using accurate two dimensional process and device simulations that the application of surface accumulation layer emitter contact does indeed enhance the bipolar transistor performance significantly. 8

19 Base Emitter Collector 1µm 0.3 µm 0.4 µm 1.6 µm 2.4 µm Metal contact Poly contact Metal contact Field oxide 0.2µm n p n - n µm Buried oxide Silicon substrate Fig.2.2 Top layout and schematic cross-section of SALTran and LBT structures 2.3 Design Methodology of SALTran To demonstrate the concept of SALTran on SOI and to calibrate our device simulations, we have first chosen an experimental process for an SOI NPN lateral bipolar transistor (LBT) reported in literature[7]. The top layout and the schematic cross-section of the SALTran or LBT are shown in Fig 2.2. For both the structures, the epitaxial silicon film thickness is chosen to be 0.2 µm, the oxide thickness is 0.38 µm, the p-base width is 0.4 µm 9

20 with a peak doping level of 5x10 17 /cm 3 and the collector drift region width is 1.6 µm with a doping level of 4.5x10 14 /cm 3 and the n + collector doping is 5x10 19 /cm 3. In the case of LBT, the emitter n-region has a doping of 5x10 19 /cm 3 with 0.3 µm length while for the SALTran, we have varied the emitter doping from 4.5x10 14 /cm 3 to /cm 3, keeping the emitter length at 0.3 µm. We have implemented the fabrication steps of [7] in the process simulator ATHENA [36] and imported the structure and doping profiles into the device simulator ATLAS [37]. We have calibrated the default model parameters in ATLAS such that the simulated current gain and the cut-off frequency of the lateral SOI BJT matches with the experimentally reported values in [7]. We have then carried out the process simulation for SALTran with different emitter dopings and emitter lengths keeping all the other process steps and device data same as that of the reported lateral bipolar transistor (LBT) on SOI so that our simulations are well validated. 2.4 Profile Design Using the Process Simulator ATHENA We have used the following process steps in ATHENA to design the doping profiles for both the LBT and the SALTran. First the n + collector implant was done with a phosphorus dose of 5x10 14 cm -2 at 100 kev after patterning of the deposited silicon nitride. Then a 0.8 µm thick CVD-oxide is deposited, patterned and etched. Next, a screen oxide of 0.03 µm thickness was deposited, followed by a 0.24 µm thick CVD-nitride deposition and etching to form a spacer. Following this, the emitter is formed by implanting phosphorus with a dose of 2.5x10 13 cm -2 and an energy of 50 kev while the base region is protected by the spacer. The emitter is then driven in for 1hr at C in nitrogen followed by LOCOS for 1 hr in wet oxygen at C to give a 0.18 µm thick oxide over emitter. After opening the base area by a wet chemical etch and removal of the nitride spacer by phosphoric acid, three subsequent 10

21 Table 2.1: ATLAS input parameters used in the simulation of SALTran/LBT Parameter Silicon film thickness t si Buried oxide thickness t box Metal work function for emitter contact(titanium) Emitter length Base length Collector length Emitter region doping for SALTran Emitter region doping for LBT Value 0.20 µm 0.38 µm 3.9 ev µm 0.40 µm 1.6 µm 4.5x10 14 cm -3 to 1x10 18 cm -3 5x10 19 cm -3 Base region doping Collector region doping N + collector region doping SRH electron minority carrier lifetime coefficient (TAUN0) SRH hole minority carrier lifetime coefficient (TAUP0) SRH concentration parameter for electrons and holes NSRHN and NSRHP Surface recombination velocity at poly base contact (VSURFN) 5x10 17 cm x10 14 cm -3 5 x10 19 cm x10-6 s 1x10-6 s 5x10 16 cm x10 4 cm/s boron implants of 3x10 12 cm -2 at 60 kev, 3x10 12 cm -2 at 20 kev, 5x10 12 cm -2 at 20 kev were performed. Next annealing at C for 20 minutes and C for 60 minutes was done. This is followed by the deposition of a polysilicon layer of 0.3 µm thickness and was doped 11

22 by boron implantation of dose 2.5x10 15 cm -2 with 70 kev energy followed by annealing at C for 80 minutes. The oxide layer was etched followed by silicon etching on the side of the emitter and the metal was deposited and patterned for providing the emitter contact. The final structure looks as shown in Fig 2.2. The process for LBT is same as that of SALTran except that the emitter implant dose and the nitride spacer width are 2.5x10 15 cm -2 and 0.34 µm respectively in the case of LBT. As an example, the final doping profiles of the SALTran and LBT obtained using the above process in ATHENA are shown in Fig. 2.3 for an emitter doping of cm -3. We have adjusted the process parameters to obtain different emitter doping values between 4.5x10 14 and cm -3. This doping data is given as an input to the device simulator ATLAS to evaluate the electrical characteristics of both the structures as discussed in the following section. Fig. 2.4 shows the band diagram near the emitter contact. Doping concentration (/cm 3 ) SALTran LBT Distance from emitter contact (µ m) Fig. 2.3 Doping profile of SALTran and LBT structures. 12

23 SALTran (4.5x10 14 /cm 3 ) LBT Conduction band Energy (ev) Metal fermi level Valence band Silicon Distance from emitter contact (µm) (a) Energy (ev) SALTran (4.5 x /cm 3 ) LBT Hole quassi fermi level V BE = 0.7 V Conduction band Electron quassi fermi level Valence band Metal Silicon Distance from emitter contact (µm) (b) Fig 2.4 Band diagram of SALTran and LBT (a) Without bias and (b) With bias 13

24 2.5 Simulation Results and Discussion Device Characteristics In the device simulator ATLAS, we have used suitable models for the bandgap narrowing, SRH and Auger recombination and the concentration and field dependent mobility. The simulation parameters are given in Table 2.1. The simulated output characteristics of the SALTran and LBT are shown in Fig The emitter doping of SALTran is 4.5x10 14 cm -3 and its length is 0.3 µm. It is clearly seen that SALTran has a higher current driving capability than the LBT for a given base current. The gummel plot shown in Fig. 2.6 for two emitter dopings of SALTran with an emitter length of 0.3 µm indicates that the base current in SALTran is quite smaller than that of LBT resulting in an enhanced current gain as shown in Fig We further notice that with the reduction in emitter doping from cm -3 to 4.5 x cm -3, the base current decreases significantly resulting in a drastic improvement in the current gain. We notice that the ideality factor of base current for SALTran increases slightly when compared to the LBT. While the peak current gain of LBT is only 20, the SALTtran exhibits a peak current gain of 200 and 1500 when the emitter doping is cm -3 and 4.5 x cm -3, respectively. This significant enhancement in current gain can be understood from the electron profile and the electric field profile in the emitter region shown in Fig As pointed out in Section 2.2, since we have chosen the workfunction (3.9 ev) of the emitter metal contact to be less than that of the silicon emitter region, there is an accumulation of electrons under the metal contact as shown by the simulated electron profile in Fig. 2.8(a) for the SALTran structure with two different emitter dopings. No such electron accumulation is observed in the case of LBT even though the same metal is used for the emitter contact. The accumulated electron gradient in SALTran results 14

25 2.0 Collector current (µa) I b =0.1 na to 0.9 na Step 0.2 na (a) Collector emitter voltage (V) Collector current (µa) I b =0.1 na to 0.9 na Step 0.2 na (b) Collector emitter voltage (V) Fig. 2.5 Output characteristics of (a) SALTran, (b) LBT structures 15

26 Collector and base current (A) 10-3 V CE =3 V SALTran(4.5x10 14 /cm 3 ) SALTran(1x10 18 /cm 3 ) LBT I C I B Base emitter voltage (V) Fig. 2.6 Gummel plots of SALTran and LBT structures. SALTran(4.5x10 14 /cm 3 ) V =3 V CE 10 3 SALTran(1x10 18 /cm 3 ) LBT Current gain Collector current (A) Fig. 2.7 Current gain versus collector current of SALTran and LBT structures. 16

27 Electron concentration (/cm 3 ) SALTran (4.5x10 14 /cm 3 ) SALTran (1x10 18 /cm 3 ) LBT Distance from emitter contact (µm) 800 (a) Electric field (kv/cm) SALTran (4.5x10 14 /cm 3 ) SALTran (1x10 18 /cm 3 ) LBT (b) Distance from emitter contact (µm) Fig. 2.8 (a) Electron concentration and (b) Electric field of SALTran and LBT structures in the emitter. 17

28 Carrier Concentration (/cm 3 ) SALTran(4.5x10 14 /cm 3 ) LBT Emitter base junction V BE =0 Metal Distance from emitter contact (µm) Carrier concentration (/cm 3 ) SALTran (4.5x10 14 /cm 3 ) LBT V BE =0.7 V Emitter base junction Metal Distance from emitter contact (µm) Fig.2.9 Minority carrier profile in emitter and base region (a) Without bias and (b) With bias 18

29 in a large electric field under the emitter as shown in Fig. 2.8(b) and acts as a reflecting boundary for the holes arriving from the emitter-base junction. The base current of SALTran will, therefore, be significantly smaller than that of the LBT as demonstrated in the gummel plots of Fig The minority carrier profile in the emitter and base region for both SALTran and LBT structures is shown in Fig. 2.9 The simulated cut-off frequency f T of SALTran and LBT are compared in Fig We notice that when the emitter doping of SALTran is cm -3, the f T of SALTran is greater than that of the LBT. This is unlike the behaviour shown by the high-low junction emitter bipolar transistors in which the presence of the high-low junction deteriorates the cutoff frequency due to an increase in the emitter transit time because of charge storage effects[34]. If the emitter doping is reduced to a low value (4.5x10 14 cm -3 ), a slight reduction in f T is observed in the case of SALTran because of increase in the emitter resistanc also indicating that one has to optimize both the emitter length and the emitter doping of SALTran to get the desired current gain enhancement without seriously affecting the cut-off frequency as discussed below Emitter Region Optimization An important aspect of the SALTran structure is that as the emitter length decreases both the current gain and cutoff frequency begin to increase. A reduction in the emitter length causes the rate of reflection of the holes from the emitter to be significant. Fig shows the peak current gain variation for different emitter lengths and emitter dopings for both SALTran and LBT structures. We notice that when the emitter doping is far smaller than the peak base doping, the current gain enhancement is maximum. For example, when the emitter doping is 4.5x10 14 cm -3, the current gain enhancement is largest for shallow emitter lengths 19

30 Cutoff frequency (GHz) V CE =3 V SALTran (4.5X10 14 /cm 3 ) SALTran (1X10 18 /cm 3 ) LBT Collector current (A) Fig Cutoff frequency versus collector current for SALTran and LBT structures which makes the SALTran structure very attractive for scaled down VLSI BJTs. We also notice that for deeper emitter lengths too the current gain enhancement is still impressive when the emitter is lightly doped. This is an indication that the SALTran concept can be conveniently applied to even high voltage power bipolar transistors in which low current gain is often a problem. In the case of deeper emitter junctions, the current gain of SALTran is smaller than that of shallower emitter due to the increased emitter region recombination for deeper emitters. The peak cutoff frequency variation with emitter length and emitter doping is shown in Fig It is seen that when the emitter doping is cm -3, at an emitter length of 0.5 µm, the SALTran has almost the same peak cutoff frequency as that of LBT and at 0.3 µm emitter length, it surpasses the LBT in terms of both the current gain and the cutoff frequency. With proper optimization of emitter length and emitter doping we can get both high current gain and high cutoff frequency. 20

31 Peak current gain x10 14 /cm 3 1x10 17 /cm 3 1x10 15 /cm 3 1x10 18 /cm 3 1x10 16 /cm 3 5x10 19 /cm Emitter length (µm) Fig Current gain versus emitter length of SALTran for different emitter dopings (4.5x10 14 /cm 3 to 1x10 18 /cm 3 ) and LBT structure for an emitter doping of 5x10 19 /cm 3. Cut off frequency (GHz) 3 4.5x10 14 /cm 3 1x10 17 /cm 3 1x10 15 /cm 3 1x10 18 /cm 3 1x10 16 /cm 3 5x10 19 /cm Emitter length (µm) Fig Cutoff frequency versus emitter length of SALTran for different emitter dopings (4.5x10 14 /cm 3 to 1x10 18 /cm 3 ) and LBT structure for an emitter doping of 5x10 19 /cm 3. 21

32 2.6 Hot Carrier Injection Problem A major reliability concern for bipolar transistors is the current gain degradation due to an increase in base current caused by the hot carrier injection when a reverse bias appears across the emitter-base junction [38,39]. In bipolar transistors, the heavy doping in the emitter and base regions results in sufficiently large electric field even at typical emitter-base reverse-bias voltages (<5 V) and is the primary cause of the hot carrier injection problem. In order to investigate this, we have compared the simulated reverse emitter-base characteristics of SALTran and LBT in Fig (a). It can be seen that because of low emitter doping (4.5x10 14 cm -3 ) used in SALTran, its reverse breakdown voltage is significantly larger than that of LBT which breaks down approximately at a reverse bias of 5.5V. The electric field in the emitter region shown in Fig. 2.13(b) at the breakdown of LBT (5.5 V) clearly shows that in the case of LBT with its heavily doped emitter, there is a larger peak electric field at the emitter-base junction compared to that of SALTran whose emitter is completely depleted because of low doping. It may be pointed out that although the electric field at the metal-semiconductor interface of the SALTran is not negligible, carrier multiplication is very unlikely to take place here due to the extremely narrow thickness of the high electric field region [40]. This clearly indicates the less vulnerability of SALTran to the hot carrier injection phenomenon if the emitter is lightly doped. In the case of SALTran, therefore, the lightly doped emitter not only helps in realizing a large gain but it may also result in a reduced hot carrier injection. 22

33 10-5 SALTran (4.5x10 14 /cm 3 ) Reverse current (A) LBT Reverse emitter base voltage (V) (a) Electric field (kv/cm) V EB =5.5 V SALTran (4.5x10 14 /cm 3 ) LBT (b) Distance from emitter contact (µm) Fig (a) Reverse break down characteristics of the emitter-base junction of SALTran and LBT structures and (b) Electric field in the emitter region of SALTran and LBT structures at a reverse bias of 5.5 V 23

34 2.7 Temperature Effects on Current Gain The current gain of a silicon bipolar transistor increases with ambient temperature and this can cause problems in many applications. To understand the temperature effects, we have compared the current gain dependence of SALTran with that of LBT in Fig (a) by plotting the normalized current gain as a function of temperature. We notice that the dependence of current gain on temperature is far less in the case of SALTran as compared to the LBT. It is well known[34] that the variation in peak current gain and the temperature can be related by β=β o exp(- E g / k B T) where β o is the maximum current gain for activation energy E g =0, k B is the Boltzmann constant and T is the absolute temperature in degrees Kelvin. If E ge and E gb are the effective bandgap narrowing in the emitter and base regions, respectively, the activation energy E g can be obtained as E g = E ge - E gb. From the peak current gain variation of SALTran and LBT as a function of temperature, one can obtain the activation energy by plotting ln β versus 1/ (k B T) as shown in Fig (b). The activation energy for SALTran comes out to be 30 mev and 34 mev for the emitter doping of 4.5x10 14 cm -3 and cm -3, respectively. The activation energy of LBT is found to be 53 mev. This clearly shows that SALTran can be operated at higher temperatures compared to LBT while keeping the current gain variations much smaller than that of LBT. 24

35 2.8 SALTran (4.5x10 14 /cm 3 )β 300 =1500 SALTran (1x10 18 /cm 3 )β 300 =198 LBTβ 300 = β(t)/β (a) Temperature (K) 10 4 E g =30 mev Peak current gain E g =34 mev E g =53 mev SALTran (4.5x10 14 /cm 3 ) SALTran (1x10 18 /cm 3 ) LBT (b) 1/K B T (ev -1 ) Fig (a) Normalized peak current gain [β(t)/ β 300 ] versus temperature, (b) Peak current gain versus 1/k B T of SALTran and LBT structures. 25

36 2.8 Effect of Interface Traps on Current Gain Since a Schottky-Ohmic contact is employed at the emitter of SALTran, it is obvious that there could be interface traps at the metal-semiconductor interface depending on the surface preparation and metal deposition method employed. Both acceptor and donor type interface traps are known to be present which will affect the band bending [41]. Since band bending is crucial to create an accumulation of electrons in SALTran, it is of practical interest to examine the extent to which the presence of interface states will affect the current gain. While it is difficult to predict the number and type of traps in the band gap which can vary from process to process, we can at least introduce in the simulator the typical range of interface traps to study their influence on the device characteristics. The effect of interface traps, for example, have been carried out earlier using simulation in the case of Schottky junctions on silicon [42]. In the device simulator ATLAS, we have introduced both donor and acceptor type interface traps to see their effect on the current gain of SALTran. For acceptor(or donor) type traps, we have set the trap energy level(e.level) at 0.49 ev from the conduction(or valance) band. The degeneracy factor(degen) for the trap level is chosen to be 12 and the capture cross-sections for electrons(sign) and holes(sigp) are taken to be 2.84x10-15 cm 2 and 2.84x10-14 cm 2, respectively. at the interface. We observe that the current gain decreases as the interface trap concentration increases and that the effect is more pronounced if both acceptor and donor type traps are present. We have observed an increase in the simulated base current when the trap concentration is increased and this, therefore, will cause the current gain to decrease. 26

37 1600 Peak current gain E.level=0.49 ev degen=12 sign=2.84e-15 cm 2 sigp=2.84e-14 cm 2 Donor or acceptor states only Both donor and acceptor states Trap density (/cm 2 ) Fig Peak current gain versus trap density for SALTran and LBT structures. Fig shows the peak current gain of SALTran with an emitter doping of 4.5x10 14 /cm 3 and emitter length of 0.3 µm as a function of both acceptor and donor type traps However, even in the presence of a significant number of interface traps, the current gain enhancement realized in SALTran over that of LBT is approximately 40 times larger which is very impressive. Therefore, if the surface preparation is well controlled as is the practice in most advanced fabrication procedures, it should be possible to preserve the current gain enhancement of the proposed SALTran structure. On the other hand, growing a native oxide of approximately Å on the emitter surface using RCA cleaning, just as is commonly done in the case of polysilicon emitter bipolar transistors [22] will minimize the effect of surface traps and may further enhance the current gain. Therefore, the interface states should not be a cause for concern. 27

38 2.9 Conclusions For the first time, the concept of surface electron accumulation to increase the current gain and also the cutoff frequency of bipolar transistors is successfully shown by using 2-D process and device simulation. We have demonstrated that the presence of a Schottky-Ohmic contact at the emitter results in a reflecting boundary for the minority carriers resulting in a significant improvement in the current gain of the bipolar transistors. We have also showed the less vulnerability of SALTran to hot carrier injection compared to LBT. Our simulations show that activation energy of SALTran is significantly lower than that of LBT making its current gain less dependent on temperature variations. Unlike in the case of the high-low emitter bipolar transistors, the cut-off frequency of the SALTran does not deteriorate in the presence of surface electron accumulation if optimized emitter design is used. Since the SALTran structure obviates the need to create a high-low junction in the emitter region and since its performance improves for both shallow and deep emitters, the proposed SALTran concept should be useful to the designers to enhance the bipolar transistor performance in VLSI as well as high voltage switching circuit applications. 28

39 CHAPTER 3 Realizing high current gain PNP transistors on SOI for Complimentary Bipolar Technology 3.1 Introduction Complementary bipolar technologies using NPN and PNP transistors play an important role in many analog applications such as feedback amplifiers, current mirrors and push-pull circuits [43]. The presence of PNP BJTs in the output stage is crucial for improved driver performance. Also, active loads in analog applications can not be implemented without PNP transistors. However, realizing compatible PNP and NPN transistors is difficult because PNP transistors exhibit low current gains due to poor hole mobility. Even the use of SiGe base [11] and polysilicon emitter [12] could not be of much help in realizing large gain PNP transistors. While both the above techniques are widely used, they require complex process steps. Further, in a polysilicon emitter BJT, the high emitter resistance due to the interfacial oxide may result in high 1/f noise. Likewise, in the case of HBTs, a finite collector offset voltage V CE(sat) [31] may result due to the dissimilarity in the emitter-base and base-collector junctions. Another technique which has been reported to increase the current gain of a bipolar transistor is the application of low-high emitter junction [10, 32-34]. Nonetheless, in this case, the cut-off frequency deteriorates due to the increase of minority carrier transit time caused by the presence of the high-low junction [34] and the need to create an additional junction within the emitter region makes it unfit for VLSI applications which use submicron transparent emitters. It would be of great practical importance, if we can get high current gain in PNP BJT using a simple emitter contact concept with out above difficulties. 29

40 The main objective of this chapter is to therefore successfully implement the high current gain PNP bipolar transistor using Surface Accumulation Layer Transistor(or SALTran) concept. The process steps in SALTran are similar to that of a conventional bipolar transistor except that in case of SALTran a lightly doped emitter with a metal contact whose workfunction is higher than that of the silicon is employed. This results in a Schottky- Ohmic emitter contact forming a reflecting boundary for the electrons injected into the emitter from the base region leading to a significant reduction in the base current. The proposed PNP SALTran is superior in performance compared to an equivalent lateral PNP BJT on SOI [14] in terms of high current gain. We further ascertain that unlike in the case of low-high emitter bipolar transistors, the cut-off frequency of SALTran does not degrade by the presence of the reflecting boundary in the emitter if optimized emitter doping and length are used. 3.2 The Surface Accumulation Layer Transistor(SALTran) Concept on PNP transistor For realizing the SALTran concept on PNP, a metal of high work function is brought in contact with a lightly doped p-type semiconductor such that an accumulation of holes takes place in the semiconductor near the metal-semiconductor interface [35]. This results in an electric field due to the hole concentration gradient from the metal-semiconductor interface towards the emitter-base junction. The direction of this field is such that it causes the reflection of electrons injected from the base into the emitter resulting in a reduced electron concentration gradient in the emitter region. Thus the application of such a Schottky-Ohmic contact to the emitter region results in a reduced base current leading to a significant improvement in the current gain. 30

41 In the following sections, we shall demonstrate using accurate two dimensional process and device simulations that the application of surface accumulation layer emitter contact does indeed enhance the PNP bipolar transistor performance significantly. 3.3 Design Methodology of PNP SALTran To demonstrate the concept of SALTran on SOI and to calibrate our device simulations, we have first chosen the typical experimental process steps for an SOI PNP lateral bipolar transistor (LBT) reported in literature [7]. The top layout and the schematic cross-section of the SALTran or LBT are shown in Fig 3.1. The simulation parameters are given in Table 3.1. We have implemented the fabrication steps of [7] in the process simulator Base Emitter Collector 1µm 0.3 µm 0.4 µ m 3.8 µm 3 µm Field oxide 0.2 µm 0.38 µm P N P P + Buried oxide Silicon substrate Fig. 3.1 Top layout and schematic cross-section of SALTran and LBT structures. 31

42 Table 3.1: ATLAS input parameters used in the simulation of PNP SALTran/LBT Parameter Value Silicon film thickness t si Buried oxide thickness t box Metal work function for emitter contact (Nickel) Emitter length Base length Collector length Emitter region doping level in LBT Emitter region doping in SALTran Base region doping Collector region doping P + collector region doping SRH electron minority carrier life time coefficient (TAUN0) SRH hole minority carrier life time coefficient (TAUP0) SRH concentration parameter for electrons and holes NSRHN and NSRHP Surface recombination velocity at poly base contact (VSURFP) 0.20 µm 0.38 µm 5.4 ev µm 0.40 µm 3.8 µm 5x10 19 /cm 3 1x10 14 cm -3 to 1x10 18 cm -3 5x10 17 cm -3 1x10 17 cm -3 5 x10 19 cm x10-6 s 1x10-6 s 5x10 16 cm -3 Atlas default ATHENA [36] to obtain the PNP lateral SOI structure reported in [14] and imported this structure and doping profiles into the device simulator ATLAS [37], to calibrate the model parameters in ATLAS such that the simulated current gain of the PNP lateral SOI BJT 32

43 matches with the reported value in [14]. We have then carried out process simulation for to obtain PNP SALTran structures of different emitter dopings and emitter lengths, which are then given as an input to the device simulator ATLAS for further investigation regarding cutoff frequency and current gain. variation of SALTran for different emitter doping and emitter lengths. 3.4 Profile Design Using the Process Simulator ATHENA We have used the following process steps in ATHENA to design the doping profiles for both the LBT and the SALTran. For the LBT first the p + collector implant was done with a boron dose of 2x10 15 cm -2 at 40 kev after patterning the deposited silicon nitride on 0.2 µm SOI of doping 1x10 17 cm -3. Then a thick CVD-oxide is deposited, patterned and etched. Next, a screen oxide of 0.03 µm thickness was deposited, followed by a 0.31 µm thick CVD-nitride deposition and etching to form a spacer. Following this, the emitter region is formed by implanting boron with a dose of 3x10 15 cm -2 and an energy of 50 kev at a tilt angle of 30 0 while the base region is protected by the nitride spacer. Then drive-in is done for 60 minutes at C in nitrogen. After opening the base diffusion window by a wet chemical etch and removal of the nitride spacer by phosphoric acid, three subsequent phosphorus implants of 4x10 12 cm -2 at 20 kev, 7x10 12 cm -2 at 40 kev and 6x10 12 cm -2 at 60 kev were performed. Next annealing at C for 20 minutes was done. This is followed by the deposition of a 0.2 µm of n + polysilicon layer of doping 5x10 19 cm -3. Finally, the oxide layer was etched followed by silicon etching on the side of the emitter and the metal was deposited and patterned for providing the emitter contact. The final structure looks as shown in Fig.3.1. The process steps for SALTran are same as that of LBT except that in the case of SALTran, the emitter doping is chosen to form the 33

44 Schottky-Ohmic contact. For the SALTran with emitter doping of 1x10 14 cm -3 the nitride spacer width is 0.08 µm. The p - collector implant was done in two subsequent boron implants of 4x10 12 cm -2 at 50 kev with a tilt angle of 25 0 and 2x10 12 cm -2 at 20 kev with a tilt angle of 50 0 and it was followed by drive in for 20 minutes at C. The base was defined by three subsequent boron implants of 9x10 12 cm -2 at 20 kev, 1x10 13 cm -2 at 40 kev and 6x10 12 cm -2 at 60 kev. The final doping profiles of the SALTran and LBT obtained using the above process in ATHENA are shown in Fig 3.2 for an emitter doping of cm -3. We have adjusted the emitter implantation parameters to obtain different emitter doping values between 1x10 14 cm -3 and 1x10 18 cm -3. This device structure is given as an input to the device simulator ATLAS to evaluate the electrical characteristics of both the structures as discussed in the following section. Fig 3.3 shows the band diagram of both structures in emitter base region. Doping concentration (/cm 3 ) SALTran LBT Distance from emitter contact (µm) Fig. 3.2 Doping profile of SALTran and LBT structures. 34

45 Conduction band PNP SALTran LBT Energy (ev) Metal Fermi level Valence band Silicon Distance from emitter contact (µm) V BE =-0.7 V Conduction band Energy (ev) Metal Electron quassi fermi level Hole quassi fermi level Silicon Valence band PNP SALTran LBT Distance from emitter contact (µm) Fig. 3.3 Band diagram in the Emitter-base region (a) without bias and (b) with bias 35

46 Collector current (µa) IB= 0.5 na to 2.5 na Step 0.5 na Emitter-collector voltage (V) Fig. 3.4 Output characteristics of the SALTran structure 3.5. Simulation Results and Discussion Device Characteristics In our simulations using device simulator ATLAS, we have used suitable models for the bandgap narrowing, SRH and Auger recombination and the concentration and field dependent mobility. The simulated output characteristics of the SALTran are shown in Fig. 3.4 for an emitter doping of 1x10 14 cm -3 and emitter length of 0.3 µm. The gummel plot shown in Fig. 3.5 (a) of SALTran indicates that the base current in SALTran is quite smaller than that of LBT resulting in an enhanced current gain as shown in Fig.3.5 (b). We further notice that with the reduction in emitter doping from cm -3 to cm -3, the base current decreases significantly resulting in a drastic improvement in the current gain. As we changed the emitter length from 3.8 µm to 0.3 µm, the peak current gain of LBT decreased from 14 to 2 due to reduction in the emitter gummel number, while that of SALTran increased from 120 to

47 10-3 Collector and base current (A) V CE =-1.5 V SALTran LBT I C I B (a) Base emitter voltage (V) 10 3 SALTran (3.8µm) SALTran(0.3µm) LBT(3.8µm) LBT(0.3µm) Current gain V CE =-1.5 V (b) Collector current (A) Fig. 3.5 (a) Gummel plots and (b) Current gain versus collector current of SALTran and LBT structures. 37