TAB Drain. Table of Contents

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1 Normally OFF ilicon Carbide Junction Transistor Features 175 C Maximum Operating Temperature Gate Oxide Free ic witch Optional Gate Return Pin Exceptional afe Operating Area Integrated ic chottky Rectifier Excellent Gain Linearity Temperature Independent witching Performance Low Output Capacitance Positive Temperature Coefficient of R D,ON uitable for Connecting an Anti-parallel Diode Advantages Compatible with i MOFET/IGBT Gate Drive ICs > 20 µs hort-circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input ignal Distortion High Amplifier Bandwidth Package TAB Drain GR G 7L D2PAK (TO-263-7L) Applications V D = 1200 V R D(ON) = 100 mω I D (@ 25 C) = 25 A I D (@ 150 C) = 10 A h FE (@ 25 C) = 80 Gate (Pin 1) Drain (TAB) Gate Return (Pin 2) ource (Pin 3, 4, 5, 6, 7) Please note: The ource and Gate Return pins are not exchangeable. Their exchange might lead to malfunction. Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) olar Inverters witched-mode Power upply (MP) Power Factor Correction (PFC) Induction Heating Uninterruptible Power upply (UP) Motor Drives Table of Contents ection I: Absolute Maximum Ratings... 1 ection II: tatic Electrical Characteristics... 2 ection III: Dynamic Electrical Characteristics... 2 ection IV: Figures... 4 ection V: Driving the GA10ICP ection VI: Package Dimensions ection VII: PICE Model Parameters ection I: Absolute Maximum Ratings Parameter ymbol Conditions Value Unit Notes Drain ource Voltage V D V G = 0 V 1200 V Continuous Drain Current I D T C = 25 C 25 A Fig. 17 Continuous Drain Current I D T C = 150 C 10 A Fig. 17 Continuous Gate Current I G 1.3 A Continuous Gate Return Current I GR 1.3 A Turn-Off afe Operating Area RBOA T VJ = 175 o C, I D,max = 10 Clamped Inductive V D V Dmax A Fig. 19 hort Circuit afe Operating Area COA T VJ = 175 o C, I G = 1 A, V D = 800 V, Non Repetitive >20 µs Reverse Gate ource Voltage V G 30 V Reverse Drain ource Voltage V D 25 V Power Dissipation P tot T C = 25 C / 150 C, t p > 100 ms 170 / 22 W Fig. 16 torage Temperature T stg -55 to 175 C Nov 2015 Latest version of this datasheet at: Pg 1 of 11

2 Parameter ymbol Conditions Value Unit Notes Free-Wheeling ic Diode Repetitive peak reverse voltage V RRM 1200 V Continuous forward current I F T C 150 C 10 A RM forward current I F(RM) T C 150 C 17 A urge non-repetitive forward current, T I C P = 10 ms 65 Half ine Wave FM T = 150 C, t C P = 10 ms 55 A Non-repetitive peak forward current I F,max T = 25 C, t C P = 10 µs 280 A I 2 t value i 2 T dt = 25 C, t C P = 10 ms 21 T = 115 C, t C P = 10 ms 15 A 2 s ection II: tatic Electrical Characteristics Parameter ymbol Conditions Value Min. Typical Max. Unit Notes A: On tate Drain ource On Resistance Gate ource aturation Voltage DC Current Gain FWD forward voltage B: Off tate Drain Leakage Current C: Thermal ection III: Dynamic Electrical Characteristics A: Capacitance and Gate Charge R D(ON) V G,AT h FE V F I D I D = 10 A, T j = 25 C I D = 10 A, T j = 150 C I D = 10 A, T j = 175 C I D = 10 A, I D /I G = 40, T j = 25 C I D = 10 A, I D /I G = 30, T j = 175 C V D = 8 V, I D = 10 A, T j = 25 C V D = 8 V, I D = 10 A, T j = 125 C V D = 8 V, I D = 10 A, T j = 175 C I F = 10 A, T j = 25 C I F = 10 A, T j = 175 C V D = 1200 V, V G = 0 V, T j = 25 C V D = 1200 V, V G = 0 V, T j = 150 C V D = 1200 V, V G = 0 V, T j = 175 C Gate Leakage Current I G V G = 20 V, T j = 25 C 20 na mω Fig. 4 V Fig. 7 V μa Fig. 8 Thermal resistance, junction - case R thjc ic Junction Transistor 0.88 C/W Fig. 20 Thermal resistance, junction - case R thjc ic Diode 0.8 C/W Fig. 21 Parameter ymbol Conditions Value Min. Typical Max. Input Capacitance C iss V G = 0 V, V D = 800 V, f = 1 MHz 1400 pf Fig. 9 V D = 1 V, f = 1 MHz 760 Reverse Transfer/Output Capacitance C rss /C oss V D = 400 V, f = 1 MHz 80 pf V D = 800 V, f = 1 MHz 60 Total Output Capacitance Charge Qoss V D = 400 V 56 V D = 800 V 80 nc Output Capacitance tored Energy E O V G = 0 V, V D = 800 V, f = 1 MHz 25 µj Fig. 10 Effective Output Capacitance, time related C oss,tr I D = constant, V G = 0 V, V D = V 100 pf Effective Output Capacitance, energy related C oss,er V G = 0 V, V D = V 75 pf Gate-ource Charge Q G V G = -5 3 V 10 nc Gate-Drain Charge Q GD V G = 0 V, V D = V 55 nc Gate Charge - Total Q G 65 nc Unit Notes Nov 2015 Latest version of this datasheet at: Pg 2 of 11

3 Parameter ymbol Conditions Value Min. Typical Max. Unit Notes B: witching 1 Internal Gate Resistance ON R G(INT-ON) V G > 2.5 V, V D = 0 V, T j = 175 ºC 0.19 Ω Turn On Delay Time t d(on) T j = 25 ºC, V D = 800 V, 10 ns Fall Time, V D t f I D = 10 A, Resistive Load 10 ns Fig. 11, 13 Turn Off Delay Time t d(off) Refer to ection V for additional 22 ns Rise Time, V D t r driving information. 10 ns Fig. 12, 14 Turn On Delay Time t d(on) 10 ns Fall Time, V D t f T j = 175 ºC, V D = 800 V, 10 ns Fig. 11 Turn Off Delay Time t d(off) I D = 10 A, Resistive Load 35 ns Rise Time, V D t r 10 ns Fig. 12 Turn-On Energy Per Pulse E on T j = 25 ºC, V D = 800 V, 140 µj Fig. 11, 13 Turn-Off Energy Per Pulse E off I D = 10 A, Inductive Load 10 µj Fig. 12, 14 Total witching Energy E tot Refer to ection V. 150 µj Turn-On Energy Per Pulse E on 140 µj Fig. 11 T j = 175 ºC, V D = 800 V, Turn-Off Energy Per Pulse E off 100 µj Fig. 12 I D = 10 A, Inductive Load Total witching Energy E tot 150 µj 1 All times are relative to the Drain-ource Voltage V D Nov 2015 Latest version of this datasheet at: Pg 3 of 11

4 ection IV: Figures A: tatic Characteristics Figure 1: Typical Output Characteristics at 25 C Figure 2: Typical Output Characteristics at 150 C Figure 3: Typical Output Characteristics at 175 C Figure 4: DC Current Gain vs. Drain Current Figure 5: On-Resistance vs. Gate Current Figure 6: On-Resistance vs. Temperature Nov 2015 Latest version of this datasheet at: Pg 4 of 11

5 Figure 7: Typical Gate ource aturation Voltage Figure 8: Typical Blocking Characteristics B: Dynamic Characteristics Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Energy tored in Output Capacitance Figure 11: Typical witching Times and Turn On Energy Losses vs. Temperature Figure 12: Typical witching Times and Turn Off Energy Losses vs. Temperature Nov 2015 Latest version of this datasheet at: Pg 5 of 11

6 Figure 13: Typical witching Times and Turn On Energy Losses vs. Drain Current Figure 14: Typical witching Times and Turn Off Energy Losses vs. Drain Current C: Current and Power Derating Figure 15: Typical Hard witched Device Power Loss vs. 2 Figure 16: Power Derating Curve witching Frequency Figure 17: Drain Current Derating vs. Temperature Figure 18: Forward Bias afe Operating Area at T c = 25 o C 2 Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology. Nov 2015 Latest version of this datasheet at: Pg 6 of 11

7 Figure 19: Turn-Off afe Operating Area Figure 20: Transient Thermal Impedance Figure 21: FWD Transient Thermal Impedance Figure 22: Typical FWD Forward Characteristics. Nov 2015 Latest version of this datasheet at: Pg 7 of 11

8 ection V: Driving the GA10ICP Drive Topology Gate Drive Power witching Consumption Frequency Application Emphasis Availability TTL Logic High Low Wide Temperature Range Coming oon Constant Current Medium Medium Wide Temperature Range Coming oon High peed Boost Capacitor Medium High Fast witching Production High peed Boost Inductor Low High Ultra Fast witching Coming oon Proportional Lowest High Wide Drain Current Range Coming oon Pulsed Power Medium N/A Pulse Power Coming oon A: tatic TTL Logic Driving The GA10ICP may be driven with direct (5 V) TTL logic and current amplification. The amplified current level of the supply must meet or exceed the steady state gate current (I G,steady ) required to operate the GA10ICP Minimum I G,steady is dependent on the anticipated drain current I D through the JT and the DC current gain h FE, it may be calculated from the following equation. An accurate value of the h FE may be read from Figure 4. An optional resistor R G may be used in series with the gate pin to trim I G,steady, also an optional capacitor C G may be added in parallel with R G to facilitate faster JT switching if desired, further details on these options are given in the following section. II GG,ssssssssssss II DD h FFFF (TT, II DD ) 1.5 TTL Gate ignal 5 / 0 V TTL i/p 5 V D C G R G G I G,steady GR Figure 23: TTL Gate Drive chematic B: High peed Driving The JT is a current controlled transistor which requires a positive gate current for turn-on and to remain in on-state. An idealized gate current waveform for ultra-fast switching of the JT while maintaining low gate drive losses is shown in Figure 24, it features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current during on-state. Figure 24: An idealized gate current waveform for fast switching of an JT. An JT is rapidly switched from its blocking state to on-state when the necessary gate charge, Q G, for turn-on is supplied by a burst of high gate current, I G,on, until the JT gate-source capacitance, C G, and gate-drain capacitance, C GD, are fully charged. QQ oooo = II GG,oooo tt 1 QQ oooo QQ gggg + QQ gggg Nov 2015 Latest version of this datasheet at: Pg 8 of 11

9 Ideally, I G,on should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady onstate. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, L par in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V G,sat (see Figure 7) level to counter these effects. A high negative peak current, -I G,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. Turn off can be achieved with V G = 0 V, however a negative gate voltage V G may be used in order to speed up the turn-off transition. Gate Return Pin The optional gate return (GR) pin allows for a reduction of source path inductive and resistive coupling in the gate driver connection to the GA10ICP Drain currents through the source pin during transient and steady state operation induce an undesirable source voltage in all power transistors due to unavoidable source pin inductance and resistance. This voltage can negatively affect gate driving performance, however the gate return pin allows for decoupling from these source current path effects which results in faster switching and higher efficiency gate driving. B:1: High peed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4 The GA10ICP may be driven using a High peed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. A 3 kv isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and lowside driving, its datasheet provides additional details about this drive topology. VCC High V GL GA03IDDJT30-FR4 Gate Driver Board +12 V C2 U3 C5 VCC High RTN Gate ignal ignal R1 ignal RTN U1 U2 V GL V GL C6 R2 R3 U5 U6 V GH V GL C9 C10 C8 D1 CG1 CG2 R4 RG1 RG2 Gate I G G GR D +12 V VCC Low C1 U4 V GH C3 C4 ource VCC Low RTN Voltage Isolation Barrier Figure 25: Topology of the GA03IDDJT30-FR4 Two Voltage ource gate driver. The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective gate resistance 3 of R G = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe operation of the GA10ICP The steady state current supplied to the gate pin of the GA10ICP with on-board R G = 3.75 Ω, is shown in Figure 26. The maximum allowable safe value of RG for the user s required drain current can be read from Figure 27. For the GA10ICP12-263, R G must be reduced for I D ~10 A for safe operation with the GA03IDDJT30-FR4. For operation at I D ~10 A, R G may be calculated from the following equation, which contains the DC current gain h FE (Figure 4) and the gatesource saturation voltage V G,sat (Figure 7). RR GG,mmmmmm = 4.7VV VV GGGG,ssssss h FFFF (TT, II DD ) 0.6Ω II DD 1.5 Nov 2015 Latest version of this datasheet at: Pg 9 of 11

10 Figure 26: Typical steady state gate current supplied by the GA03IDDJT30-FR4 board for the GA10ICP with the on board resistance of 3.75 Ω Figure 27: Maximum gate resistance for safe operation of the GA10ICP at different drain currents using the GA03IDDJT30-FR4 board. B:2: High peed, Low Loss Drive with Boost Inductor A High peed, Low-Loss Driver with Boost Inductor is also capable of driving the GA10ICP at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses I G,on and I G,off. During operation, inductor L is charged to a specified I G,on current value then made to discharge I L into the JT gate pin using logic control of 1, 2, 3, and 4, as shown in Figure 28. After turn on, while the device remains on the necessary steady state gate current I G,steady is supplied from source V CC through R G. Please refer to the article A current-source concept for fast and efficient driving of silicon carbide transistors by Dr. Jacek Rąbkowski for additional information on this driving topology. 4 1 V CC 2 L D 3 G R G 4 GR Figure 28: implified Inductive Pulsed Drive Topology 3 R G = (1/RG1 +1/RG2) -1. Driver is pre-installed with RG1 = RG2 = 7.5 Ω 4 Archives of Electrical Engineering. Volume 62, Issue 2, Pages , IN (Print) , DOI: /aee , June 2013 Nov 2015 Latest version of this datasheet at: Pg 10 of 11

11 C: Proportional Gate Current Driving For applications in which the GA10ICP will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current I D feedback to vary the steady state gate current I G,steady supplied to the GA10ICP C:1: Voltage Controlled Proportional Driver The voltage controlled proportional driver relies on a gate drive IC to detect the GA10ICP drain-source voltage V D during on-state to sense I D. The gate drive IC will then increase or decrease I G,steady in response to I D. This allows I G,steady, and thus the gate drive power consumption, to be reduced while I D is relatively low or for I G,steady to increase when is I D higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and GA10ICP are in off-state. A simplified version of this topology is shown in Figure 29, additional information will be available in the future at Gate ignal ense Proportional Gate Current Driver HV Diode G D ignal Output I G,steady GR Figure 29: implified Voltage Controlled Proportional Driver C:2: Current Controlled Proportional Driver The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback I D of the GA10ICP during on-state to supply I G,steady into the device gate. I G,steady will then increase or decrease in response to I D at a fixed forced current gain which is set be the turns ratio of the transformer, h force = I D / I G = N 2 / N 1. GA10ICP is initially turned-on using a gate current pulse supplied into an RC drive circuit to allow I D current to begin flowing. This topology allows I G,steady, and thus the gate drive power consumption, to be reduced while I D is relatively low or for I G,steady to increase when is I D higher. A simplified version of this topology is shown in Figure 30, additional information will be available in the future at N2 D Gate ignal G GR N3 N1 N2 Figure 30: implified Current Controlled Proportional Driver Nov 2015 Latest version of this datasheet at: Pg 11 of 11

12 ection VI: Package Dimensions TO-263-7L PACKAGE OUTLINE REF (10.160) (10.668) (1.397) REF (1.905) (1.143) (1.397) (4.343) (4.597) EATING PLANE (0.000) <D> (0.305) (1.143) (1.397) (10.160) (7.620) (6.502) (1.651) (3.175) (7.722) (14.605) (15.875) GA10ICP XXXXXX (8.915) (9.169) Lot code (0.330) (0.432) (2.286) (2.794) (1.27) (0.60) GATE PLANE (0.254) 0-8 NOTE 1. CONTROLLED DIMENION I INCH. DIMENION IN BRACKET I MILLIMETER. 2. DIMENION DO NOT INCLUDE END FLAH, MOLD FLAH, MATERIAL PROTRUION Revision History Date Revision Comments upersedes 2015/11/23 1 Updated Electrical Characteristics 2015/05/29 0 Initial release Published by GeneiC emiconductor, Inc Trade Center Place uite 155 Dulles, VA GeneiC emiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. GeneiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, GeneiC products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Nov 2015 Latest version of this datasheet at: Pg 12 of 11

13 ection VII: PICE Model Parameters GA10ICP This is a secure document. Please copy this code from the PICE model PDF file on our website ( into LTPICE (version 4) software for simulation of the GA10ICP * MODEL OF GeneiC emiconductor Inc. * $Revision: 2.0 $ * $Date: 20-NOV-2015 $ * * GeneiC emiconductor Inc. * Trade Center Place te. 155 * Dulles, VA * * COPYRIGHT (C) 2015 GeneiC emiconductor Inc. * ALL RIGHT REERVED * * These models are provided "A I, WHERE I, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPREED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIE OF MERCHANTABILITY AND FITNE FOR A * PARTICULAR PURPOE." * Models accurate up to 2 times rated drain current. * * tart of GA10ICP PICE Model.UBCKT GA10ICP12 DRAIN GATE OURCE Q1 DRAIN GATE OURCE GA10ICP12_Q D1 OURCE DRAIN GA10ICP12_D1 D2 OURCE DRAIN GA10ICP12_D2 *.model GA10ICP12_Q NPN + I 9.833E-48 IE 1.073E-26 EG BF 87 BR 0.55 IKF NF 1 NE 2 RB IRB RBM 0.16 RE RC 0.08 CJC 229.9E-12 VJC MJC CJE 1244E-9 VJE MJE XTI 3 XTB TRC1 7E-3 VCEO 1200 ICRATING 10.MODEL GA10ICP12_D1 D + I 4.55E-15 R N 1 + IKF 1000 EG 1.2 XTI -2 + TR TR E-05 CJO 6.40E-10 + VJ M FC TT 1.00E-10 BV 1200 IBV 1.00E-03 + VPK 1200 IAVE 10.MODEL GA10ICP12_D2 D + I 1.54E-22 R 0.19 TR N EG 3.23 IKF 19 + XTI 0 FC 0.5 TT 0 + BV 1200 IBV 1.00E-03 VPK 1200.END * End of GA10ICP PICE Model Nov 2015 Latest version of this datasheet at: Pg 1 of 1