Table of Contents. I D,max = 50 Clamped Inductive Load

Transcription

1 Normally OFF ilicon Carbide Junction Transistor Features 210 C maximum operating temperature ate Oxide Free ic witch Exceptional afe Operating Area Excellent ain Linearity Compatible with 5 V TTL ate rive Temperature Independent witching Performance Low Output Capacitance Positive Temperature Coefficient of R,ON uitable for Connecting an Anti-parallel iode Advantages Compatible with i MOFET/IBT ate rive ICs > 20 µs hort-circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input ignal istortion High Amplifier Bandwidth Package TO-258 Applications V = 600 V R (ON) = 25 mω I (Tc = 25 C) = 100 A h FE (Tc = 25 C) = 105 own Hole Oil rilling eothermal Instrumentation olenoid Actuators eneral Purpose High-Temperature witching Amplifiers olar Inverters witched-mode Power upply (MP) Power Factor Correction (PFC) Table of Contents ection I: Absolute Maximum Ratings...1 ection II: tatic Electrical Characteristics...2 ection III: ynamic Electrical Characteristics...2 ection IV: Figures...3 ection V: riving the A50JT ection VI: Package imensions ection VII: PICE Model Parameters ection I: Absolute Maximum Ratings Parameter ymbol Conditions Value Unit Notes rain ource Voltage V V = 0 V 600 V Continuous rain Current I T J = 210 C, T C = 25 C 100 A Continuous ate Current I M 3.5 A Turn-Off afe Operating Area RBOA T J = 210 C, I = 3.5 A, I,max = 50 Clamped Inductive V V max A Fig. 18 T hort Circuit afe Operating Area COA J = 210 C, I = 3.5 A, V = 400 V, Non Repetitive >20 µs Reverse ate ource Voltage V 30 V Reverse rain ource Voltage V 25 V Power issipation P tot T J = 210 C, T C = 25 C 769 W Fig. 16 Operating and torage Temperature T stg -55 to 210 C ec Pg1 of 10

2 ection II: tatic Electrical Characteristics Parameter ymbol Conditions Value Min. Typical Max. Unit Notes A: On tate rain ource On Resistance ate ource aturation Voltage C Current ain B: Off tate rain Leakage Current C: Thermal ection III: ynamic Electrical Characteristics A: Capacitance and ate Charge B: witching 1 R (ON) V,AT h FE I 1 All times are relative to the rain-ource Voltage V I = 50 A, T j = 25 C I = 50 A, T j = 125 C I = 50 A, T j = 175 C I = 50 A, T j = 210 C I = 50 A, I /I = 40, T j = 25 C I = 50 A, I /I = 30, T j = 175 C V = 5 V, I = 50 A, T j = 25 C V = 5 V, I = 50 A, T j = 125 C V = 5 V, I = 50 A, T j = 175 C V = 5 V, I = 50 A, T j = 210 C V R = 600 V, V = 0 V, T j = 25 C V R = 600 V, V = 0 V, T j = 125 C V R = 600 V, V = 0 V, T j = 210 C ate Leakage Current I V = 20 V, T j = 25 C 20 na mω Fig. 5 V Fig. 7 Fig. 5 μa Fig. 8 Thermal resistance, junction - case R thjc 0.26 C/W Fig. 19 Parameter ymbol Conditions Value Min. Typical Max. Input Capacitance C iss V = 0 V, V = 100 V, f = 1 MHz 6450 pf Fig. 9 Reverse Transfer/Output Capacitance C rss/c oss V = 100 V, f = 1 MHz 420 pf Fig. 9 Output Capacitance tored Energy E O V = 0 V, V = 400 V, f = 1 MHz 17.4 µj Fig. 10 Effective Output Capacitance, time related C oss,tr I = constant, V = 0 V, V = V 390 pf Effective Output Capacitance, energy related C oss,er V = 0 V, V = V 284 pf ate-ource Charge Q V = -5 3 V 55 nc ate-rain Charge Q V = 0 V, V = V 156 nc ate Charge - Total Q 211 nc f = 1 MHz, V Internal ate Resistance zero bias R AC = 50 mv, V = 0 V, (INT-ZERO) V = 0 V, T j = 210 ºC 0.9 Ω Internal ate Resistance ON R (INT-ON) V > 2.5 V, V = 0 V, T j = 210 ºC 0.09 Ω Turn On elay Time t d(on) T j = 25 ºC, V = 400 V, 25 ns Fall Time, V t f I = 50 A, Resistive Load 44 ns Fig. 11,13 Turn Off elay Time t d(off) Refer to ection V for additional 40 ns Rise Time, V t r driving information. 33 ns Fig. 12,14 Turn On elay Time t d(on) 19 ns Fall Time, V t f T j = 210 ºC, V = 400 V, 43 ns Fig. 11 Turn Off elay Time t d(off) I = 50 A, Resistive Load 89 ns Rise Time, V t r 27 ns Fig. 12 Turn-On Energy Per Pulse E on T j = 25 ºC, V = 400 V, 690 µj Fig. 11,13 Turn-Off Energy Per Pulse E off I = 50 A, Inductive Load 359 µj Fig. 12,14 Total witching Energy E tot Refer to ection V µj Turn-On Energy Per Pulse E on 758 µj Fig. 11 T j = 210 ºC, V = 400 V, Turn-Off Energy Per Pulse E off 337 µj Fig. 12 I = 50 A, Inductive Load Total witching Energy E tot 1095 µj Unit Notes ec Pg2 of 10

3 ection IV: Figures A: tatic Characteristics Figure 1: Typical Output Characteristics at 25 C Figure 2: Typical Output Characteristics at 125 C Figure 3: Typical Output Characteristics at 210 C Figure 4: rain-ource Voltage vs. ate Current Figure 5: Normalized On-Resistance and Current ain vs. Temperature Figure 6: C Current ain vs. rain Current ec Pg3 of 10

4 Figure 7: Typical ate ource aturation Voltage Figure 8: Typical Blocking Characteristics B: ynamic Characteristics Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Output Capacitance tored Energy Figure 11: Typical Turn On Energy Losses and witching Times vs. Temperature Figure 12: Typical Turn Off Energy Losses and witching Times vs. Temperature ec Pg4 of 10

5 Figure 13: Typical Turn On Energy Losses and witching Times vs. rain Current Figure 14: Typical Turn Off Energy Losses and witching Times vs. rain Current Figure 15: Typical Hard witched evice Power Loss vs. 2 Figure 16: Power erating Curve witching Frequency Figure 17: : Forward Bias afe Operating Area at T c= 25 o C Figure 18: Turn-Off afe Operating Area 2 Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology. ec Pg5 of 10

6 Figure 19: Transient Thermal Impedance Figure 20: rain Current erating vs. Pulse Width ec Pg6 of 10

7 ection V: riving the A50JT The A50JT is a current controlled ic transistor which requires a positive gate current for turn-on and to remain in on-state. It may be driven by different drive topologies depending on the intended application. Table 1: Estimated Power Consumption and switching frequencies for various ate rive topologies. rive Topology ate rive Power witching Consumption Frequency imple TTL High Low Constant Current Medium Medium High peed Boost Capacitor Medium High High peed Boost Inductor Low High Proportional Lowest Medium Pulsed Power Medium N/A A: imple TTL rive The A50JT may be driven by 5 V TTL logic by using a simple current amplification stage. The current amplifier output current must meet or exceed the steady state gate current, I,steady, required to operate the A50JT An external gate resistor R, shown in the Figure 21 topology, sets I,steady to the required level which is dependent on the JT drain current I and C current gain h FE, R may be calculated from the equation below. The values of h FE and V,sat may be read from Figure 6 and Figure 7, respectively. V EC,sat can be taken from the PNP datasheet, a partial list of high-temperature PNP and NPN transistors options is given below. High-temperature MOFETs may also be used in the topology. RR,mmmmmm = 5.0 VV VV EEEE,ssssss (PPPPPP) VV,ssssss (JJJJ) h FFFF (TT, II ) II 1.5 TTL ate ignal 0 / 5 V TTL i/p inverted Inverting Current Boost tage 5 V PNP 0 / 5 V TTL o/p NPN I,steady R ic JT Figure 21: imple TTL ate rive Topology Table 2: Partial List of High-Temperature BJTs for TTL ate riving BJT Part Number Type T j,max ( C) PHPT60603PY PNP 175 PHPT60603NY NPN 175 2N2222 NPN 200 2N6730 PNP 200 2N2905 PNP 200 2N5883 PNP 200 2N5885 NPN 200 ec Pg7 of 10

8 B: High peed riving For ultra high speed A50JT switching (t r, t f < 20 ns) while maintaining low gate drive losses the supplied gate current should include a positive current peak during turn-on, a negative voltage peak during turn-off, and continuous gate current I to remain on. An JT is rapidly switched from its blocking state to on-state, when the necessary gate charge for turn-on, Q, is supplied by a burst of high gate current until the gate-source capacitance, C, and gate-drain capacitance, C, are fully charged. Ideally, the burst should terminate when the drain voltage has fallen to its on-state value in order to avoid unnecessary drive losses. A negative voltage peak is recommended for the turn-off transition in order to ensure that the gate current is not being supplied under high dv/dt due to the Miller effect. While satisfactory turn off can be achieved with V = 0 V, a negative V value may be used in order to speed up the turn-off transition. B:1: High peed, Low Loss rive with Boost Capacitor The A50JT may be driven using a High peed, Low Loss rive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide current peaks at turn-on and turn-off for fast switching and a continuous gate current while in on-state. As shown in Figure 22, in this topology two gate driver ICs are utilized. An external gate resistor R is driven by a low voltage driver to supply the continuous gate current throughout on-state.and a gate capacitor C is driven at a higher voltage level to supply a high current peak at turn-on and turn-off. A 3 kv isolated evaluation gate drive board (A03IJT30-FR4) from eneic emiconductor utilizing this topology is commercially available for high and low-side driving, its datasheet provides additional details about this drive topology. V H ate ignal V L C R I ate ic JT Figure 22: High peed, Low Loss rive with Boost Capacitor Topology B:2: High peed, Low Loss rive with Boost Inductor A High peed, Low-Loss river with Boost Inductor is also capable of driving the A50JT at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses I,on and I,off. uring operation, inductor L is charged to a specified I,on current value then made to discharge I L into the JT gate pin using logic control of 1, 2, 3, and 4, as shown in Figure 23. After turn on, while the device remains on the necessary steady state gate current I,steady is supplied from source V CC through R. Please refer to the article A current-source concept for fast and efficient driving of silicon carbide transistors by r. Jacek Rąbkowski for additional information on this driving topology. 3 V CC 1 V CC 2 L 3 V EE ic JT 4 R V EE Figure 23: High peed, Low-Loss river with Boost Inductor Topology 3 Archives of Electrical Engineering. Volume 62, Issue 2, Pages , IN (Print) , OI: /aee , June 2013 ec Pg8 of 10

9 C: Proportional ate Current riving A proportional gate drive topology may be beneficial for applications in which the A50JT will operate over a wide range of drain current conditions to lower the gate drive power consumption. A proportional gate driver relies on instantaneous drain current I feedback to vary the steady state gate current I,steady supplied to the A50JT C:1: Voltage Controlled Proportional river A voltage controlled proportional driver relies on a gate drive integrated circuit to detect the A50JT drain-source voltage V during on-state to sense I. The integrated circuit will then increase or decrease I in response to I. This allows I and gate drive power consumption to reduce while I is low or for I to increase when I increases. A high voltage diode connected between the drain and sense protects the integrated circuit from high-voltage when blocking. A simplified version of this topology is shown in Figure 24. Additional information will be available in the future at ate ignal ignal ense Proportional ate Current river Output HV iode I,steady ic JT Figure 24: implified Voltage Controlled Proportional river C:2: Current Controlled Proportional river The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback of the A50JT drain current during on-state to supply I,steady into the gate. I,steady will increase or decrease in response to I at a fixed forced current gain which is set be the turns ratio of the transformer, h force = I / I = N 2 / N 1. A50JT is initially tuned-on using a gate current pulse supplied into an RC drive circuit to allow I current to begin flowing. This topology allows I,steady and the gate drive power consumption to reduce while I is relatively low or for I,steady to increase when I increases. A simplified version of this topology is shown in Figure 25. Additional information will be available in the future at N 2 ate ignal ic JT N 3 N 1 N 2 Figure 25: implified Current Controlled Proportional river ec Pg9 of 10

10 ection VI: Package imensions TO-258 PACKAE OUTLINE NOTE 1. CONTROLLE IMENION I INCH. IMENION IN BRACKET I MILLIMETER. 2. IMENION O NOT INCLUE EN FLAH, MOL FLAH, MATERIAL PROTRUION Revision History ate Revision Comments upersedes 2014/12/12 5 Updated Electrical Characteristics 2014/08/23 4 Updated Electrical Characteristics 2014/04/10 3 Updated Electrical Characteristics 2014/02/05 2 Updated Electrical Characteristics 2013/12/19 1 Updated ate rive ection 2013/12/05 0 Initial release Published by eneic emiconductor, Inc Trade Center Place uite 155 ulles, VA eneic emiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. eneic disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, eneic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. ec Pg10 of 10

11 ection VII: PICE Model Parameters A50JT This is a secure document. Please copy this code from the PICE model PF file on our website ( into LTPICE (version 4) software for simulation of the A50JT MOEL OF eneic emiconductor Inc. $Revision: 1.3 $ $ate: 12-EC-2014 $ eneic emiconductor Inc Trade Center Place te. 155 ulles, VA COPYRIHT (C) 2014 eneic emiconductor Inc. ALL RIHT REERVE These models are provided "A I, WHERE I, AN WITH NO WARRANTY OF ANY KIN EITHER EXPREE OR IMPLIE, INCLUIN BUT NOT LIMITE TO ANY IMPLIE WARRANTIE OF MERCHANTABILITY AN FITNE FOR A PARTICULAR PURPOE." Models accurate up to 2 times rated drain current..model A50JT06 NPN + I 5.00E-47 + IE 1.26E-26 + E BF BR IKF NF 1 + NE 2 + RB IRB RBM RE RC CJC E-9 + VJC MJC CJE 6.026E-09 + VJE MJE XTI 3 + XTB TRC1 7.00E-3 + VCEO ICRATIN MF eneic_emiconductor End of A50JT06 PICE Model ec Pg1 of 1