Normally OFF Silicon Carbide Junction Transistor

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Normally OFF Silicon Carbide Junction Transistor Features 210 C maximum operating temperature ate Oxide Free SiC switch Exceptional Safe Operating Area Excellent ain Linearity Temperature Independent

1 Normally OFF Silicon Carbide Junction Transistor Features 210 C maximum operating temperature ate Oxide Free SiC switch Exceptional Safe Operating Area Excellent ain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Co-efficient of R S,ON Suitable for connecting an anti-parallel diode Advantages Compatible with Si MOSFET/IBT gate-drivers > 20 µs Short-Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal istortion High Amplifier Bandwidth ie Size = 2.85 mm x 2.85 mm Applications V S = 600 V R S(ON) = 65 mω 25 o C = 45 A h FE = 110 own Hole Oil rilling, eothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor rives Absolute Maximum Ratings (T C = 25 o C unless otherwise specified) Parameter Symbol Conditions Values Unit rain Source Voltage V S V S = 0 V 600 V Continuous rain Current I T C = 25 C 45 A Continuous rain Current I T C > 125 C, assumes R thjc < 0.53 o C/W 20 A ate Peak Current I M 1.3 A Turn-Off Safe Operating Area RBSOA T VJ = 210 o C, I,max = 20 Clamped Inductive V S V Smax A Short Circuit Safe Operating Area SCSOA T VJ = 210 o C, I = 1 A, V S = 400 V, Non Repetitive 20 µs Reverse ate Source Voltage V S 30 V Reverse rain Source Voltage V S 40 V Operating Junction and Storage Temperature T j, T stg -55 to 210 C Maximum Processing Temperature T Proc 10 min. maximum 325 C Electrical Characteristics Parameter Symbol Conditions Values min. typ. max. Unit On Characteristics rain Source On Resistance ate Source Saturation Voltage C Current ain R S(ON) V S,SAT h FE I = 20 A, I = 400 ma, T j = 25 C I = 20 A, I = 500 ma, T j = 125 C I = 20 A, I = 1000 ma, T j = 175 C I = 20 A, I = 1000 ma, T j = 210 C = 20 A, I /I = 40, T j = 25 C 3.44 I = 20 A, I /I = 30, T j = 175 C 3.24 V S = 5 V, I = 20 A, T j = 25 C 110 V S = 5 V, I = 20 A, T j = 125 C 78 V S = 5 V, I = 20 A, T j = 175 C 73 V S = 5 V, I = 20 A, T j = 210 C 71 mω V Off Characteristics rain Leakage Current I SS V R = 600 V, V S = 0 V, T j = 25 C 10 V R = 600 V, V S = 0 V, T j = 210 C 100 µa ate Source Leakage Current I SS V S = -20 V, T j = 25 C 20 na Feb Pg1 of 9

2 Electrical Characteristics Parameter Symbol Conditions Values min. typ. max. Unit Capacitance Characteristics Input Capacitance C iss V S = 0 V, V = 100 V, f = 1 MHz 2100 pf Reverse Transfer/Output Capacitance C rss /C oss V = 100 V, f = 1 MHz 160 pf Figures Figure 1: Typical Output Characteristics at 25 C Figure 2: Typical Output Characteristics at 125 C Figure 3: Typical Output Characteristics at 175 C Figure 4: Typical Output Characteristics at 210 C Feb Pg2 of 9

3 Figure 5: Typical ate Source Saturation Voltage Figure 6: Normalized On-Resistance and Current ain vs. Temperature Figure 7: Typical Blocking Characteristics Figure 8: Capacitance Characteristics Feb Pg3 of 9

4 riving the rive Topology ate rive Power Switching Consumption Frequency Application Emphasis Availability TTL Logic High Low Wide Temperature Range Coming Soon Constant Current Medium Medium Wide Temperature Range Coming Soon High Speed Boost Capacitor Medium High Fast Switching Production High Speed Boost Inductor Low High Ultra Fast Switching Coming Soon Proportional Lowest High Wide rain Current Range Coming Soon Pulsed Power Medium N/A Pulse Power Coming Soon A: Static TTL Logic riving The may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must meet or exceed the steady state gate current (I,steady ) required to operate the A20JT06- CAL. The power level of the supply can be estimated from the target duty cycle of the particular application. I,steady is dependent on the anticipated drain current I through the SJT and the C current gain h FE, it may be calculated from the following equation. An accurate value of the h FE may be read from Figure 6. II,ssssssssssss II h FFFF (TT, II ) 1.5 TTL ate Signal 5 / 0 V TTL i/p 5 V I,steady SiC SJT S Figure 9: TTL ate rive Schematic B: High Speed riving The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 10 which features a positive current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on. Figure 10: An idealized gate current waveform for fast switching of an SJT. An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, Q, for turn-on is supplied by a burst of high gate current, I,on, until the gate-source capacitance, C S, and gate-drain capacitance, C, are fully charged. QQ oooo = II,oooo tt 1 QQ oooo QQ gggg + QQ gggg Feb Pg4 of 9

5 Ideally, I,pon should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady on-state. In practice, the rise time of the I,on pulse is affected by the parasitic inductances, L par in the device package and drive circuit. A voltage developed across the parasitic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V S,sat (see Figure 5) level to counter these effects. A high negative peak current, -I,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V S = 0 V, a negative gate voltage V S may be used in order to speed up the turn-off transition. Two high-speed drive topologies for the SiC SJTs are presented below. B:1: High Speed, Low Loss rive with Boost Capacitor, A03IJT30-FR4 The A20JT06- CAL may be driven using a High Speed, Low Loss rive with Boost Capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in on-state. A 3 kv isolated evaluation gate drive board (A03IJT30-FR4) utilizing this topology is commercially available for high and lowside driving, its datasheet provides additional details about this drive topology. VCC High V L A03IJT30-FR4 ate river Board +12 V C2 U3 C5 VCC High RTN ate Signal Signal R1 Signal RTN U1 U2 V L V L C6 R2 R3 U5 U6 V H V L C9 C10 C8 1 C1 C2 R4 R1 R2 ate I SiC SJT S +12 V VCC Low C1 U4 V H C3 C4 Source VCC Low RTN Voltage Isolation Barrier Figure 11: Topology of the A03IJT30-FR4 Two Voltage Source gate driver. The A03IJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (R1, R2) pre-installed for an effective gate resistance 3 of R = 3.75 Ω. It may be necessary for the user to reduce R1 and R2 under high drain current conditions for safe operation of the A20JT06- CAL. The steady state current supplied to the gate pin of the A20JT06- CAL with on-board R = 3.75 Ω, is shown in Figure 12. The maximum allowable safe value of R for the user s required drain current can be read from Figure 13. For the, R must be reduced for I ~13 A for safe operation with the A03IJT30-FR4. For operation at I ~13 A, R may be calculated from the following equation, which contains the C current gain h FE (Figure 6) and the gatesource saturation voltage V S,sat (Figure 5). RR,mmmmmm = 4.7VV VV,ssssss h FFFF (TT, II ) 0.6Ω II 1.5 Feb Pg5 of 9

6 Figure 12: Typical steady state gate current supplied by the A03IJT30-FR4 board for the with the on board resistance of 3.75 Ω Figure 13: Maximum gate resistance for safe operation of the at different drain currents using the A03IJT30-FR4 board. B:2: High Speed, Low Loss rive with Boost Inductor A High Speed, Low-Loss river with Boost Inductor is also capable of driving the A06JT12- CAL at high-speed. It utilizes a gate drive inductor instead of a capacitor to provide the high-current gate current pulses I,on and I,off. uring operation, inductor L is charged to a specified I,on current value then made to discharge I L into the SJT gate pin using logic control of S 1, S 2, S 3, and S 4, as shown in Figure 14. After turn on, while the device remains on the necessary steady state gate current I,steady is supplied from source V CC through R. Please refer to the article A current-source concept for fast and efficient driving of silicon carbide transistors by r. Jacek Rąbkowski for additional information on this driving topology. 4 V CC S 1 V CC S 2 L S 3 SiC SJT S 4 R S Figure 14: Simplified Inductive Pulsed rive Topology 3 R = (1/R1 +1/R2) -1. river is pre-installed with R1 = R2 = 7.5 Ω 4 Archives of Electrical Engineering. Volume 62, Issue 2, Pages , ISSN (Print) , OI: /aee , June 2013 Feb Pg6 of 9

7 C: Proportional ate Current riving For applications in which the A20JT06- CAL will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain current I feedback to vary the steady state gate current I,steady supplied to the A20JT06- CAL C:1: Voltage Controlled Proportional river The voltage controlled proportional driver relies on a gate drive IC to detect the A20JT06- CAL drain-source voltage V S during on-state to sense I. The gate drive IC will then increase or decrease I,steady in response to I. This allows I,steady, and thus the gate drive power consumption, to be reduced while I is relatively low or for I,steady to increase when is I higher. A high voltage diode connected between the drain and sense protects the IC from high-voltage when the driver and A20JT06- CAL are in off-state. A simplified version of this topology is shown in Figure 15, additional information will be available in the future at ate Signal Signal Sense Proportional ate Current river Output HV iode I,steady SiC SJT S Figure 15: Simplified Voltage Controlled Proportional river C:2: Current Controlled Proportional river The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback I of the A20JT06- CAL during on-state to supply I,steady into the device gate. I,steady will then increase or decrease in response to I at a fixed forced current gain which is set be the turns ratio of the transformer, h force = I / I = N 2 / N 1. A20JT06- CAL is initially tuned-on using a gate current pulse supplied into an RC drive circuit to allow I current to begin flowing. This topology allows I,steady, and thus the gate drive power consumption, to be reduced while I is relatively low or for I,steady to increase when is I higher. A simplified version of this topology is shown in Figure 16, additional information will be available in the future at N 2 ate Signal SiC SJT S N 3 N 1 N 2 Figure 16: Simplified Current Controlled Proportional river Feb Pg7 of 9

8 Mechanical Parameters ie imensions 2.85 x 2.85 mm x 112 mil 2 ie Area total / active 8.12/6.60 mm /10237 mil 2 ie Thickness 360 µm 14 mil Wafer Size 100 mm 3937 mil Flat Position 0 deg 0 deg ie Frontside Passivation ate/source Pad Metallization Bottom rain Pad Metallization ie Attach Wire Bond Reject ink dot size Recommended storage environment Polyimide 4000 nm Al 400 nm Ni nm Au Electrically conductive glue or solder Al 10 mil (Source) Al 3 mil (ate) Φ 0.3 mm Store in original container, in dry nitrogen, < 6 months at an ambient temperature of 23 C Chip imensions: A C mm mil E IE A B F B SOURCE WIREBONABLE C E H F ATE WIREBONABLE H Feb Pg8 of 9

9 Revision History ate Revision Comments Supersedes 2015/02/09 9 Updated Electrical Characteristics 2014/08/26 3 Updated Electrical Characteristics 2014/04/29 2 Updated Electrical Characteristics 2014/02/27 1 Updated Electrical Characteristics 2013/12/04 0 Initial release Published by enesic Semiconductor, Inc Trade Center Place Suite 155 ulles, VA enesic Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice. enesic disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any intellectual property rights is granted by this document. Unless otherwise expressly indicated, enesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage. Feb Pg9 of 9

10 SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PF file on our website ( into LTSPICE (version 4) software for simulation of the. MOEL OF enesic Semiconductor Inc. $Revision: 1.1 $ $ate: 27-FEB-2014 $ enesic Semiconductor Inc Trade Center Place Ste. 155 ulles, VA COPYRIHT (C) 2013 enesic Semiconductor Inc. ALL RIHTS RESERVE These models are provided "AS IS, WHERE IS, AN WITH NO WARRANTY OF ANY KIN EITHER EXPRESSE OR IMPLIE, INCLUIN BUT NOT LIMITE TO ANY IMPLIE WARRANTIES OF MERCHANTABILITY AN FITNESS FOR A PARTICULAR PURPOSE." Models accurate up to 2 times rated drain current..model A20JT06 NPN + IS 5.00E-47 + ISE 1.26E-28 + E BF BR IKF NF 1 + NE 2 + RB RE RC CJC E-10 + VJC MJC CJE E-9 + VJE MJE XTI 3 + XTB TRC1 6.20E-03 + VCEO ICRATIN 20 + MF enesic_semiconductor End of SPICE Model April Pg1 of 1

Table of Contents. I D,max = 50 Clamped Inductive Load

Table of Contents. I D,max = 50 Clamped Inductive Load Normally OFF Silicon Carbide Junction Transistor Features 175 C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent