Optical Maskless Lithography (OML) Project Status

Transcription

1 Optical Maskless Lithography (OML) Project Status Timothy O Neil, Arno Bleeker, Kars Troost SEMATECH ML 2 Conference January 2005 / Slide 1

2 Agenda Introduction and Principles of Operation DARPA Program Activities w Contrast Device Test Stands w Systems Engineering w Modeling Results Micronic SIGMA 7300 results Summary and Conclusions / Slide 2

3 Project Status within ASML ASML views OML as natural extension of the optical lithography roadmap, especially for low wafer/mask situations Throughout 2004, technical and commercial studies have been performed w Technical SLM contrast device Projection and illumination optics Datapath w Commercial Customer applications Product positioning and roadmap / Slide 3

4 Advantages of OML Fab transparency (e.g. same resist platform as mask-based) Advances in conventional mask-based lithography are readily extendable to OML w Wavelength reduction w Immersion w OPC w Strong phase-shifting Maskless lithography provides w Reduced cost of introduction and faster time-to-market for new designs w Reduced cost of manufacturing of low-volume designs Leverages TWINSCAN platform and optics expertise at customer and within ASML / Slide 4

5 OML: Projected Key Specifications Technology node: Wavelength: Illumination: Throughput: 65/45nm half pitch 193 nm Conventional, Annular, Dipole, Quasar,... 5 wph (300mm) Optical Maskless Scanner TWIN SCAN XT MASK LESS / Slide 5

6 Optical Maskless Lithography System Overview Concept w Illumination light is reflected from a dynamic pattern generating device (Spatial Light Modulator, or SLM) w SLM contains a section of a desired circuit pattern w Pattern is imaged onto a substrate through a high de-magnification projection lens First Technology Use: Micronic w Sigma 7300 photomask writing system (results reported in this meeting) w One SLM (16 µm mirrors, 1 MPixel) (1): Sandström, et al. Micronic Laser Systems. Pattern Generation with SLM Imaging. Proceedings of SPIE Vol (2002) / Slide 6 (1)

7 Imaging Engine of the OML Scanner The Spatial Light Modulator (SLM) (2) (2) OML Scanner DUV Laser Illum Optics SLM Contrast Devices >100x Proj Optics Image Plane Example Contrast Device: Micronic / Fraunhofer SLM 16 µm square tilting pixels 8 mm x 33mm active area 512 x 2048 pixels (1.048 MPixels per SLM) Multiple devices are used in parallel to achieve throughput requirements Multiple contrast device technologies are being evaluated. (2) Sandström, et al. Micronic Laser Systems. Pattern Generation with SLM Imaging. Proceedings of SPIE Vol (2002) / Slide 7

8 Systems Engineering Alternative Pixel Geometries Tilt Phase-Step Tilt Piston Operating Principle Phase interference between each half of mirror creates net intensity thru tilt. Like tilt with λ/4 phase step. Provides balanced intensity range for 0 o and 180 o phase. Pure phase manipulation. Interference with neighboring mirrors manipulates intensity. Phase & Intensity Range 0 o phase: 0% - 100% 180 o phase: 0% - 4% 0 o phase: 0% - 50% 180 o phase: 0% - 50% Any phase between 0 o and 360 o : 0% - 100% ASML is actively engaging with all SLM suppliers to evaluate actuation principles and alternatives. / Slide 8

9 Tilt SLMs Principle of Image Formation Tilt Mirror Intensity Bright (full reflection into pupil) when mirror is at zero tilt Gray Tone (partial reflection into pupil) at intermediate tilt positions Attenuated Phase Shift (reflection into pupil with 180 o phase shift) when mirror tilt is beyond λ/4 height difference edge-to-edge Capable of emulating the imaging capabilities of binary and att-psm masks. / Slide 9

10 Phase-Step Tilt SLMs emulate alt-psm and CPLTM Masks Clear Dark Attenuated Shifted Dark (no reflection into pupil) when mirror is at zero tilt Bright (70% reflection), symmetrical in positive and negative phase Gray Tone (partial reflection into pupil) at intermediate tilt positions for both positive and negative phase Im(Refl) [Phase] Re(Refl) [Amplitude] Amplitude +0.7 Tilt α / Slide 10

11 Piston SLMs emulate also alt-psm, CPLTM and multi-phase masks Gray Tone (grouped mirrors for destructive interference) by alternating pistons in checkerboard pattern. w Gray-tone based on relative heights in checkerboard w Phase based on the average height of the checkerboard Phase Edge (line interference) by alternating rows / columns of height. / Slide 11

12 Writing Strategy: Loading and Writing a Pattern 1. Break die pattern into stripes. 2. Break stripe into micro-stripes. Each micro-stripe spans one row of SLMs in the array. Micro-shot n Micro-shot n+1 Micro-shot n+2 3. Load full micro-stripes into each SLMs drive electronics. 4. Address the position of the next stamp in the micro-stripe. This address determines the pattern data from the die to be included in stamp. + = Idealized pattern SLM data calibration Data to be sent to SLM 5. For each stamp, apply pixel calibration data and send final processed image to SLM. 6. Wafer is printed by controlling the sequence of stamps and stripes across all SLMs in the array. / Slide 12

13 Writing Strategy: Field Writing Strategies Field Writing Strategy I A given stripe in all fields on the wafer is exposed before proceeding to the next stripe Field Writing Strategy II All stripes in a given row of fields are exposed proceeding to the next row of fields Field Writing Strategy III All stripes in a given field are exposed proceeding to the next field in the column The data path architecture can be configured for different field writing strategies. / Slide 13

14 Data Path: In-line Rasterization Once per Design [60... min] Once per Lot [60 min] 525GB (800GB) Parse convert 0.2 GB/s Design file: 525 GB ATP 800GB Max. 750GB (1.2TB) Image cache: I/O bandwidth: 2.8 GB/s 34 servers (9TB) Print buffer: holds 2 image stripes (SDRAM) Once per wafer [12 min] Rasterization supersample 2 GPix/s Invariant pixel manipulations 2 GPix/s 2 x 26 GB Once per Die Extraction & Rasterisation twice per wafer 80% eff. writing time, Variant pixel Manipulations 250 GPix/s To DAC s, Amp s & SLM / Slide 14

15 Data Path: Off-line Rasterization Design file: 525 GB ATP 800GB Max. Intermediate storage: IO bandwidth: 0.4 GB/s 8 servers (2TB) Image cache: I/O bandwidth: 1.6 GB/s 22 servers (6TB) Once per Design [60... min] 525GB (800GB) Parse Convert 0.2GB/s 750GB (1.2TB) Rasterize Supersample 0.4GPix/s 860GB (1.4TB) Once per Lot [60 min] Once per wafer [12 min] 1.4GB/s Invariant pixel manipulations 2 GPix/s 2x0.7 TB Print buffer: Holds 2 shots for entire die (SDRAM) Once per Die Variant pixel Manipulations 250 GPix/s To DAC s, Amp s & SLM / Slide 15

16 Technical Challenges OML SLM Contrast Device w Mirror variability w Calibration w Manufacturability Lasers with improved pulse-to-pulse stability and jitter performance Rasterization for different contrast device types Logistics for seamless factory integration of OML / Slide 16

17 Agenda Introduction and Principles of Operation DARPA Program Activities w Contrast Device Test Stands w Systems Engineering w Modeling Results Micronic SIGMA 7300 results Summary and Conclusions / Slide 17

18 Program Activities DARPA Contract Awarded to ASML, June 30, 2004 Development of calibration and imaging test stands w w Characterize SLM mechanical properties, including shape, dynamic response, flatness, height variation, repeatability, drift, etc. Test Bench 1: White Light Interferometer Demonstrate SLM imaging capabilities with aerial image measurements at target wavelength. Test Bench 2: SLM Calibration and Imaging Test Stand Characterize and image multiple candidate contrast devices w Working closely with Fraunhofer and DARPA-sponsored contrast device suppliers Systems Engineering w w w Pixel Geometry Tradeoff Study -- developing modeling tools to simulate the lithographic imaging performance of different SLM types (e.g. tilt, piston, etc.), and the imaging impact of known imperfections System Requirements and Error Budgets -- developing system performance budgets to be able to place specifications on critical contrast device parameters Calibration and Rasterization Algorithm Development -- developing calibration and pattern generation schemes for optimizing the imaging performance of each contrast device type and incorporating low k1 imaging enhancements (e.g. off-axis illumination, OPC, etc.) / Slide 18

19 White Light Interferometer Measurements Zygo NewView 5000 Series System for Surface Profiling Z resolution ~ 0.1nm Lateral resolution ~ 0.5 µm Images courtesy of Zygo Corportation / Slide 19

20 Zygo White Light Tester Device Independent Infrastructure IBM Workstation Control Software: LabVIEW 7.1 / C Camera & Interferometer Illumination Source Frame grabber Serial port GPIB Interface Zygo NewView 5032 Stages DUT TCP/IP Network Contrast Device Drive Electronics ASML Computer interfaces with Zygo NewView 5032 / Slide 20

21 / Slide 21

22 Aerial Image Tester Optical Magnification of SLM Image Image at CCD Available magnifications are 3, 9.6 and 24 x In the tester, SLM mirrors are not resolved at image plane. The optical design mimics the condition of a future OML tool. Contrast Device Mirror Array / Slide 22

23 Aerial Image Tester Device Independent Infrastructure IBM Workstation Control Software: LabVIEW 7.1 / C Camera & Controller Hamamatsu CCD 193 nm Litho Laser Lambda NovaLine A2010 Frame grabber Serial port XY Stage & Controller Physik Instrumente GPIB Interface ASML Aerial Image Tester DUT Contrast Device Drive Electronics ASML Computer Controls laser, drives stages, collects camera images / Slide 23

24 Pattern Generator & Device Drive Electronics Architecture Supports Multiple Contrast Devices 2 meter flexible interconnect Pattern Generator PCB (host) Memory Data Path Transfers Mirror Contrast Pattern from PC Device to Driver Contrast PCB FPGA (plug in module) Device USB 2.0 Interface 1 GByte Pattern Generator PCB (Host) Accepts Contrast Device Driver PCB plug-in module (customizable plug-in) Required mirror settings are downloaded over USB port and stored in 1 GByte of memory Field Programmable Gate Array (FPGA) drives 18 channels of Mhz (4.3 Gbps) FPGA is re-configurable via the USB port to support multiple contrast devices Digital Interface DAC Amp Analog Outputs Contrast Device Interface PCB DUT 1/2 meter flexible interconnect Contrast Device Driver PCB (Module) 150 x 150 mm CMC plug-in module Baseline design drives 16 analog outputs with 30V swing and 10 bit accuracy at MHz Modules will be developed as needed to drive specific contrast devices Host / module are scalable to drive more lines by using multiple boards / Slide 24

25 Calibration and Imaging Test Stand Status Tester Optical Design has been completed w Mag Lenses and electronics have been designed to accommodate different SLM from Silicon Light Machines, Micronic, and Lucent Technologies. Projection Optics Optical fabrication complete Jan 2005 Illumination Optics fabrication complete Feb 2005 Optical assembly expected completion Feb 2005 Datapath/Electronics Complete March of 2005 Integration of imaging tester complete March 2005 Testing of static contrast devices March 2005 Testing of final devices Q4 05 / Slide 25

26 Systems Engineering Impact of SLM Imperfections Imperfection Mirror Reflectance Mirror Height Variation Mirror Flatness (Intra-Mirror) Mirror Gap Properties SLM Global Flatness Impact on Imaging Non-uniform intensity, resulting in contrast reduction, poor uniformity, errors in CDU and overlay Non-uniform phase, resulting in contrast reduction, poor uniformity, errors in CDU and overlay Non-uniform intensity and phase across the mirror, resulting in contrast reduction, poor uniformity, errors in CDU and overlay Stray light and/or undesired interference with mirrors, resulting in image degradation Non-flat chip results in telecentricity effects at the wafer / Slide 26

27 Systems Engineering Height Variation and its Impact on the Aerial Image thru Focus Best focus, 0.4% uniformity -50 nm defocus, 2.25% uniformity -25 nm defocus, 1.3% uniformity +25 nm defocus, 1.2% uniformity +50 nm defocus, 2% uniformity / Slide 27

28 Applications Sample Imaging Applications with OML Double-dipole elbow Isolated line exposure dose window Memory cell Alternating Phase Shift with Trim OPC with Gray Scaling Dense Contact Holes / Slide 28

29 Applications Double Dipole Decomposition of 70 nm Elbows Simulation w NA 0.93, 193 nm w Dipole, sigma 0.7/0.8/30 o w Tilt Mirror SLM w High-NA vector unpolarized model w No OPC Results w Elbow features print the same in mask-based and OML w Any OPC needed is exactly the same for mask-based and OML Data + = Exp. 1 Exp. 2 Y (nm) Vertical Component Mask = Y (nm) Horisontal Component X (nm) Y (nm) X (nm) Vertical Component OML = Y (nm) Horisontal Component X (nm) X (nm) Y (nm) Y (nm) Resulting Image X (nm) Resulting Image X (nm) Courtesy of Micronic / Slide 29

30 Applications Exposure Dose Window, 50 nm Isolated Line w/ Scatter Bars Simulation: w NA 0.93, 193 nm, dipole illumination w Tilt Mirror SLM w High-NA vector unpolarized model w 30 nm OML pixels (wafer scale) Line: 1.67 pixels wide Scatter Bars: 0.67 pixels wide Result: Matched Exposure Latitude with Mask-Based & OML 6% Att-PSM Reticle OML Data / Slide 30

31 Applications Memory Cell Gate Layer with OPC and Custom Illumination Original Pattern Aerial Image Intensity thru Focus Rasterized Pattern w/ OPC Optimized Illuminaton for Improved Depth of Focus Best Focus -50 nm de-focus -100 nm de-focus / Slide 31

32 Applications Alternating PSM with Binary Trim Mask Mask + Contrast Device + w Phase-Step Tilt Mirror SLM, 30 nm wafer scale, 0.93 NA in resist w Printed linewidth is 35 nm w Linewidth and resist cross-section is maintained as the image is shifted through the mirror grid Height (nm) Resist Cross Sections Grid shift 0 nm Grid shift 5 nm Grid shift 10 nm Grid shift 15 nm Grid shift 20 nm Grid shift 25 nm Grid shift 30 nm Height (nm) nm X (nm) X (nm) Courtesy of Micronic / Slide 32

33 Applications Optical Proximity Correction (OPC) with Gray Scaling Without OPC With OPC Mirror Tilt [mrad] / Slide 33

34 80 nm Half-Pitch Contact Holes Shift = 0 nm / Slide 34

35 80 nm Half-Pitch Contact Holes Shift = 5 nm / Slide 35

36 80 nm Half-Pitch Contact Holes Shift = 10 nm / Slide 36

37 80 nm Half-Pitch Contact Holes Shift = 15 nm / Slide 37

38 80 nm Half-Pitch Contact Holes Shift = 20 nm / Slide 38

39 80 nm Half-Pitch Contact Holes Shift = 20 nm Grayscaling makes aerial image independent of grid position / Slide 39

40 Agenda Introduction and Principles of Operation DARPA Program Activities w Contrast Device Test Stands w Systems Engineering w Modeling Results SLM based Printing Results: Micronic SIGMA 7300 Summary and Conclusions / Slide 40

41 Micronic Sigma7300 SLM-based mask writer for 65 and 45 nm reticles / Slide 41

42 Micronic Sigma7300 Second generation SLM-based mask writer Status January 2005 Product development finalized β-shipment late 2003 Field evaluation completed at major mask shop. System selected. Shipping to customers Major application space Quick turn-around and cost-effective production of 65 nm and 45 nm node reticles Interconnect layers (manhattan 150 & nm dense X-design) on mask 2 nd level printing of advanced PSM (alt-psm, CPL) 150 nm space on mask / Slide 42

43 Sigma7300 Technical Data Laser SLM KrF (248nm), 2 khz excimer One SLM Gen. 2B 512 x 2048 mirrors 16 x 16 µm Al alloy mirror Lifetime ~6 months (24/7 op.) Optics 0.82 NA 200x de-magnification Data channel FPGA Supports 2 Gpixel/sec On-line pattern accuracy enhancements, e.g. Corner Enhancement (CE) SLM chip module in Sigma7300 Throughput 3-hour 6 reticle write time (using four exposure passes) Independent of design and OPC (>100 Gb mask data volume) 16x16 µm Al alloy micro mirrors / Slide 43

44 Corner Enhancement (CE) CAD data Gray pixel data in pass #1 SEM image Sigma7300 exposure Gray scale enhancements at corners for increased pattern fidelity Line-end shortening, corner pullback and OPC fidelity match 50 kev VSB Pattern matching to 1 st level for 2 nd level printing of advanced PSM On-line enhancement in FPGA Adjustment Processor No throughput penalty / Slide 44

45 Corner Enhancement (CE) CAD data Gray pixel data in pass #1 SEM image Sigma7300 exposure Gray scale enhancements at corners for increased pattern fidelity Line-end shortening, corner pullback and OPC fidelity match 50 kev VSB Pattern matching to 1 st level for 2 nd level printing of advanced PSM On-line enhancement in FPGA Adjustment Processor No throughput penalty / Slide 45

46 Throughput Write time in high-quality mode (4-pass) is typically 3 hours Throughput only depends on the mask layout Independent of pattern design and OPC (>100 Gb mask data volume) 3-pass or 2-pass write modes for looser mask requirements. Same resolution and address unit as in 4-pass mode. Non-critical patterns, e.g. text and barcodes, printed with 1-pass Total job time (hours) Total mask write times, including overhead, in different write modes Typical 90-nm node metal layer reticle Mask layout 4-pass 4-pass with CE 3-pass 2-pass / Slide 46

47 Performance on Mask Resolution w Min. dark assist line 130 nm w Min. clear assist line 170 nm w CD linearity, iso space <10 nm (range), nm w CD linearity, contact <10 nm (range), nm CD uniformity w Global (132x132 mm) <7 nm (3σ) w Local <5 nm (3σ) Registration w Global (140x140 mm) <12 nm (3σ) w Local <7 nm (3σ) Alignment system for PSM w Layer to layer overlay <20 nm (mean+3σ) / Slide 47

48 CD Linearity CD Linearity Isolated lines and spaces <10 nm (range) [ nm] / Slide 48

49 Global CD Uniformity 132x132 mm. Composite 260 nm isolated spaces. X Y Linewidth 3-sigma Range/2 260 nm 6,2 5,7 / Slide 49 5 nm - 5 nm Linewidth 3-sigma Range/2 260 nm 5,0 5,0 5 nm - 5 nm

50 Any Angle Performance Good performance for X-design 520 Angular CD variation w 4.4 nm (0,45,90,135 degree) w 5.5 nm (any angle) CDU and LER almost independent of pattern orientation Throughput independent of pattern orientation CD (nm) Angle (Deg) / Slide 50

51 Layer to layer overlay (nm) Second Layer Alignment for PSM Sigma7300 PSM alignment monitor plate, May-October Plate # (May-Oct. 2004) / Slide 51 Y 3s Y Mean Layer to layer overlay (nm) Plate # (May-Oct. 2004) X 3s X Mean

52 Conclusions Sigma7300, a second generation SLM-based mask writer, is shipping to customers Performance on mask meets or exceeds expectations Field evaluation completed at major mask shop. System selected. Major application space: w 65 and 45 nm interconnect layer reticles w Second layer printing of advanced PSM (AAPSM, CPL) / Slide 52

53 Agenda Introduction and Principles of Operation DARPA Program Activities w Contrast Device Test Stands w Systems Engineering w Modeling Results SLM based Printing Results: Micronic SIGMA 7300 Summary and Conclusions / Slide 53

54 Summary OML Advantages Save money on mask costs Improve time to market for prototype, low-volume, and medium-volume wafer runs w Fab transparency with the same lithographic processes l, NA, resists, (OPC) Enable strong-phase shift applications that are impossible or prohibitively expensive with masks Make Engineering and Development easier w Enable more characterization tests for processes / design libraries w Evaluate alternative designs and design iterations in resist / Slide 54

55 Current Wafer Fab Regular scanners All designs All reticles All wafers All output wafers / Slide 55

56 Vision on Future Wafer Fab Regular scanners High volume designs Few reticles Most wafers High volume wafers New designs Few wafers Low volume and design prototype wafers New and Low-Volume and Medium-Volume Designs Maskless scanners / Slide 56

57 Conclusions ASML is actively investigating OML as lower-nre, more flexible alternative to mask-based lithography for w Lower cost and faster design verification in silicon w Lower cost low-volume production of ASICs and SOCs Micronic SIGMA 7300 results proves SLM based printing The SLM for a 5-wph 65/45nm OML Scanner is actively addressed through US (DARPA) and European cooperation w Supporting mask-equivalent 65/45nm imaging performance ASML Views FAB Transparency as a key advantage of OML Acknowledgements w This work is partly sponsored by DARPA under Contract # N C-8027 / Slide 57