Metrology in the context of holistic Lithography

Transcription

1 Metrology in the context of holistic Lithography Jeroen Ottens Product System Engineer YieldStar, ASML

2 Lithography is at the heart of chip manufacturing Slide 2 25.April.2017 Repeat 30 to 40 times to build 3 dimensional structure

3 Overlay and CD-Uniformity (CDU) are critical for device performance Slide 3 20 November 2017 Rule-of-thumb: OV 30 % of CD CDU 10 % of CD Critical Dimension (CD) OV Today s devices: CD 16 nm OV < 5 nm CDU < 1.5 nm

4 Holistic Lithography Concept Scanner aspects Metrology aspects - YieldStar - Computational Metrology - Pattern Fidelity Monitoring Conclusions l Slide 4 25.Apirl.2017

5 ASML Holistic Lithography approach seeks to maximize patterning process performance and control Slide 5 25.April Lithography scanner with advanced capability (Imaging, overlay and focus) Process Window Enhancement Process Window Control 3 2 Computational Lithography Full chip process window detection Metrology

6 Scanner aspects Slide 6 25.April.2017

7 40 years projection lithography driving performance improvements 3 orders of magnitude* Slide 7 25.April.2017 Micralign Innocence Understanding Models and setup Process control Metrology feedback Mark design and sampling Holistic approach High order corrections Integrated metrology Computational NXT:1950i litho Design for control * Use overlay as example based on SPIE publications

8 ASML Scanners at the core of patterning control capability Slide 8 25.April ASML scanners measure 100% of the wafers ASML scanners knobs control every die 100% of the wafers are measured Wafers processed field by field

9 Metrology aspects Slide 9 25.April. 2017

10 ASML Holistic Lithography approach seeks to maximize patterning process performance and control Slide April Lithography scanner with advanced capability (Imaging, overlay and focus) Process Window Enhancement Process Window Control 3 2 Computational Lithography Full chip process window detection Metrology

11 YieldStar Optical Scatterometry System Overlay, Focus and CD measurement capability YieldStar Stand alone Measurem ent Overlay Signal type Target size ( µm 2 ) Primary application Pupil 40x160 Monitor wafer Dark field image 10x10 On Product l Slide April Integrated Pupil 40x40 Monitor wafer Focus Dark field image 10x10 On Product CD Pupil 40x40 5x5 Monitor & On Product

12 * Supported with LithoInsight (LIS) software and the off-tool Litho Computation Platform (LCP) wafer 2 wafer Applying scanner corrections needs holistic approach supporting* the setup & optimization of Overlay, Focus, Dose Process development Ramp HVM Slide 13 Scanner Performance 1 Metrology setup 2 Static process setup 3 Dynamic process setup 34 Process control & monitoring 5 YieldStar and Smash Metrology Overlay and Imaging On-Product Performance Reduce Impact of Variations Maintain Performance 1.7nm mdbo mdbf lot 2 lot CD SMASH XY machine 2 machine Matched machine overlay on all layouts Optimal metrology accuracy, precision and throughput Optimal correction models and sampling Reduce Lot-lot and Wafer-wafer variation Excursion control thru scanner, metro & process KPI monitoring

13 On-product overlay [m3s]] Improved Overlay performance with minimized sampling Logic example HOPC +CPE control Product/layer : Logic/FEOL Lot exposure via dedicate chuck on NXT:1970Ci Monitoring trend via POR layout Overlay measurement by multiple YS S-250 Performance measured on POR layout Slide hours ~ 2 month ~ 1 month POR control strategy : POR Sampling 557 pt /wfr ; 1wfr/ck Correction Model : HOPC3txty+iHOPC+Dynamic CPE LiS control Enabled LiS control Saturated LiS control strategy : SSO Sampling 200 pt/wfr ; 1wfr/ck (64% less than POR) LiS Estimation Model : 5 th order Correction Model : Same as POR model

14 Metrology Sampling Density Roadmap The number of metrology points needed is higher than physically practical! Slide April. 2017

15 correct Apply Emulated fingerprint Computational metrology Scanner with integrated YieldStar Stand-alone YieldStar Etcher YieldStar ARM-CD/OVL ADI metrology Scanner interface BMMO residuals AEI metrology measured wafer Product wafer (Waver level) corrections BMMO Comp. Metro ARM (LIS est.) Comp. Metro Focus & CD Focus ADI CD on device OVL ADI OVL on device OVL SPIE 2017: W. Tel, Efficient Hybrid metrology for focus, CD, and overlay YS-IM YS-IDM

16 Computational Overlay for LELE case Evaluation after 2 nd litho step Slide 17 Measured OVL Computational Overlay = etch+leveling+udbo Delta OVL map 80 pts μdbo Level sensor etcher monitoring 200 pts

17 Proof of principle CD l Slide 18 <Date> SPIE 2017: W. Tel, Efficient Hybrid metrology for focus, CD, and overlay

18 Confidential l Slide April. <Date> 2017

19 HVM Defect patterning defect predictions on 100% of wafer Simulated PW Hybrid process modulation map On Wafer Defect Prediction Slide April. February 2017 Predicted Defect Map Best focus map Depth of focus map + Validation FEM per HotSpot Note that (in this experiment) validation can only be done at the same sampling scale as verification plan Verification sampling plan On Wafer Defect Observation Advanced in-production hotspot prediction and monitoring with micro-topography, , SPIE Advanced Lithography, San Jose, CA, USA, Feb 28, 2017

20 Rate (%) Patterning Fidelity Monitoring verifies the predicted defects on wafer using E-beam CD metrology tools Established good correlation between dense focus map and measured pattern defects Slide April. February 2017 HDFM focus map Defect prediction Defect observation M3DR4 AI60L1R3_AI90L1R9 LMC19 Capture rate: Percentage of successfully (verified) predicted defect locations Advanced in-production hotspot prediction and monitoring with micro-topography, , SPIE Advanced Lithography, San Jose, CA, USA, Feb 28, 2017

21 Summary - The large number of knobs on the scanner allows correction for process variations both Intra- and Inter-field. l Slide April The metrology required to feed control loops for high frequency spatial and temporal process variations requires computational methods to create per-wafer high density metrology information - Combination of Scanner model, multiple metrology sources and computational modeling allows for defect prediction and in turn scanner model optimization.

22 Slide April Thank you! I would like to recognize the following ASML colleagues for their contributions: Wim Tel, Stefan Hunsche, Marinus Jochemsen, Leon Verstappen, Arie den Boef, Jan Mulkens, Martin Ebert

23 #User selectable litho corrections Overlay 3 orders of magnitude down¹ Overlay correctables 4 orders of magnitude up Slide 24 The future: extending Holistic approach High order corrections Process robust metrology, broad wavelength, polarization and multiple orders using marker reconstruction, Integrated metrology Computational litho and metrology optimization Dense on product sampling enabling litho control; lot-lot, wafer-wafer, on product Reference : Key note Metrology conference M vd Brink

24 On-product overlay [m3s]] Improved Overlay performance for Logic HOPC + CPE Logic example HOPC +CPE control : 23% average overlay improvement,64% less samples Product/layer : Logic/FEOL Lot exposure via dedicate chuck on NXT:1970Ci Monitoring trend via POR layout Overlay measurement by multiple YS S-250 Performance measured on POR layout Slide hours ~ 2 month ~ 1 month POR control strategy : POR Sampling 557 pt /wfr ; 1wfr/ck Correction Model : HOPC3txty+iHOPC+Dynamic CPE LiS control Enabled LiS control Saturated LiS control strategy : SSO Sampling 200 pt/wfr ; 1wfr/ck (64% less than POR) LiS Estimation Model : 5 th order Correction Model : Same as POR model

25 Proof of principle for Focus Confidential Slide 27 <Date>

26 Level Sensor: measures wafer height map h(x,y) Requirements: 1. Accuracy: nm-range 2. Available time: few seconds 3. Resolution: 2 2 mm 2 Concept: optical triangulation Light source grating (pitch P) grating detector P 2sin Slide November 2017 detector response measured height h wafer Wafer stage Height variations are caused by: 1. Wafer thickness variations 2. Layer thickness variations 3. Deformation (warp) due to processing

27 Solution: Interferometric alignment sensor ( SMASH ): measures the position of any target with 180 rotation symmetry Slide November 2017 j Ae X P -1 j Ae 1 X P +90 Image rotation prisms -90 (+1,-1) (+1,-1) detector 0 X 1 X laser 2 2 X A A cos 1 4 P is measured with a self-referencing interferometer X P wafer X 0 X 1 X 2 Wafer stage X

28 Confidential Slide 30 <Date>

29 Level Sensor and Alignment run in parallel with wafer exposure Slide November 2017

30 EUV extension roadmap introduction 55 WPH 125 WPH 145 WPH 185 WPH Overlay [nm] Slide 32 SPIE NXE:3300B NXE:3350B NXE:3400B 3 NXE:next <3 High NA <2 products under study More on high-na in talk of Alberto Pirati: