Computational Lithography

Transcription

1 Computational Lithography An EDA Perspective Frank Schellenberg, Ph.D. Mentor Graphics 22nm SEMATECH Workshop 5/15/2008

2 22nm Optical Lithography 22nm with λ = 193nm Wow! Several processing options Double Exposures (Resist Freezing) LELE Spacer Other 22nm 2 Workshop 5/15/2008

3 And, once you ve picked one, EDA tools can accommodate them all. 22nm 3 Workshop 5/15/2008

4 Thank you for your attention. 22nm 4 Workshop 5/15/2008

5 IC Design Flow Specification RTL Netlist Layout (wafer) Jobdeck Reticle Wafer Design Synthesis Place & Route Data Preparation Reticle Lithography Wafer Lithography 22nm 5 Workshop 5/15/2008

6 Double Exposure / Patterning Specification RTL Netlist Target Layout DRC Physical Verification Layout Layout RET/Decomposition Jobdeck Jobdeck Reticle Reticle Wafer Simulation Based Verification (Double Exposure/ Double Patterning) Fab: New Illuminators / New Processes 22nm 6 Workshop 5/15/2008

7 Physical Verification / RET / DFM tools manage the layout polygons It s just polygon data Matchmaking for polygons and simulation models Process rules and constraints come first; Layout processes follow Software can do anything you need. Don t put the cart before the horse. 22nm 7 Workshop 5/15/2008

8 22nm Options K1 < 0.25 Limitation on pitch, not linewidth Some kind of complex patterning needed for critical layers Double Exposure (Resist Freezing, PSM, ) L+L E Double Patterning LELE Spacer Technology One line becomes two Self-Assembly Grow your own circuit! 22nm 8 Workshop 5/15/2008

9 22nm Options K1 < 0.25 Limitation on pitch, not linewidth Some kind of complex patterning needed for critical layers Double Exposure (Resist Freezing, PSM, ) L+L E Double Patterning LELE????? Spacer Technology One line becomes two Self-Assembly Grow your own circuit! 22nm 9 Workshop 5/15/2008

10 Spacer Technology Graphics: IMEC Process decisions Process rules Cell Library Design in pairs Simulation of variations Process models more complex Linewidth not defined lithographically OPC Same technology New models Custom Illumination Same technology I do not expect widespread adoption for general logic Memory, yes.. 22nm 10 Workshop 5/15/2008

11 Spacer for Memory Cell design by hand Spacer lines in pairs For us, they re just polygons Proceed as normal Might need process models Translate a single line into a pair With variation Possible in software today Generate the process, we can make the corresponding rules 22nm 11 Workshop 5/15/2008

12 22nm Options K1 < 0.25 Limitation on pitch, not linewidth Some kind of complex patterning needed for critical layers Double Exposure (Resist Freezing, PSM, ) L+L E Double Patterning LELE????? Spacer Technology One line becomes two Self-Assembly Grow your own circuit! 22nm 12 Workshop 5/15/2008

13 DE / DP Checklist Process decisions Process rules Layout parsing Definition of layers Separation rules Simulation of variations DP = Single Exposure Failure locations Alignment & Overlay OPC DP = Single Exposure DE like altpsm Custom Illumination Mix & match exposure 22nm 13 Workshop 5/15/2008

14 DE / DP Checklist Process decisions Graphics: IMEC Process rules Layout parsing Definition of layers Separation rules Simulation of variations DP = Single Exposure Failure locations Alignment & Overlay OPC DP = Single Exposure Double Exposure - PSM Custom Illumination Mix & match exposure 22nm 14 Workshop 5/15/2008

15 Design Rules Double Design Rules Depends entirely on the process Double Exposure (PSM rules) Interdigitation spacing Printable Assist Features (PrAF) Depends entirely on the user and what their process supports RDR at 22nm can be good for patterning Making gratings, then trimming them. Tela PDF Fabbrix but not a thrill for designers. 22nm 15 Workshop 5/15/2008

16 DE / DP Checklist Process decisions Process rules Layout parsing Definition of layers Separation rules Simulation of variations DP = Single Exposure Failure locations Alignment & Overlay OPC DP = Single Exposure Double Exposure - PSM Custom Illumination Mix & match exposure 22nm 16 Workshop 5/15/2008

17 Double Patterning Grey Mask A Blue Mask B Light blue Decomposition directive Graph to define connections between polygons Look for odd cycles Define cut locations 22nm 17 Workshop 5/15/2008

18 DP Compliance Check on Contacts Odd cycle => design change needed Red Decomposition directive Green Native conflict 22nm 18 Workshop 5/15/2008

19 Decomposition with 1D Cut 1D cuts Grey Mask A Purple Mask B Light blue Decomposition directive Orange Violated Decomposition directive 22nm 19 Workshop 5/15/2008

20 DE / DP Checklist Process decisions Process rules Layout parsing Definition of layers Separation rules Simulation of variations DP = Single Exposure Failure locations Alignment & Overlay OPC DP = Single Exposure Double Exposure - PSM Custom Illumination Mix & match exposure 22nm 20 Workshop 5/15/2008

21 3D Mask Topology Simulation MaskSim generates the mask transmission real and imaginary components using finite difference time domain (FDTD) 22nm 21 Workshop 5/15/2008

22 Jones Pupil Matrix Calculates Polarization Effects Accounts for the transmission loss of the projection lens due to oblique aberrations For hyper-na (NA>1) exposure systems 22nm Workshop 5/15/2008

23 Extending Simulation Process Window OPC PW Failure with acceptable nominal condition OPC Optimized OPC correction to prevent PW failure 22nm 23 Workshop 5/15/2008

24 Process Simulation Models for processing EM Mask model Polarization effects Especially at higher NA Process Window models Model Calibration Contour prediction Managing RET with a contour database 22nm 24 Workshop 5/15/2008

25 Hot Spot Detection M. Simmons, J.M. Brunet, S.W. Paek, Y.K. Kim, System to Improve RET-OPC Production by Dynamic Design Coverage Using Sign-Off Litho Simulator Proc. SPIE 6925, 69250X, (2008) 22nm 25 Workshop 5/15/2008

26 Litho Hotspot Enhancement Original Repaired 22nm 26 Workshop 5/15/2008

27 Power/Leakage variability Transistor CD variation Max Variability Band Min 22nm 27 Workshop 5/15/2008

28 Parametric side-benefit: Timing Original Cell [RET] Defocus [nm] Defocus [nm] Normalized Dose Optimized Cell [RET] Normalized Dose Arrival Time [ns] Arrival Time [ns] Signal Arrival time [ns] TT Signal Arrival time [ns] Defocus [nm] TT Dose The optimized cell performs within spec even under larger process variability conditions. Dose nm 28 Workshop 5/15/2008

29 Overlay Compensation Example Decomposed target Image without overlay error Image with overlay error Red: Mask 1 Blue: Mask 2 Green: Image contour after OPC Red/Blue overlap is created for overlay compensation by overlay_comp <value> 22nm 29 Workshop 5/15/2008

30 DE / DP Checklist Process decisions Process rules Layout parsing Definition of layers Separation rules Simulation of variations DP = Single Exposure Failure locations Alignment & Overlay OPC DP = Single Exposure Double Exposure - PSM Custom Illumination Mix & match exposure 22nm 30 Workshop 5/15/2008

31 Sparse to Dense 45nm dense Dense simulation introduced to OPC with 45nm products 22nm 31 Workshop 5/15/2008

32 Sparse / Dense Sparse Dense Dense is Contour based Some advantages, some disadvantages 22nm 32 Workshop 5/15/2008

33 Contour based OPC With Site-Based OPC With Dense OPC (nmopc) Typical poly layer Gate region Gate length active_layer enabled Contour based OPC allows more complex functions Gate CD Prioritization 22nm 33 Workshop 5/15/2008

34 PIXbar approach Overlapping Process window for contact dense logic design Total EL (%) no_sraf ortho octa DOF (nm) 22nm 34 Workshop 5/15/2008

35 Chromeless Lithography Y. Granik, N. Cobb and D. Medvedev, Extreme Mask Corrections: Technology and Benefits Proc. SPIE 6924, 69243W, (2008) 22nm 35 Workshop 5/15/2008

36 DE / DP Checklist Process decisions Process rules Layout parsing Definition of layers Separation rules Simulation of variations DP = Single Exposure Failure locations Alignment & Overlay OPC DP = Single Exposure Double Exposure - PSM Custom Illumination Mix & match exposure 22nm 36 Workshop 5/15/2008

37 Source / Mask Optimization a) b) c) d) Y. Granik, Source optimization for image fidelity and throughput, J. Microlith., Microfab, Microsyst. 3, 509 (2004). 22nm 37 Workshop 5/15/2008

38 Illumination Source / Mask Optimization (SMO) Mathematics of co-optimization developed Constraints of mask Constraints of source DOE RDR for the wafer Can mix and match Different source for each exposure 22nm 38 Workshop 5/15/2008

39 22nm OPC Several Options Classical extension: Same edge motions Inverse masks: much more complex Chromeless masks: very complex Data Volume issues Mask writer resolution 22nm 39 Workshop 5/15/2008

40 RET Double Patterning Checklist Process decisions Process rules Layout parsing Definition of layers Separation rules Simulation of variations DP = Single Exposure Failure locations Alignment & Overlay OPC DP = Single Exposure Double Exposure - PSM Custom Illumination Mix & match exposure 22nm 40 Workshop 5/15/2008

41 Computation Parallel processing for runtime acceleration Additional blades in a network Additional cores on a processor Job division depends on task But generally, more is faster 22nm 41 Workshop 5/15/2008

42 Computation Higher level Design Heirarchy of cells Parallel threads / cell based distribution OPC Image simulation using FFTs Contour generation need a lot of images Ideal for Cell BE processor Parallel system of parallel systems Fractured (flat) data Tiling for parallel processing 22nm 42 Workshop 5/15/2008

43 Cell BE Processor Architecture 22nm 43 Workshop 5/15/2008

44 Data volume Single layers approaching 300 GB We just ran a tape-out on a 22nm prototype Typical transmission BER error per Gb 8 errors per GB 2400 errors per file File shipped on hard drive Consequences for some technologies Maskless data verification 22nm 44 Workshop 5/15/2008

45 Conclusions Double Patterning is a process decision And it has some advantages and tradeoffs DP will be implemented at the RET/MDP step EDA tools for RET/MDP exist to execute all the required functions Parallel processing required Come up with a process; EDA tools can manipulate the (many) polygons. See your EDA supplier for specifics 22nm 45 Workshop 5/15/2008

46 So, once you ve picked a solution, EDA tools can accommodate them all. 22nm 46 Workshop 5/15/2008

47 Acknowledgments Mentor Graphics J.M. Brunet Nick Cobb Yuri Granik Juan Rey Andres Torres Alex Tritchkov James Word IMEC Mercury Computer Jim McKibbin Tessera N. America Marc Himel UC Berkeley Prof. Andy Neureuther IMPACT program UC San Diego Prof. Andrew Kahng 22nm 47 Workshop 5/15/2008

48 Thank you for your attention. 22nm 48 Workshop 5/15/2008

49 22nm 49 Workshop 5/15/2008

50 Why Cell BE? Supercomputer on a chip; network on a chip 1 Power PC + 8 Synergistic Processing Elements Unique architecture for image processing Standard device architectural platform Software programmable for rapid implementation Calibre OPC simulations using FFT s are ideally suited for this processing platform > 80% OPC run time consumed in simulation 15x to 30x acceleration of simulation component of OPC 22nm 50 Workshop 5/15/2008

51 Two Approaches for Hybrid Compute Farm GPP & CPA physically distinct Can be individually optimized GPP CPA bandwidth lower Loosely Coupled Hybrid CF GPP & CPA physically inseparable GPP CPA bandwidth high Tightly Coupled Hybrid CF SCF Supplier Master GPP Remote GPP Remote GPP Remote Ethernet Ethernet CPA Supplier CPA CPA CPA System Supplier Master GPP Remote CPA GPP Remote CPA GPP Remote CPA Ethernet Application SW Supplier Application SW Application SW 22nm 51 Workshop 5/15/2008