Design of Mixed-Signal Microsystems in Nanometer CMOS

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1 Design of Mixed-Signal Microsystems in Nanometer CMOS Carl Grace Lawrence Berkeley National Laboratory August 2, 2012 DOE BES Neutron and Photon Detector Workshop

Introduction Common themes in emerging detector requirements: Need to

decreased system footprint, severe cost constraints Integrated mixed-signal

increase in readout channels (for Mpixel square sensor) Conventional CCD

2 Introduction Common themes in emerging detector requirements: Need to capture dynamic processes More channels, higher speed, lower power/channel, decreased system footprint, severe cost constraints Integrated mixed-signal readout a must Example: Fast soft X-ray cameras over last 10 years 1000X increase in readout channels (for Mpixel square sensor) Conventional CCD Today (FCCD) Tomorrow (cp-ccd) Integrated readout required to deal with huge amounts of data 2

3 Why nanometer CMOS? Increased transistor density Enables increased channel/pixel count and new functionality New, more SUBTITLE digital centric HERE IF approaches NECESSARY to design possible Vastly improved performance Lower power for a given level of functionality SMALLER, FASTER, CHEAPER Cheaper on a functionality basis Performance Figure of Merit g m /I * f t Nanometer CMOS is an enabling technology for future imaging and particle detection systems 3

4 Opportunities and Challenges K. Kundert Mentor Graphics Design Rules multiplying as processes shrink Current design techniques inappropriate for system-level mixed-signal ASICs 4

5 IC Development Infrastructure Software Infrastructure Design entry (schematic and physical layout design) Simulation (analog, digital, mixed -mode) Synthesis Automatic Place-and-Route DRC/LVS verification FPGA firmware development environment Board development suite Test framework, instrument control Design-space exploration (MATLAB or similar) Required Team Competencies Transistor-level analog and mixed -signal design Digital RTL development Physical Design and Verification System-level Validation Analog/Digital co-simulation Behavioral Modeling Project management Board-level circuit design FPGA firmware development Teststand software development Advanced test execution and debug Designing a nanometer mixed-signal ASIC requires a competent and experienced team The days of debugging a chip with an oscilloscope and a function generator are over 5

Platform-Based Design Most readout systems look broadly similar A platform can embody these commonalities Individual readout ICs are instances of the common platform Dramatic improvements in design

6 Platform-Based Design Most readout systems look broadly similar A platform can embody these commonalities Individual readout ICs are instances of the common platform Dramatic improvements in design productivity and tractability Enables small teams to complete projects that would be impossible using an ad-hoc approach Sow once Reap many times Each new chip is a platform instance instead of a scratch design A. Sangiovanni Vincentelli, UC Berkeley Leads directly to improved top-down design methodologies 6

7 Platform-Based Design Platform is an integrated system designed for modification and extensibility Choose flexible macros for reuse e.g. use Pipelined ADC over SAR Process, block interfaces, and characteristics standardized e.g. 65nm CMOS, pitch matching, electrical interfaces, biasing requirements Platform includes set of pin-accurate functional models in Verilog-AMS Models allow rapid development of platform instances Verilog Verilog-AMS Verilog-A Verilog-AMS allows full system simulation (analog + digital) Enables digital-centric design approach lower cost and higher performance 7

8 Analog Challenges in Nanometer CMOS Low supply voltage Low device gain Analog design is hard! But cheap and fast transistors B. Murmann, Stanford University Leverage cheap digital circuits to assist analog circuits 8

9 Logic Energy over Time 500nm 350nm 250nm 180nm ~1000x 130nm 90nm 65nm 32nm B. Murmann, Stanford University 9

10 ADCs versus Logic in 1997/1998 B. Murmann, Stanford University 10

11 ADCs versus Logic in 1997/1998 Digital assistance affordable only for high-resolution ΔΣ (decimation filtering) B. Murmann, Stanford University 11

12 ADCs versus Logic in 2012 ~100x ~1000x B. Murmann, Stanford University 12

13 ADCs versus Logic in 2012 ~100x ~1000x Today, it is feasible to use digital signal processing to assist moderate resolution ADCs B. Murmann, Stanford University 13

14 Digital-Centric System Design (optical comms) 155 Mb/s data rate 10 Gb/s data rate K. Kundert Challenging analog design requires large design team and multiple silicon spins Well-understood digital circuits can compensate for analog shortcomings Agazzi, et al ISSCC Digital-centric design has vastly improved system performance, functional on first silicon 50X performance improvement due to digital-centric design 14

15 HIPPO: High-Speed Image Pre-Processor with Oversampling 16-channel prototype fabricated in

16 HIPPO Platform in 65nm CMOS Front end specific to initial application: Column-Parallel CCD readout for soft X-rays Back end more general for signal acquisition and data conversion Functional blocks developed with standard interfaces and Verilog-AMS models to allow accelerated redeployment 16

17 Digital-Centric HIPPO Platform Payoff HIPPO ADC designed for good noise performance with relaxed linearity Result to be presented at NSS 2012 Low-accuracy analog system plus digital assistance = high-accuracy mixed-signal system 17

POM an instance of the HIPPO platform Mu2e: experiment

Decays Mu2e tracker - Fermilab 21,600 gas-filled straws.

Example of BES-supported platform development enabling

18 POM an instance of the HIPPO platform Mu2e: experiment to observe neutinoless muon decay Processor of Muon Decays Mu2e tracker - Fermilab 21,600 gas-filled straws. Each straw has dedicated channel of electronics. Example of BES-supported platform development enabling accelerated development of high-performance readout IC for HEP 18

19 Frequency POM Behavioral Simulation (enabled by Platform-Based Design methodology) TDC electron hits (midstraw) More Bin Frequency TDC electron hits (edge of longest straw) More Functional circuit blocks modeled with Verilog-AMS Input straw pulses provided by FNAL using GARFIELD System-level simulation conducted before detailed design THIS IS TOP-DOWN DESIGN Bin Spreading due to dispersion in straw model 19

20 POM Design Reuse BLOCK REUSE Block Development time reduction ADC Core structure adapted from silicon-proven HIPPO. 80% Modified to lower power and area. Shaper Silicon-proven op amp architecture ported from 50% HIPPO. S2DIFF S2DIFF architecture adapted from Multiplying DAC circuit used in HIPPO ADC. 80% LVDS Masterbias Silicon-proven LVDS driver and receiver from HIPPO reused in POM. Silicon-proven current bias generation and distribution block from HIPPO reused in POM. Silicon-proven, radiation-tolerant configuration register from HIPPO reused in POM. 100% 95% Configuration 95% Register Standard Cells Standard cell library used in HIPPO reused in POM. 100% Pads Pad library used in HIPPO reused in POM. 75% (estimate) Digital Backend Experience gained in HIPPO synthesis and place-androute cycle greatly reduced development time. 80% 20

21 Design Reuse example Pipelined ADC HIPPO ADC (2011): 12-bit, 80 MSPS, 50 mw POM ADC (2012): 8-bit, 65 MSPS, 3 mw 80% shorter development time due to HIPPO platform 21

The Virtuous Circle of Platform-Based Design Refinements made to POM ADC and improved digital expertise will be directly applied to HIPPO 2, a planned 128-channel readout IC to

22 The Virtuous Circle of Platform-Based Design Refinements made to POM ADC and improved digital expertise will be directly applied to HIPPO 2, a planned 128-channel readout IC to instrument cp-ccd image sensors. Platform-based design allows each project to be used as a springboard to improve the performance and lower the cost of the next project HIPPO POM HIPPO 2 22

23 Platform-Based Design as enabling technology Highly leveraged from HIPPO development POM would have required severe compromises in functionality or performance without Platform-Based Design 23

24 Conclusion Science requirements demand increases in detector channel count and performance To meet these needs we need readout ICs that are: Platform-Based Digital Centric Developed using a top-down methodology These are enabling technologies. They represent an industry-proven path to improve the productivity and reach of existing design teams Development costs can be spread across projects and application domains for maximum impact 24

Digital Systems Design

Digital Systems Design Digital Systems Design and Test Dr. D. J. Jackson Lecture 1-1 Introduction Traditional digital design Manual process of designing and capturing circuits Schematic entry System-level