Imaging for the next decade

Transcription

1 Imaging for the next decade Martin van den Brink Executive Vice President Products & Technology IMEC Technology Forum June, 2009 Slide 1

2 Congratulations! ASML and years of making chips better Slide 2

3 20 years jointly pushing litho technology transitions /50 /60 /200 /70 / nm /300 /750 AT750 / nm /1100 /1100 MSVII 157 nm XT1250i XT nm immersion XT1700i XT1900i The World s first exposure IMEC a-tool: ADT EUVL NXE3100 Slide 3

4 Agenda Litho strategy Litho equipment Extension of immersion through holistic lithography Double patterning Computational lithography supporting litho performance High productive metrology for litho control EUV Slide 4

5 Shrink continues Lithography keeps adding value (based on the average of multiple customers update april 09) 200 Logic / SRAM Resolution/half pitch, "Shrink" [nm] DRAM NAND Flash Logic NAND 6 Transistor SRAM Cell k ~ 0.44 DRAM k ~ 0.35 k ~ /1/15 1/1/14 1/1/13 1/1/12 1/1/11 1/1/10 1/1/09 1/1/08 1/1/07 1/1/06 1/1/05 1/1/04 1/1/03 1/1/02 * Note: Process development 1.5 ~ 2 years in advance updated 4/09 Slide 5 Year of production start*

6 Shrink appetite has been accelerated for NAND Based on moving 5 years average forecast from -1 to 4 yrs 22% 20% NAND R 2 = % Moore s Law Yearly shrink rate 16% 14% 12% Logic DRAM R 2 = R 2 = % Jan-02 Jan-03 Jan-04 Jan-05 Jan-06 Jan-07 Jan-08 Jan-09 Year of production start* * Note: Process development 1.5 ~ 2 years in advance updated 04/09 Slide 6

7 Likely lithographic options k 1 = (half-pitch) * numerical aperture / wavelength Most likely Opportunity Unlikely Half pitch (nm) Year λ (nm) NA Double patterning: CoO challange Infrastructure challenge 1.35 Low k 1 challenge With 248 nm 68 nm L&S With 193 nm DPT 22 nm L&S With EUV, 28 nm L&S Slide 7

8 The world of lithography equipment Photo-lithography fastest and most cost-effective chip production method 1, DVDs/s 100 DVDs/s 1000 DVDs/s T e r r a I n c o g n i t a Legend Markets > 1000M/yr Throughput [m 2 /hour] DVDs/s 1/10 DVDs/s I C L i t h o g r a p h y W a t e r s Non-critical applications i-line KrF ArF, ArFi EUV Imprint M/yr M/yr Market Scope Pixel rate in DVDs/second 1 DVD = 8.5 GB 0.1 E-beam M a s k M a k i n g IC Masks µm 3 µm 1 µm 300 nm 100 nm 30 nm 10 nm Resolution Slide 8

9 Agenda Litho strategy Litho equipment Extension of immersion through holistic lithography Double patterning Computational lithography supporting litho performance High productive metrology for litho control EUV Slide 9

10 ASML Immersion Product Roadmap Available XT:1900Gi Resolution 40 nm Tool CDU < 1.5 nm SMO 6/5 nm Throughput 131/140 WPH 65 defects (ASML PDT) Available XT:1950Hi Resolution 38 nm CDU (3σ) < 1.1 nm SMO 4 nm Throughput 148 WPH 20 defects (ASML PDT) Q NXT:1950i Resolution 38 nm CDU (3σ) < 1.1 nm SMO 3 nm Throughput 175 WPH 10 defects (ASML PDT) Q NXT:1950i +PEP Resolution 38 nm CDU (3σ) < 1.1 nm SMO 3 nm Throughput 200 WPH 10 defects (ASML PDT) Performance enhancements 1) Improved overlay using segmented wafer table 2) Improved optics 1950 lens 3) Improved productivity/defectivity using new immersion hood 4) Faster stages Platform enhancements 1) New high-acceleration stages 2) Improved overlay using New stage position control Platform enhancements 1) Platform evolutionary field upgradeable performance Slide 10

11 Total defects 3x lower with new immersion hood 600mm/sec. scan-speed, 45 nm patterned defect test, TCX041 top-coat 80 Current IH defects < 65 /wafer New IH defects < 20 /wafer Immersion specific Printed particles Total defects per wafer Micro sieve 0 w1 w3 w5 w7 w9 w2 w4 w6 w8 w10 Wafer Not linked with track KLA2800 metrology Slide 11

12 NXT wafer stage metrology impact on overlay Current stage metrology Current stage metrology Interferometer Interferometer 300 mm 300 mm stage stage Overlay [nm, 99.7%] Y- coordinate X-coordinate Overlay: < 4 nm System [#] (ArF 0.93NA) Improved metrology Grid plate <15 mm stage Overlay [nm, 99.7%] Overlay: < 2 nm Wafer [#] (prototype) Slide 12

13 Dual stages: maximize throughput & measurement time TWINSCAN delivers both throughput and performance Squeezed Sequential sequential operation operation swap measure step time scan time wafer measurement time is minimal! TWINSCAN NXT dual stage metrology operation chuck swap wafer metrology focus + align 80 pairs step time wafer exposure operation scan time 1. Overlay performance - metrology corrects wafer grid 2. High throughput - increased acceleration - chuck swap without H-bar - chuck swap without closing disk Time needed to expose a single 300mm wafer Slide 13

14 NXT + Fast allignment: SMASH GridAlign Improved overlay & maximum throughput On Product Overlay M+3S [nm] scheme robust for grid deformations 6 parameters model REDUCE Noice of process effects Number of alignment mark pairs MEASURED OVERLAY zone alignment (30 mm) radius minimum for 6 parameters typical usage NXT:1950i + SMASH NXT:1950i minimum for zone alignment % expected usage Number of alignment mark pairs THROUGHPUT Throughput [%] Slide 14

15 ASML system throughput roadmap drives CoO ATP throughput [WPH] Wavelength Wafer size EUV 150 mm stepper Immersion ArF KrF i-line g-line 200 mm stepper 150 mm 200 mm 300 mm 200 mm scanner Year of introduction 300 mm NXT 300 mm AT & XT EUV ADT XT:1900Gi EUV NXE Source: ASML Slide 15

16 Agenda Litho strategy Litho equipment Extension of immersion through holistic lithography Double patterning Computational lithography supporting litho performance High productive metrology for litho control EUV Slide 16

17 Holistic litho: low k1 application specific imaging enable Scanner tuning knobs DoseMapper for optimum CD Uniformity Correction Mask Enhanced Computational Lithography Mask OPC/RET Optimization GridMapper for minimizing Overlay grid residuals ImageTuner for Application specific lens setup Free form DOE/Flexible illuminator for Application specific illumination optimization Holistic lithography is the Application Improved integration Productivity, specific of wafer recipe i.e. lithography, Overlay Dose Mapper and computational Critical Recipe Dimension lithography Uniformity and metrology (CDU) to deliver Data improved productivity, Faster Recipe overlay and Application ramp up and critical dimension specific improved uniformity metrology (CDU) yield Metrology control loops Baseliner for Twinscan stability, matching and set-up + = Source -mask optimization Freeform illuminator/mask Pattern Matcher for consistency across installed base Slide 17

18 Agenda Litho strategy Litho equipment Extension of immersion through holistic lithography Double patterning Computational lithography supporting litho performance High productive metrology for litho control EUV Slide 18

19 Options to print below immersion single exposure limit Cost, complexity and cycle time *Wafer does not leave the exposure system between the two exposures *Wafer preferably does not leave the litho cell between the exposures Single exposure SE 45 nm *Wafer leaves litho cell for etch between the exposures Spacer DPT SPCR 32 nm Litho DPT - LELE LDPT 32 nm Litho DPT - LFLE LDPF 32 nm Double exposure DE 38 nm SiON /HM Etch Clean Strip Film Etch Metrology Develop Expose Top coat Resist BARC SiON / SiC Hard Mask Device film Si Slide 19

20 Litho double patterning introduction in 2009 Supported by NXT: high productivity and superior overlay First exposure Etch 32 nm Lines/96 nm Spaces Second exposure Final CD < 10% CD Etch 32 nm Lines/32 nm Spaces Slide 20

21 Spacer Double Patterning Side view Top view First exposure First exposure Sacrificial Spacer making Second exposure Trimming lines Etch Final CD < 10%CD Third exposure Larger features (e.g. landing pads) Slide 21

22 Double patterning requires better and more lithography Litho exposure equipment parameter as percentage of CD Single exposure Litho double patterning Spacer double patterning ΔCD 7% 3.5% 3% Overlay (depending on DFM) 20% 7% 7-20%* # mask steps # process steps relative to single exposure Application 2D, all 2D, all 1D, mainly memory * Depending on the amount of Design For Manufacturing effort Slide 22

23 Overlay requirements are about to accelerate Litho overlay [nm] DRAM - 4F2 DRAM - 6F2 NAND-ReRAM NAND Logic Process node [nm] Limit of double patterning Slide 23

24 Agenda Litho strategy Litho equipment Extension of immersion through holistic lithography Double patterning Computational lithography supporting litho performance High productive metrology for litho control EUV Slide 24

25 Prediction Capabilities of Lithography Models The Only Relevant Definition of Model Accuracy Process window prediction Prediction accuracy Fitting accuracy Prediction accuracy Pattern prediction Scanner Optics extrapolation Prediction accuracy Slide 25

26 Predictive Modeling Requirements Calibration Prediction With limited gauges For real layouts E E With limited process conditions F For the entire process window F Slide 26

27 Super-FEM Calibration Methodology dose Model calibration conditions focus illumination Slide 27

28 Model Extrapolation Feasibility Prediction accuracy for detuned illuminator settings RMS(CD_model-CD_wafer) over 7 FEM conditions base model fit fitting rms (reference) extrapolation rms 1.6 rms (nm) NA1.2, Ann 0.9/0.64 NA1.1, Ann 0.9/0.64 NA1.15, A 0.95/0.69 NA1.15, A 0.85/0.59 NA1.15, Quasar MODEL FIT MODEL EXTRAPOLATION Extrapolation accuracy allows OPC/Verification model calibration per process layer with illuminator tuning trough extrapolation per device Slide 28

29 Existing Model-Based Scattering Bar Placement Flow SRAF Guidance Map (SGM) used in sequential SMO Calculate the two dimensional cost function map Place scattering bars at the optimum positions of the map Run clean-up algorithm to satisfy MRC constraints OPC is applied only to the main target patterns Exposure Rule Focus Scattering bars are placed based on the SGM mapping Scatter bar placement does not change during OPC Scatter bar size can only decrease to satisfy MRC and OPC constraints Slide 29

30 Free form co-optimized source-mask optimization Co-Optimization of all mask features with the source Calculate the two dimensional cost function map Place scattering bar seeds at the optimum positions of the map Expand the seeds to form scattering bars as part of the OPC processing (co-optimization) Exposure Rule Focus Initial placement of scattering bars is determined base on cost function map Main pattern OPC and scattering bar size and placement are co-optimized Scatter bar size and placement maximize the process window Slide 30

31 Free-form co-optimized source-mask optimization Improved process window using Tachyon SMO Depth of 6% Exposure Latitiude Depth of Focus (nm) Sequential SMO Tachyon SMO Co-Optimization 4x node DRAM Contact layer XT:1900i, 1.35NA 6% AttPSM k1 < Standard Standard Parametric Free-form DOE DOE DOE DOE Slide 31

32 Pattern Matcher full chip improves factory matching & yield 2D structure matching impacts factory yield FullChip targets baseline targets Source: TSMC; Chi-Yuan Shih et al, SPIE 2009 Slide 32

33 Agenda Litho strategy Litho equipment Extension of immersion through holistic lithography Double patterning Computational lithography supporting litho performance High productive metrology for litho control EUV Slide 33

34 Spacer litho control improves wafer CDU measurements of final 32 nm L/S using angular resolved scatterometry Uncontrolled S 1 S 2 L 1 L 2 S 1 3σ=3.92 S 2 3σ=3.46 3σ S 1 -S 2 = σ L1,L2=2.12 Controlled S 2 3σ=2.74 S 1 3σ=2.1 3σ S 1 -S 2 = σ L1,L2=1.99 SPIE Slide 34

35 Agenda Litho strategy Litho equipment Extension of immersion through holistic lithography Double patterning Computational lithography supporting litho performance High productive metrology for litho control EUV Slide 35

36 Hynix: EUV is more cost effective at >30 wph Source: Hynix, SPIE 2009 Slide 36

37 Blank defect for memory compatible with R&D requirements (data scaled around actual measured defect size 50nm) defects/wafer Asahi Glas Hoya Today DRAM/Flash Logic ok ~50x Data Source: Sematech, Sapporo 2007 Slide 37

38 Complete source integration achieved in Q2/09 year integrated hardware perfomance Test Bench Data Prototype Pilot H2/07 H1/08 H2/08 Q1/09 Q2/09 H2/09 vacuum system yes yes yes yes yes yes collector none none 1.6sr 5sr 5sr 5sr debris mitigation none none yes yes yes yes dose control none none none none 7.5% <1.5% burst length [ms] power level [W] duration [hrs] < >24 Now shipped to ASML power level demonstration [W] Slide 38

39 EUVL roadmap: a single multi-generation platform For different optics suitable down to 16 nm Res nm NXE: 3XX0 0.4 x NA 16 nm 22 nm NXE: 3350 NXE: 3300 same projection system, enhanced off-axis illumination 0.32 NA +off axis illumination, >180 wph 0.32 NA, 3 nm OVL, >150 wph* 27 nm NXE: NA, 4 nm OVL, wph* ADT 0.25 NA, 8 nm OVL *At 10 mj/cm² preparation implementation volume production Targeted first shipment Q210 Slide 39

40 Extendibility of EUV down to sub 5 nm possible increasing apertures up to 0.7, wavelength reduction down to 6.8 nm using 13nm compatible optics Resolution, Depth of focus [nm] Slide Year k-factor, Aperture Resolution DOF@13 nm DOF@6.8nm k-factor@13nm Aperture@13nm k-factor@6.8nm Aperture@6.8nm

41 NXE Throughput vs Dose vs Power Roadmap 200 Throughput (WPH) NXE: nm, 200 W, 2012 NXE: nm, 200 W, 2011 NXE: nm, 100 W, 2010 Current best EUV resist dose range NXE: nm, >400W, Exposure Dose (mj/cm ) Intel, Lake Tahoe 30 nm hp, 8.7mJ SPIE/Lake Tahoe 22 nm hp, <20mJ Slide 41

42 EUV Model-Based proximity and flare OPC Improvements in CD Statistics for 32 nm Poly Layer Count CD Error for 32nm Horizontal Lines 7.E+05 Correction No Correction 6.E+05 5.E+05 4.E+05 3.E+05 2.E+05 1.E+05 0.E CD Error (nm) Correction for proximity and flare effects results in: centering distribution at CD error=0 reducing std dev by 4X from to nm 0.25 NA, 0.5 sigma annular, 10 nm resist blur CD measurements made at every 5 nm along all horizontal gates OPE & Flare correction Orientation Measurement Count Mean (nm) Maximum CD (nm) Minimum CD (nm) Std Dev (nm) Mean Error + 3s (nm) Horizontal 32nm Horizontal 32nm No 1,059, (-1.63) (6.56%) Yes 1,059, (+0.01) (0.45%) Slide 42

43 Summary 25 years cooperation between IMEC and ASML facilitated a continuous shrink in semiconductors scaling its volume and applications 193 nm extensions down to 20 nm half pitch using double patterning requires: > 200 W/hr, < 4nm overlay and tight CD control litho Holistic approach optimizing mask and litho equipment facilitating fast ramp up and higher yield EUV is the cost effective successor of 193 nm below 20 nm With shrinking capability well below 10 nm at lower cost than double pattering Transparent transition to EUV possible using calibrated computational litho Slide 43

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