EUV is progressing towards production

Transcription

1 ASML s customer magazine 211 Summer Edition EUV is progressing towards production NXT:195i makes 22-nm processing possible, cost effective Integrated metrology maximizes on-product performance

2 Editor s note 4 Enhancing the TWINSCAN NXT for 22-nm production 8 Gaining hands-on EUV experience 12 Integrated metrology: full speed ahead to better overlay 16 Enabling 22 nm Logic No de with Adanced RET Solutions 2 The Russian semiconductor revolution images Colofon Editorial Board Lucas van Grinsven, Peter Jenkins Managing Editor Ryan Young Contributing Writers Matthew McLaren, Ron Schuurhuis, Stuart Young, Keith Gronlund, Frank Driessen, Bernardo Kastrup, Henk Niesing, Angelique Nachtwein, Hans Bakker, Kaustuve Bhattacharyya, Arie den Boef and Rutger Voets Circulation Emily Leung, Michael Pullen, Shirley Wijtman For more information, please see: 211, ASML Holding BV ASML, ASM Lithography, TWINSCAN, PAS 55, PAS 5, SA 52, ATHENA, QUASAR, IRIS, ILIAS, FOCAL, Micralign, Micrascan, 3DAlign, 2DStitching, 3DMetrology, Brion Technologies, LithoServer, LithoGuide, Scattering Bars, LithoCruiser, Tachyon 2., Tachyon RDI, Tachyon LMC, Tachyon OPC+, LithoCool, AGILE, ImageTuner, EFESE, Feature Scan, T-ReCS and the ASML logo are trademarks of ASML Holding N.V. or of affiliate companies. The trademarks may be used either alone or in combination with a further product designation. Starlith, AERIAL, and AERIAL II are trademarks of Carl Zeiss. TEL is a trademark of Tokyo Electron Limited. Sun, Sun Microsystems, the Sun Logo, iforce, Solaris, and the Java logo are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. Bayon is a trademark of Kureha Chemical Industry Co. Ltd. Nothing in this publication is intended to make representations with regard to whether any trademark is registered or to suggest that any sign other than those mentioned should not be considered to be a trademark of ASML or of any third party. ASML lithography systems are Class 1 laser products. 2

3 ASML Images, Summer Edition 211 Editor s note Optical lithography is dead. By Ryan Young, Senior Manager Communications How many times, and for how long have we heard that? I know that personally I ve been hearing it since the industry was trying to break through.25μm imaging. Yet here we are today preparing for 22nm resolutions more than 1 times smaller. It s amazing what we ve been able to do as an industry, following Moore s Law to ever smaller feature sizes. ASML is proud to have played a part and remains committed to shrink as the best way to provide the most value to you, our customers. Today, we continue the shrink roadmap by enabling double patterning on our advanced immersion systems, as well as by introducing a shorter wavelength through our EUV program. Even so, due to today s increased complexity and imaging budgets of just a few nanometers, your yield and productivity are under constant pressure and we therefore strive to continuously expand ASML s holistic lithography portfolio with new hardware and software to optimize, validate and verify your designs while also monitoring and adjusting manufacturing operations in real time. Our Eclipse program is here for you to make this brave new world as straightforward as possible with the simple aim to deliver to you more good chips at smaller nodes. In this edition of Images, you can read about how our NXT immersion platform is being enhanced for cost-effective double-patterning by increasing productivity above 2 wafers per hour, while also improving imaging and overlay. We also provide an update on EUV, as multiple NXE:31 systems have now been installed at customer fabs and are imaging wafers. IC manufacturers are now starting work on process development and integration. In addition, NXE:33 systems are in development with module manufacturing already in progress. Holistic Lithography continues to gain interest as geometries shrink and more fine-tuning becomes required to maintain yields. At ASML, we are developing more methods to achieve this fine-tuning, at the pre-reticle phase before manufacturing, as well as during production. One such method before manufacturing involves Reticle Enhancement Techniques (RET). Read more about this method in our article on recent work with STMicroelectronics on 22nm logic nodes with advanced RET. Other techniques leverage scanner adjustments during manufacturing, which require fast and accurate measurements of actual wafer imaging, and that means advanced metrology. ASML s YieldStar metrology system provides the data required for better on-product overlay, CDU and focus, and does so efficiently, without compromising productivity. Another way to look at the ongoing life of optical lithography is through emerging markets. We usually think of emerging markets in terms of technology, for example gyroscopes for smartphones and tablets or micro-mirrors for projections systems, but there are geographic regions that are emerging as well. One such emerging market is Russia. We feature a story in this edition about the Russian semiconductor industry and the many interesting things that are taking place there. Optical lithography is very much alive and growing. Regards, Ryan Young 3

4 Enhancing the TWINSCAN NXT for 22-nm production By Angelique Nachtwein, Ron Schuurhuis and Stefan Weichselbaum, Product Managers 1% throughput increase with PEP High Dose wph 2wph 18wph 23wph PEP NXT:195i 125shots ATP PEP High Dose PEP NXT:195i 96shots FF Throughput of ATP layout job increases with 1% for NXT:195i + PEP NXT:195i when PEP High Dose is installed Graphs are indicative only. Throughput estimations for customer recipes can be made with simulation by CS-ABS Fig 1 Abstract In keeping with our philosophy of maximizing value of ownership for customers through system enhancements, ASML is releasing a number of upgrade options for the TWINSCAN NXT:195i. These options improve system overlay, imaging and productivity performance, allowing the NXT:195i to be used for cost-effective production at the 22-nm half-pitch node. ASML has always aimed to maximize value of ownership for our customers. We do that through scanners that provide an outstanding combination of performance and productivity, and through system enhancement packages that extend the economic lifetime of those scanners and improve output from your installed base. These system enhancements help you get the highest possible return on your investment in lithography equipment. will improve the system s imaging, overlay and throughput performance. Productivity means profitability Maximizing your output is the key to maximizing your return on investment. This is particularly true if you are employing double patterning techniques. Consequently, we are releasing two new Productivity Enhancement Packages (PEP) to boost throughput on the NXT:195i. In 29, we introduced the NXT:195i. This ultra-precise, ultra-high-throughput ArF immersion lithography system was designed to target the 32-nm half-pitch node and provides throughput up to 175 wafers per hour (wph) under ATP conditions or 19 wph under full field conditions. Now in 211, we are releasing a number of system enhancement options that will allow you to use the NXT:195i to manufacture 22-nm half-pitch layers profitably and at high yields. These options, which are either already available or will become available in the next few months, The first of these, PEP High Dose, is already available. For standard NXT:195i systems, the highest dose that can be delivered at maximum scan speed is 3 mj/cm 2. However, around 3% of layers exposed on immersion systems require higher doses and so, currently, have to be exposed at lower throughputs. Ongoing improvements to the optical components of our systems have increased the maximum transmission levels. PEP High Dose is a software-only upgrade that lets you exploit this higher transmission to increase the light intensity 4

5 ASML Images, Summer Edition 211 at wafer level at the same laser power level. It increases the critical dose to 45 mj/cm 2, allowing you to expose more layers at the maximum scan speed. And for layers that require doses of 45 mj/cm 2 or higher, PEP High Dose improves throughput by around 1% (Figure 1). In beta testing, the actual throughput gain was 7% at 125 shots and 12% at 96 shots. PEP High Dose is fully compatible with our second productivity enhancement, PEP NXT. Due for release in Q1 212, PEP NXT is a major upgrade that aims to improve throughput by 15-2% at similar or even improved overlay, imaging and focus performance. The upgrade includes wider reticle clamps to support higher accelerations. As a result, once PEP NXT is installed, the system only supports pellicles up to 115 mm. However, this covers most pellicles used today and the Pellicle Safeguard feature ensures wider pellicles are not loaded, preventing damage to the machine and pellicle. 5 wafers per day within reach for an immersion system PEP NXT also features a faster metrology cycle while delivering the same quality of data. A new, stiffer position module has a higher bandwidth to improve dynamics plus thermal behavior. In addition, PEP NXT introduces a new immersion hood that helps improve dynamic behavior and enables faster scan speeds without affecting defectivity levels. The new hood has the same recommended contact angle as previous versions (75 ). In addition, with PEP NXT, ASML is introducing four new edge speed optimization (ESO) modes. Together with a number of other improvements in PEP NXT, these new features push TWINSCAN NXT:195i system throughput from 175 to 2 wph at 125 exposures. At 96 exposures, the gain is even larger, with throughput rising from 19 to 23 wph. This puts the 5 wafers per day (wpd) milestone within reach for an immersion system. TOP Reticle Control PEP High Dose and PEP NXT are the next products in our ongoing productivity roadmap. This roadmap increases throughput by around 1% each year. These increases will help make manufacturing at advanced nodes more cost-effective. However higher throughput can have an impact in other areas of the scanner. For instance, it can lead to heating of the reticle, particularly in layers such as contact layers that use high doses and low transmission reticles. This is exactly the issue the TOP Reticle Control option is designed to address. Reticle heating causes the reticle to expand which in turn reduces on-product, intrafield overlay performance. The exact amount of reticle heating and hence overlay penalty is very dependent on the specific process. However, 5

6 analyses carried out by ASML suggest that intrafield overlay is becoming one of the largest contributions to on-product overlay. Consequently, addressing intrafield overlay factors such as reticle heating is vital for 22-nm production. TOP RC beta test results are much better than spec XT:195Hi Intrafield Overlay drift without TOP RC Intrafield Overlay drift with TOP RC TOP Reticle Control features a new sensor that measures the reticle s temperature profile throughout its first production lot. The system then predicts the resulting thermal expansion per shot and calculates feed-forward corrections to lens and stage parameters. These corrections are then applied as part of your exposure recipe for all subsequent lots. To ensure the accuracy of the corrections, TOP Reticle Control checks the reticle s thermal profile once per batch. Fig 2 1% x: 2.2 nm y: 6.5 nm 5 nm Overlay Improvement measured in resist: 2.6 nm (Spec > 1.5 nm) (Last 2 wafer First 2 wafer) of a lot Overlay measured to nominal 2.6 nm Improvement (Spec > 1.5 nm) FlexWave increases LH correction potential by a factor >2 More than sufficient to support the throughput roadmap 1% x: 1.6 nm y: 3.9 nm 5 nm TOP Reticle Control is already available as a field upgrade for the NXT:195i (a version for the TWINSCAN XT:195i is also available and a version for the XT:19i will be released in Q3) and is specified to improve intrafield overlay by 1.5 nm under ATP conditions. In beta testing under standard ATP test condition, it performed significantly better than specifications achieving intrafield overlay improvements of 2.6 nm (Figure 2). The actual overlay benefit in production could be higher or lower depending on the specific use case. Fig 3 Throughput [wph] Throughput Throughput roadmap increase ~1.1x per year year Ratio residual aberration for standard configuration vs FlexWave FlexWave Lens Heating correction potential improvement w.r.t. standard lens ~3.5 X 5 X 4 X 3 X 2 X 1 X dipx35 dipy35 memory 4x/2x nm 1.35NA hexapole dipx NA dipx35 1.2NA DRAM DRAM 4x nm 3x nm 1.35 NA 1.2/1.35 NA 7 LH use case simulations roadmap requires 2 X dipx35 dipy35 NAND 3x nm 1.2NA FlexWave improves imaging and overlay Finally, FlexWave is a highly flexible lens control option that helps improve your onproduct overlay and imaging performance. Already discussed in the previous issue of Images, FlexWave is now available to order. It features an optical element positioned close to the pupil plane of the projection lens and improved lens control, including much higher-order aberration terms that extend the Zernike series expansion up to 64 terms. This allows you to correct for aberration offset during production. In short, FlexWave lets you create almost any wavefront you want in your system s projection optics. It can be used in three ways. First, it can reduce the aberration fingerprint of the projection optics, bringing you closer to the theoretical FlexWave could increase the system s ability to correct for lens heating by at least a factor of two perfect lens. Second, it can reduce lens These predictions were validated in heating effects. Third, it can compensate recent experiments carried out at a for so-called 3D mask effects. customer site on an NXT:195i at full productivity. FlexWave was shown As with reticle heating, lens heating to improve through-lot Zernike rootmean-square (RMS), through-lot critical effects become ever more significant as throughput increases. A 1% increase dimension (CD) stability and through-lot in throughput will lead to a similar-sized on-product overlay by more than a factor increase in lens heating. Our simulations of two (Figures 4 and 5). This level of suggest that, in typical memory performance exceeds our throughput manufacturing use cases, FlexWave roadmap, ensuring customers can run the could increase the system s ability to NXT:195i at higher throughputs without correct for lens heating by at least a affecting overlay and CDU performance. factor of two compared to a standard lens (Figure 3). Similarly, experimental results have proven FlexWave s ability to compensate 6

7 ASML Images, Summer Edition 211 Fig 4 Through lot lens RMS result improves by a factor >2 Measured on NXT195i at full productivity Exposure conditions: One lot of 25 FEM wafers dip3y rotated, 1.35 NA, reticle transmission 25%, 24.4 mj/cm 2 Relative CD [nm] Through lot CD stability improves by a factor >2 Measured on NXT195i at full productivity Exposure conditions: One lot of 25 FEM wafers dip3y rotated, 1.35 NA, reticle transmission 25%, 24.4 mj/cm Residual lens RMS [nm] Z5-25 spher. comax comay ASThv AST45 3foilX 3foilY 4foilX 4foilY LH improvement through FlexWave 2.5 X 2.6 X 1.5 X 3.4 X 2.5 X 1.7 X 2.1 X 1.4 X 2.8 X 2.3 X No Center of array line space structure Grouped Zernike RMS Standard FlexWave Wafer no. Relative CD [nm] End of line space structure, end is not tied to any other structure (last minus first wafer, max over field) Sensitive to AST45 and 4foilX No Wafer no. CD [nm] Standard FlexWave Yes Periphery structure, large trench Wafer no. Source: Micron.8 nm 1.9 nm Source: Micron for 3D mask effects. Such effects, which arise when trying to image features that are smaller than the wavelength of light used, can result in reduced process windows. In experiments based on a typical NAND Flash pattern, FlexWave improved the Best Focus shift by 15 nm and CD asymmetry by.5 nm (Figure 6). In both cases, this was an improvement of about 4%. These improvements were achieved by optimizing over a limited set of features. An evaluation based on full chip design is ongoing. However, this initial result strongly suggests that FlexWave allows you to maximize the process window for a variety of pitches, orientations and feature sizes, improving your yield of good wafers. All together for 22-nm These system enhancements will be supported by a new release of our TWINSCAN software, available in the fall of 211. Together, they ensure the NXT:195i has the performance necessary for production at the 22-nm half-pitch node with the productivity levels needed for cost-effective operations and a rapid return on investment. Fig 5 Best Focus 15 nm, CD asymmetry.5 nm improvement Experimental optimization Best Focus shift CD asymmetry Best Focus [nm] 4 BF shift [nm] 2 1 Uncorrected Corrected anchor pitch 34 nm 2 nm SG WL1 WL2 WL7 SP SP1 CD asymmetry [nm] SG WL1 WL2 WL7 H45P9 H45P112.5 H45P135 H45P27 H45P315 V9P27 V9P27 CD asymmetry T-B [nm] nm.9 nm [nm] 2 34 nm 1.3 nm Both 4 BF shift [nm] nm CD asymmetry T-B [nm] nm Fig 6 7

8 Gaining hands-on EUV e By Rudy Peeters and Stuart Young, Senior Product Managers EUV Abstract EUV lithography is moving from research centers into manufacturing fabs. ASML has now delivered four NXE:31 EUV lithography scanners to customers and these systems have been used to expose thousands of wafers. Performance validation tests have proven the imaging and overlay capabilities of the NXE:31. Meanwhile, ASML is helping customers develop EUV optimized on-product performance through our Eclipse program. 8

9 ASML Images, Summer Edition nm lines that were printed with large process windows xperience Extreme ultraviolet (EUV) lithography is progressing towards production. Systems are being delivered to customers, and wafers are being produced. Process knowledge developed on ASML alpha demo tools (ADTs) located at imec in Leuven, Belgium, and CSNE in Albany, USA is now being transferred to the semiconductor fab. And chip makers are starting work on EUV process integration. In the last issues of Images, we announced that the first of our TWINSCAN NXE:31 systems had been shipped to a customer as planned. Three more systems have subsequently been delivered to customer sites and the final two NXE:31 systems are expected to ship in the coming months. Last December saw the first ever exposure of a wafer on an EUV scanner at a manufacturing site. Since then, the number of EUV wafers exposed has accelerated, and thousands of wafers have now been exposed on the four delivered NXE:31s. However, experience of the TWINSCAN NXE platform isn t limited to those customers that ordered and have taken delivery of an NXE:31. Many customers have visited our site in Veldhoven to run 9

10 imaging demonstrations. The feedback from these demonstrations has been highly positive. Customers have been pleased with the quality and range of demonstrations they can run, and the insight this has given them for developing their own EUV processes. Improving performance Designed for process development, the NXE:31 is an NA =.25 scanner with a specified resolution of 27 nm. It features a.8σ that is capable of providing both conventional and off-axis illumination. The NXE:31 has a specified throughput of 6 wafers per hour (wph). Source roadmaps have been aligned and work is currently underway to reach the full specified productivity. With all six planned systems built, the NXE:31 is showing excellent performance. Flare levels have been verified in resist to be below 5% and full-field illumination uniformity is better than 1.2%. See Fig. 1 The NXE:31 can reach its resolution specification with conventional illumination. Switch to off-axis illumination, and the imaging capabilities can be pushed much further. For example, Figure 2 shows 22 nm lines that were printed with large process windows (depth of focus (DOF) around 2 nm and an approximately 12% exposure latitude. Process windows of this size promise robust, high-yield manufacturing processes. Fig 1 Fig 2 Fig 3 NXE:31 lenses within flare specifications [%] 27 CD (nm) proto ~15 22nm DoF ~2nm, EL ~12% Focus Offset (mm) dipole-6, inorganic negative tone resist in collaboration with IMEC Flare below 2. µm Flare below 2. µm (variation over field) NXE:31 large process windows for 22nm and 18nm resolution capability shown 13.mJ 14.5mJ 16.mJ CD (nm) NA=.25, 75deg dipole, Resist dose ~15mJ/cm 2 SEVR14 SB/PEB : 15 C/95 C 21p42 2p4 19p38 18p36 Even this isn t the limit for the NXE:31. Dense lines have been imaged at resolutions down to 18 nm using off-axis dipole illumination and inorganic resists. See Fig. 3 Of course, resolution and large process windows aren t the only scanner performance factors necessary for high-yield processes. Critical dimension uniformity (CDU) and overlay are important too. ATP: 27nm CDU full wafer and intrafield specifications met Mean CD = σ = 1.5nm, spec is 2nm Mean CD = σ = 1.nm, spec is 1.8nm Single exposure processes require full-wafer CDU that is around 6% of the 1 Fig 4 Process - 5nm SPUR-V2 : Developer TMAH +DIW Rinse : Dose 12mj/cm²

11 ASML Images, Summer Edition 211 EUV to dry 193 Overlay measured at 6.5 nm Dedicated chuck Overlay 3.7 nm MMO: NXE 31 to XT145 NXE 31 chuck dedication Single Chuck Overlay, 2 wafe, ATP filtered 15 nm 99.7%F 1 nm X: 6.5 nm y: 5.9 nm 4 wafers: (x:6.5,y:5.9) 2 wafers: (x: 1.8,y:3.7) 99.7%F X: 1.8 nm y: 3.7 nm Standard system calibration, 99.7% fields, 9 Fig 5 Thousands of wafers have now been exposed on the delivered NXE:31s resolution. For the 27-nm half-pitch node that means a CDU of around 1.6 nm is needed. In initial tests, the NXE:31 demonstrated full-wafer CDU of less than 2 nm. This could be further improved through the use of optical proximity correction (OPC). See Fig. 4 The NXE:31 s overlay specifications are 4 nm for dedicated chuck overlay (DCO) and 7 nm for matched machine overlay (MMO). During performance validation, the system performed better than specification on both counts with a DCO of 3.5 nm and an MMO of 6.5 nm. For MMO validation, the NXE:31 was referenced to wafers exposed on a dry TWINSCAN XT:14 to ensure both interfield and intrafield contributions were considered. See Fig. 5 The next generation With NXE:31 systems already in customers hands and exposing wafers, work is continuing on the next generation of EUV lithography systems: the NXE:33B. While the NXE:31 is designed for process development and R&D, the NXE:33B targets volume production at the 22-nm half-pitch node. Our optics partner, Carl Zeiss SMT AG, began making the mirror-based projection lenses for the NXE:33B last year. Improvements in polishing and coating technologies have enabled the NA of these lenses to be increased from the original planned.32 to.33. This change has minimal effect on the resolution but it does increase the pupil surface or system etendue by 6%, ensuring more EUV power can be transmitted to the wafer. The first hardware for the NXE:33B has been delivered to our dedicated EUV facilities in Veldhoven. This hardware is the so-called bottom module, which includes the wafer stage and handler, and the reticle stage and handler. The modules are currently undergoing testing which puts the NXE:33B on course for its scheduled delivery in 212. Looking towards production The delivery and performance of the NXE:31 and the development work on the NXE:33B show EUV lithography s continued progression. IC manufacturers can now start work on process development and integration. ASML is already helping customers with this through Eclipse. Eclipse is our systematic structure to promote cooperation between ASML and our customers and to reduce R&D cycles, accelerate ramp up and improve yield. We are setting up Eclipse programs with a variety of customers to address customer-specific issues and support on-product optimization. These programs are tailor-made to suit each customer, and designed to help them move EUV lithography into production faster. 11

12 Integrated met full speed ahea By Kaustuve Bhattacharyya, Senior Product Manager for Metrology, and Stefan Keij, Product Devel Abstract The need for better on-product overlay, CDU and focus while producing more wafers per day is driving metrology into the litho cluster. To maximize value, integrated metrology must operate at the same speed as the litho cluster and deliver sub-nanometer precision. ASML s unique YieldStar T-2 3-in-1 integrated metrology tool is the only solution available today that makes that possible. Compact, fast and accurate, it helps you maximize on-product performance and minimize overall cycle time. 12

13 ASML Images, Summer Edition 211 rology: d to better overlay opment Manager Producing wafers economically at ever smaller feature sizes creates increasingly rigorous demands for on-product performance parameters such as overlay, critical dimension uniformity (CDU) and focus control. Continuously improving scanner performance helps to meet these requirements, but there are additional contributors to overall performance, including the mask. Metrology and process variations can also be significant. For example, recent studies suggest that process variations typically account for around 5% of the total on-product overlay budget. These variations, which arise in steps such as etching, chemicalmechanical planarization (CMP) and deposition, introduce a considerable amount of unpredictability into the process. To overcome this, IC manufacturers use offline metrology tools to measure a subset of features on a subset of wafers in a batch. They then calculate process correction based on those measurements. The accuracy of these corrections can be improved by increasing the metrology sampling density; measuring more features on more wafers in more batches of each lot. As feature sizes shrink and overlay, CDU and focus requirements become tighter, metrology sampling densities will rise from 2 points per lot to around 8. Total overlay measurement uncertainty below.25 nm 13

14 Residual.X, nm Raw Overlay (nm, m+3s) More wafers are measured, the higher the potential of improving overlay control >.5nm overlay residual improvement Dec 3 Residual.X Each data point contains 1 combinations of wafer selection Dec number of Wafers.75nm Residual.Y, nm 2 4 Residual.Y number of Wafers KH Chen, K. Bhattacharyya et. al., SPIE Advanced Lithography KH Chen, K. Bhattacharyya et. al., SPIE Advanced Lithography, 211 Using Exponentially Weighted Moving Average, (EWMA) feedback, more data added in time scale, overlay improved Uncorrected overlay Dec 31 Jan 2 Jan 5 Jan 1 X Y Jan 11 Raw Overlay (nm, m+3s) Dec 3 Corrected overlay with EWMA Dec 3 Dec 31 Jan 2 Jan 5 Jan 1 X Y Jan 11.5nm Source: TSMC Source: TSMC Yet the metrology-to-litho turnaround time for offline metrology can be as long as the time taken to expose ten lots. So the last wafer in a run may have already been exposed before the first corrections are available. Consequently, manufacturers usually devise metrology strategies that balance the demands of cycle time and on-product performance. Often this means measuring only two or three wafers per lot. But there is an alternative that eliminates the compromise. By moving metrology into the litho cluster, integrated metrology reduces metrology cycle times and delays. Wafers don t need to be removed from the production line. Instead they can be measured as soon as they are processed. This allows you to measure more wafers and update your Exponentially Weighted Moving Average (EWMA) feedback for APC more frequently. It also enables you to generate useful corrections faster, allowing you to improve on-product performance on short-run products as well. KH Chen, K. Bhattacharyya et. al., SPIE Advanced Lithography, 211 Measure practically every wafer YieldStar T-2 specifications Overlay TMU <.25 nm CD precision <.25 nm Throughput (under ATP conditions) > 2 wafers per hour The right tool for the job Integrated metrology requires tools capable of delivering precise and accurate results fast. Currently, ASML s YieldStar T-2 is the only tool available that fits the bill. YieldStar is a unique 3-in-1 metrology platform that measure overlay, CDU and focus in a single wafer pass. It is capable of making thousands of measurements per hour with proven sub-nanometer precision and accuracy. Speed? Performance? Or both? However, using offline metrology means wafers have to be removed from the processing line and transferred to standalone metrology tools. That takes time. And the higher your sampling density, the more time it takes slowing down your production cycle. Metrology cycle times can be a particular problem for foundries who often manufacture products in short runs of around ten lots. Advanced process control demands a fast turnaround time for metrology, so that process corrections can be fed back to the scanner in time to expose subsequent wafers of the same product. It can deliver that unrivalled combination of performance, flexibility and speed because it is the only scatterometrybased metrology system to make use of higher diffraction orders, and because it employs extremely advanced wafer stage technology. That means YieldStar systems can operate with the same throughput and precision as our scanners. 14

15 ASML Images, Summer Edition 211 What s more, the T-2 has a very small footprint, allowing it to fit easily into existing track set ups and space-limited fabs. Yet it is built using the same modular platform as the standalone YieldStar tools (S-2 systems): this means there is no compromise in performance with T-2 compare to S-2 systems. This also enables an optional capability to simply convert a standalone system into an integrated metrology module and vice versa depending on the fab s need. In tests at a customer site, the T-2 demonstrated total overlay measurement uncertainty below.25 nm for a variety of product layers. The same tests showed that the tools performance remained extremely stable when monitored over a period of many months. Optimizing metrology When incorporated into your litho clusters, the T-2 s combination of speed and performance lets you optimize your post-patterning metrology strategy simultaneously for overlay and throughput. You can sample wafers more densely, and you can measure practically every wafer. This allows you to build up more data for your EWMA fast, enabling further accuracy in overlay feedback control. Integrated metrology also greatly reduces your metrology-to-litho turnaround time. This is particularly true for the YieldStar T-2 because it measures overlay, CDU and focus in one go. You don t have to move the wafer from tool to tool to build up a full set of metrology data. If you are measuring all three quantities, turnaround time for offline metrology can be 2-5 hours. With the T-2, turnaround time is less than fifteen minutes. For an average product with 4 layers, this equates to a total cycle time reduction of 1.25 days if you monitor 25% of your layers and 5 days if you monitor all the layers. What s more you can achieve these cycle time savings while collecting twice as much metrology data. 15

16 Enabling 22 nm Logic No Advanced RET Solutions Vincent Farys, Emek Yesilada, Nassima Zeggaoui and Clovis Alleaume - STMicroelectronics, Yorick Trouiller - LETI, Laurent Depre, Vincent Arnoux and HuaYu Liu - Brion Technologies, Jo Finders - ASML (a) (b) Litho1 (c) Etch1 Litho1 Litho2 Figure 1 Splitting comparison for Metal jog structure with 1st litho on the left and 2 nd litho on the right; a) double patterning with LELE scheme, b) Sidewall Image Transfer 1 st decomposition (SIT1), c) Sidewall Image Transfer 2 nd decomposition (SIT2) Litho2 Etch2 Figure 2 Process flow for a double patterning scheme based on Litho-Etch-Litho-Etch (LELE) process Abstract The 22 nm technology node presents challenges as state of the art scanners are limited to a numerical aperture of Thus we cannot simply apply a shrink factor from the previous node, and tradeoffs have to be found between Design Rules (DR), Process integration and RET solutions. Patterning Back End Of Line (BOEL) layers with sufficient process window (PW) is challenging as these need to be performed by double patterning technique coupled with advanced OPC solutions. This article is a comparison between possible double patterning solutions: Pitch Splitting (PS) and Sidewall Image Transfer (SIT) and their implication on design rules and CD Uniformity. Advanced OPC solutions such as Model Based SRAF and Source Mask Optimization are also investigated in order to ensure good process control. The highly regulated design rules on Gate layers at the 32 nm and 22 nm logic nodes induce an increase of design complexity on contact and metal trench patterning, with 9 nm and 64 nm pitch lines respectively nm wavelength immersion litho with an NA of 1.35 implies a theoretical resolution limit of 71 nm (with 8 nm in practice), which demonstrates that 22 nm logic nodes are below the resolution limit, therefore requiring some form of double patterning scheme. Double Dipole Lithography (DDL) is rejected because this method is applicable only on features above the resolution limit 2, 3. DDL cannot print trenches below 6 nm without a chemical shrink 4 which is cost-prohibitive. The only viable solutions for patterning sub-resolution trench layers are pitch splitting with tone inversion or self-aligned double patterning. We will compare two decomposition types: Litho Etch Litho Etch (LELE) with negative tone developer (NTD), and Sidewall Image Transfer (SIT) with spacer on resist as described in Figure 1 in the case of Metal X (Mx) jog structure (32 nm lines with 6 nm gaps). 16

17 ASML Images, Summer Edition 211 de with Litho1 Litho1 Spacer (+ resist strip) Spacer (+ resist strip) Litho2 Litho2 Etch Etch (a) (b) Figure 3 Process flow for a double patterning scheme based on SIT process flow (LithoSpacer-Litho-Etch); a) SIT1 decomposition type, b) SIT2 alternate decomposition type. Figure 4 Edge-based CD uniformity calculation method. CD variability (3σ) from each edge are independently taken into account and then recombined to determine the final CDU (3σ) between edges e1 and e2 LELE (Figure 1.a) appears to be the simplest in terms of pattern decomposition as you only have to split the pitch. SIT involves indirect decompositions with the first lithographic step used to define the structure supporting spacer deposition and the second for extra features removal. One particularity of the SIT process is that there are two possible ways to pattern the 1 st lithographic step as shown in Figures 1.b and 1.c. This is due to the fact that the half pitch lines are derived from the 1 st lithographic step after spacer deposition process and as such the half pitch lines can be reversed. Double Patterning Process Flow The number of process steps increases with double patterning and an illustration for LELE with five steps is shown above left in Figure 2 with two consecutive litho-etch steps and one alignment step between the first and second exposures. On this figure we have reported the case of the Mx jog. Litho1 prints trenches in resist which are transferred to a hard mask by Etch 1. This is then repeated, after alignment, by Litho 2 and Etch 2. Figure 3 shows the four principal steps for SIT with both options for image decomposition shown (SIT1 and SIT2) where only the Litho1 step is different. The spacer primarily defines the half-pitch features, with the second mask being used to help define the metal line-end and the jog structure. Note in the examples shown LELE has rounded line ends, both SIT have clear-cut ends due to the second exposure and that both LELE and SIT1 have some risk of pinching on the horizontal line of the 2D shape which is minimized on SIT2. CD uniformity calculation Using an edge-based method to determine the CD uniformity takes into account the contribution of the 3σ variability from lithography and process step (etch, overlay, etc.). The CDU calculation for a gap between line-ends of two consecutive lithographic steps is described in Figure 4. The CDU (3σ) of the gap between edges e1 and e2 (gap e1-e2) is impacted by the 17

18 variability of litho and etch of each step as well as overlay. Applying this global CDU calculation to the three different double patterning methods we see the different gaps and CD s to be studied (Figure 5). This study compares 9 nm pitch (45 nm target CD) and a 64 nm pitch (32 nm target CD) with double patterning using rigorous simulation from Panoramic Technology. The results are represented as CDU (3σ) versus target as a percentage to allow comparison between the different patterning methods. Figure 6 shows the results for the Mx jog structure for Gap1, Gap2 and Line. Single exposure (SE) has uniform variability and as it is the equivalent step for LELE for Gap 1 this is also 9%. SIT performance for Gap 1 is better as resist CD control is easier than the gap between two trench-ends. (a) (b) (c) Figure 5 CD variability definition of both patterning steps for each decomposition style, a) LELE, b) SIT1 and c) SIT2 Gap 1 Gap 2 Line LELE 8% 12% 14% SIT 1 4% 12% 12% SIT 2 4% 11% 15% Gap 2 and Line show a 1.5x to 2.5x CDU degradation comparing SE to LELE and SIT which comes from the added process steps. For Line CDU with LELE and SIT1 the increase is almost exclusively due to lithography. These structures are super critical and the feature decomposition shown in Figure 1 shows that there are four different structures depending on the decomposition style used. Three structures are quite regular (Litho1 and Litho2 of LELE and Litho1 of SIT process) and one looking like random dots (Litho2 of SIT process). Source optimization (SO) performs best when optimizing periodic structures and model-based SRAF (MB-SRAF) for random dots when exploring if there are possible RET gains in the process window. RET improvement Brion s Tachyon Source-Mask Optimization (SMO) is used to co-optimize the scanner source and mask pattern simultaneously, based on Edge Placement Error (EPE) minimization 5. Tachyon SMO has been used to optimize the freeform source for various sets of structures in both vertical and horizontal orientations Figure 6 CD uniformity (3σ) calculation results for Mx 2D shape structure comparing single exposure, LELE, SIT1 and SIT2. through seven evaluation conditions between +/-4 nm defocus, +/-3% delta dose and +/-.5 nm mask error offsets. Figure 7 illustrates the different optimized source compared to an initial Quasar shape, and Figure 8 compares the Bossung curves (showing CD variations through focus and dose) of the original quasar and optimized source for SIT1 litho1 (7c) showing a significant improvement towards the goal of isofocal (curvature equal to zero) behavior. Figure 9 shows the scatter bar (SRAF) placement for the Litho 2 stage with both rule based and model based placement. Table 2 shows the CD variation (3σ) before and after RET optimization where CD 1 to CD 4 have been optimized using SMO and CD 5 to CD7 with MB-SRAF. CD 1, CD 2 and CD 4 are the super critical structures where variability has been improved from 1.5x to 2x. (a) CDU reference (3σ) CDU improvement (3σ) (b) (c) Figure 7 Source shape outputs after SO process for a) Litho1 of LELE, b) Litho2 of LELE and Litho1 of SIT2, c) Litho1 of SIT1. CD1 CD2 CD3 CD4 CD5 - CD7 8% 23% 18% 7% 4% 7% 14% 12% 5% 3% Table 2 CDU (3σ) for lithographic step before and after RET optimization 18

19 ASML Images, Summer Edition CD (nm) CD (nm) Focus (nm) Focus (nm) (a) (b) Figure 8 CD variations through dose and focus (Bossung curves) of the distance CD3 of the Litho1 of SIT1 process, a) for Quasar 3 [.85.97] XY polarization and b) for SO source and needs to be considered, such that it is preferable that the 2D shape be decomposed on the first lithographic step in the case of SIT, as this avoids including the spacer deposition in the overall CDU. The SIT technique offers the best CDU control with lower variability for line-end definition and 2D shapes compared to LELE process. (a) (b) Figure 9 SRAF placement for Litho2 of SIT process, a) Rule based placement, b) Model-based placement Acknowledgment The authors would like to thank all the partners of the Solid Nano 212 program and Nicolas Martin, field application engineer at Brion technology, for their help on MB-SRAF solution. Gap 1 Gap 2 Line Single Exposure 9% 9% 9% LELE 9% 16% 24% SIT 1 5% 14% 19% SIT 2 5% 12% 16% Figure 1 CD uniformity (3σ) calculation results for Mx 2D shape structure in the case of LELE, SIT1 and SIT2 process flow Figure 1 shows the CDU impact to Gap1, patterning due to the increase of process Gap 2 and Line when we apply the above steps that consider multiple lithographic, RET techniques. It is significant to note etching, spacer deposition and overlay that the improvements to SIT2 due to contributions. Advanced RET solutions RET techniques is minimal as the CDU of such as source optimization and model this decomposition style is not driven by based SRAF, placement provide a path lithographic step. to overcome this problem by enhancing the lithographic performance and moving Conclusion the CD variation through dose and focus Double patterning is shown to have 2 ~ towards the isofocal. The decomposition 3x CDU degradation compared to single style is a key factor for CD process control References 1 ITRS roadmap, Links/21ITRS/Home21.htm 2 A-Y. Je et al., Model-based double dipole lithography for sub-3nm node device, Proc. SPIE 7823 (21) 3 J.C. Urbani et al., Characterization of inverse SRAF for active layer trenches on 45 nm node, Proc. SPIE 667 (27) 4 Y. Chen et al., Sub-2 nm trench patterning with a hybrid chemical shrink and SAFIER process, Proc. SPIE 7273 (29) 5 S. Hsu, An innovative Source-Mask co-optimization (SMO) method for extending low k1 imaging, Proc SPIE vol. 714 (28) 6 J. Finders et al., Dense lines created by spacer DPT scheme: process control by local dose adjustment using advanced scanner control, Proc. SPIE 7274 (29) 19

20 The Russian semiconductor revolution By Marcel Kemp, Director Europe Accounts, and Rutger Voets, Product Manager Abstract Russia isn t the first place people think of for semiconductors. But after years of limited investment, the Russian semiconductor industry is starting to blossom. ASML supports the growth of the Russian semiconductor industry by making advanced lithography systems available at cost-effective prices and through flexible customer support to meet the needs of customers of all sizes. In 1697, Tsar Peter the Great of Russia visited the Netherlands to study ship building. Over three hundred years later, the Russians are again looking for support and know-how in setting up a new industry. This time it s not ship building but chip building. But once more the Netherlands is playing a key role this time through ASML s lithography equipment. Russia may not be the first place you think of when it comes to semiconductors. Its industry is relatively small, accounting for less than 1% of the global market. But that market is growing. Andrei Golushko, Deputy Director General for marketing at JSC Mikron Russia s largest microelectronics company predicts the size of the Russian semiconductor market could rapidly increase ten-fold. This growth is in part driven by a government plan to modernize the nation s semiconductor industry. The main aim of the plan is to create an infrastructure that can fulfill the semiconductor requirements of the domestic microelectronics market a market that comprises some 15 million people. Key to the plan are Rusnano, a government-owned investment company that stimulates microelectronics developments in Russia, and the creation of free economic zones for electronics and related industries at Zelenograd, St. Petersburg, Kaliningrad region, Tomsk and Dubna. A lasting relationship ASML has been active in Russia since In the early days, our customers typically bought lithography equipment for R&D facilities. For example, in 21, we shipped a PAS 55/25C 2-mm i-line stepper to the Scientific Research Institute of System Analysis (SRISA) a government-funded R&D center in Moscow. Since then, we have supplied lithography systems to various Russian customers, and new potential lithography customers are appearing all the time. Many of these companies are transitioning to manufacturing or looking to expand their production capabilities. Typically, manufacturing lines are still based around 2-mm wafers and our shipments to Russia have been exclusively from our PAS 55 range, which covers i-line, KrF and ArF steppers and Step-and-Scan systems. For instance this year we will 2

21 ASML Images, Summer Edition 211 The Russian semiconductor market could rapidly increase ten-fold who produce surface acoustic wave (SAW) devices, and Ryazan Metal Ceramics Instrumentation Plant (RMCIP) who produce micro-electro-mechanical systems (MEMS). deliver a PAS 55/75F and PAS/115C to Sitronics-Nano for its manufacturing fab in Zelenograd. Many of the systems we ship to Russia were previously owned by customers in other regions. Once no longer required by the original owners, ASML refurbished them to meet the needs of new customers in Russia. This allowed our Russian customers to acquire the advanced lithography technology they needed for a lower investment. If the Russian industry is to achieve its goal of supporting its domestic microelectronics market, the volumes required will, in all likelihood, mean the creation of at least one 3-mm facility. This will likely spark a further increase in infrastructure investment, probably within the next few years. Market diversity The Russian semiconductor industry includes a few large players like Mikron. It also features a multitude of start-ups targeting niche markets, such as Avangard This makes the market place very diverse. In addition to MEMS and SAW devices, our Russian customers are active in a wide variety of market sectors. Example applications are smartcards and television set-top boxes. Such a varied lithography market means ASML has to address a wide variety of customer needs. R&D centers are looking for advanced technology, while the larger manufacturers productivity is the key decision factor. 21

22 Russian customers choose ASML Our Russian agent, ELINT SP, has because we lead the way in both these an intimate understanding of the areas, in terms of what our systems can Russian semiconductor industry, do and the customer support we can and the challenges faced by Russian provide. This allows us to offer complete manufacturers. This is invaluable for turnkey solutions, meeting customers matching customers with machines. specific requirements at the lowest cost We back up this relationship with expert and highest quality. technical support through our European Turnkey solutions meeting customer s specific requirements at the lowest cost and highest quality In this way, ASML has established customer service organization based a strong reputation in Russia. This is a in Veldhoven. Our customer support crucial factor in doing business in the engineers and account management country. The Russian semiconductor teams pay regular visits to established, community is still relatively small new and potential customers in Russia and close knit. So word of mouth is to ensure our lithography offering important. Most Russian semiconductor continues to meet their needs. manufacturers don t have import / export licenses which means business is usually These visits highlight how the relationship done through local agents making between Russian and non-russian an established reputation even more companies is evolving from client-supplier important. to true partnerships. To support this evolution, industry organizations such as SEMI are actively trying to promote the cross-border flow of information. Established in 1992, SEMI Russia has been organizing the annual SEMICON Russia tradeshow since The show has grown each year, with the 21 show attracting 11 exhibitors and 145 visitors. The 211 event which was held May 31 to June 2 was even larger and, for the first time, ran over three days to accommodate the increased traffic. Land of opportunity The planned modernization of the Russian manufacturing infrastructure promises big opportunities for companies throughout the semiconductor value chain. For equipment suppliers, it opens up a new market that is set to grow rapidly. Meanwhile, international chip manufacturers can look to build new partnerships and draw on the innovative chip design ideas the country generates. As the modernization plan takes hold and the country starts to create its own Silicon Valley and free economic zones, it really is an exciting time to be in Russia. 22

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