Nanometer Technologies: Where Design and Manufacturing Converge. Walden C. Rhines CHAIRMAN & CEO

Transcription

1 Nanometer Technologies: Where Design and Manufacturing Converge Walden C. Rhines CHAIRMAN & CEO

2 Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware of manufacturing challenges Resolution enhancement technology will proliferate Parallel processing, multi-threading and hierarchical analysis will be mandatory Design for Manufacturing will be a major EDA requirement New silicon modeling and analysis will be required Design for Manufacturing and Design for Test must merge 2

3 Resolution Enhancement Technology Will Delay the Need for New Lithographic Equipment ITRS, 1994, 1998,

4 Manufacturing Yields Will Be Driven by Physical Features Instead of Particles Product yield 100% Feature-limited yield Traditional defect-limited yield µm 0.5µm 0.35µm 0.25µm.18µm.13µm 90nm Courtesy PDF Solutions 4

5 New Failure Modes Will Drive New Test Methodologies EE Times Article: Failures plague 130-nanometer IC processes, By Ron Wilson, August 27, 2002 Void Migration Tearing Misalignment R R = 50 KΩ Additional delay of 250ps How do you test for it? 5

6 Physical Verification Moves From Design Rules to Design Guidelines 6

7 Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware of manufacturing challenges Resolution enhancement technology will proliferate Parallel processing, multi-threading and hierarchical analysis will be mandatory Design for Manufacturing will be a major EDA requirement New silicon modeling and analysis will be required Design for Manufacturing and Design for Test must merge 7

8 Growing Importance of RET 21 Increasing Number of Chip Layers With RET nm 180 nm 130 nm 90 nm 8

9 Resolution Enhancement Combines Different Approaches 9

10 Resolution Enhancement Will Require Optical Modeling 10

11 Immersion Lithography Can Extend Life of Current and Future Technology Process Technology 65nm Dry NA = 0.85 K 1 = 0.28 λ = nm Wet NA = 1.2 Process Node Lithography Technology, no immersion EUV* EUV Lithography Technology, with immersion wet 193 wet 193 wet# 157 wet *EUV: extreme ultra-violet lithography # with litho friendly design constraints - B. Lin, TSMC, 7/15/

12 Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware of manufacturing challenges Resolution enhancement technology will proliferate Parallel processing, multi-threading and hierarchical analysis will be mandatory Design for Manufacturing will be a major EDA requirement New silicon modeling and analysis will be required Design for Manufacturing and Design for Test must merge 12

13 Verification Rule Base Is Expanding Rule Count Explosion Data is not the only problem! Additional Metal Rules Rules with 3 metal layers Total DRC Rules RET and DFM requirements impose new DRC constraints SOC components require different checks % more checks per process Physical Verification Must Outpace Moore s Law! um 0.25um 0.18um 0.13um 0.09um

14 Mask Turnaround Time is Limiting Design Cycles Mask cycle time 6+ weeks 2-3 weeks data preparation and verification time at IDM 3-4 weeks manufacturing time for mask Data preparation for Variable Shaped Beam mask writing machines is complex and impacts mask writing time Data sample post RET and fracturing for VSB11 format (Toshiba) Advanced parallel processing is required to restore and maintain overnight data processing 14

15 Parallel Processing and Multi-Threading Will Be Mandatory 15

16 Hierarchy Preservation Enables Downstream Efficiency Hierarchy after OPC JEOL - Fracture time based on hierarchy of incoming data Relative File Size Relative CPU Time Active Layer Contact Layer Metal Layer Logic Metal Layers Active Layer Contact Layer Metal Layer Logic Metal Layers DB flattened Hierarchical output 16

17 Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware of manufacturing challenges Resolution enhancement technology will proliferate Parallel processing, multi-threading and hierarchical analysis will be mandatory Design for Manufacturing will be a major EDA requirement New silicon modeling and analysis will be required Design for Manufacturing and Design for Test must merge 17

18 Design Modifications to Enhance Yield Will Be Automated DRC Rules Check design compliance with process rules DFM Rules Identify layout issues which may limit yield Direct link to measured yields 18

19 Evaluation of Designs For Manufacturability Requires Statistical Analysis of the Design Software highlights an area that is a potential problem Visualize the appearance of circuit in silicon Calculate metrics based on evaluation of DFM rules # of transistors involved % of transistors that can be fixed Make suggestions of possible fixes Overlay Statistical Color Maps Pinpoint specific problems Via Check Adequate spacing to double 45% of single via instances. Display locations Make global change Find first instance Defect density at 85% 19

20 Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware of manufacturing challenges Resolution enhancement technology will proliferate Parallel processing, multi-threading and hierarchical analysis will be mandatory Design for Manufacturing will be a major EDA requirement New silicon modeling and analysis will be required Design for Manufacturing and Design for Test must merge 20

21 Nanometer Design Closure Requires Extensive Analysis Nanometer Analysis Requires Nanometer Silicon Modeling 21

22 New Processes Require New Parasitic Models Dual Damascene - trench etch profile, barrier/seed layer Lithography - Cu wire dimensions are not as drawn CMP - dishing, erosion lead to line thickness variation Result: Cu wire width and thickness becomes a function of Wire width and spacing Wire pattern density Wire topography Circuit Relevance: Interconnect Resistance Varies Across the Die! 22

23 Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware of manufacturing challenges Resolution enhancement technology will proliferate Parallel processing, multi-threading and hierarchical analysis will be mandatory Design for Manufacturing will be a major EDA requirement New silicon modeling and analysis will be required Design for Manufacturing and Design for Test must merge 23

24 Design for Test Will Change Dramatically 180 nm New fault models 130 nm At speed test Test/physical correlation 90 nm 24

25 New Fault Models Drive Increased Test Requirements P.D. Agnello, Nov Nigh, IBM, ITC 01 Resistive open Resistive via 25

26 At-Speed Testing Will Increase Requires 3X-5X pattern volume 10X-100X pattern compression and tester throughput Fabless Forum March 2003 at-speed Embedded Test Compression compressed stuck-at test at 26

27 Embedded Deterministic Test Increases Patterns and Tester Throughput 10X-100X Without Design Methodology Change D E C O M P R E S S O R C O M P A C T O R Compressed Stimuli stimuli ATE Compacted Responses responses No Change to ATE Interface 27

28 ATPG s X Discontinuity A 1,146K B 4,441K C 10,344K D 2,835K E 4,086K F 13,254K V NEW Time[ks ks] Time[ks ks] Improvement Ratios 15.2X 22.4X 13.7X 6.8X 10.9X 3.7X Average 12X Performance Improvement V Patterns 2,889 8,857 28,000 11,758 10,719 25,244 NEW Patterns 2,435 11,085 15,732 4,187 4,485 5,884 Improvement Ratios 1.2X 0.8X 1.8X 2.8X 2.4X 4.3X Average 2X Improvement in Compression 28

29 Integrating Physical Verification and Test D Layout view A A E Logic view B Possible bridging sites C 29

30 Nanometer Technologies: Where Design and Manufacturing Converge Nanometer technologies make designers aware of manufacturing challenges Resolution enhancement technology will proliferate Parallel processing, multi-threading and hierarchical analysis will be mandatory Design for Manufacturing will be a major EDA requirement New silicon modeling and analysis will be required Design for Manufacturing and Design for Test must merge 30

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