Direct calculation of metal oxide semiconductor field effect transistor high frequency noise parameters

Transcription

1 Direct calculation of metal oxide semiconductor field effect transistor high frequency noise parameters C. H. Chen and M. J. Deen a) Engineering Science, Simon Fraser University, Burnaby, British Columbia V5A 1S6, Canada Received 12 August 1997; accepted 28 November 1997 This article presents, for the first time, a method to directly calculate the noise parameters minimum noise figure NF min, equivalent noise resistance R n, and optimized source resistance R opt and reactance X opt of metal oxide semiconductor field effect transistors based on the HSPICE level 3 model because all the model parameters are available from the manufacturer of our device-under-test. All physically based high frequency noise sources, thermal noise from the channel, gate, source and drain resistances, induced gate noise, and the correlation among them, are considered, and the impact of gate resistance and induced gate noise on the noise parameters is studied. The method of direct calculation of noise parameters can be applied to any sophisticated small-signal device model American Vacuum Society. S I. INTRODUCTION The downscaling of metal oxide semiconductor field effect transistor MOSFET dimensions to deep-submicron values and the resulting very high unity-gain frequencies of tens of GHz makes MOSFETs increasingly attractive for microwave applications. 1 However, at high frequencies, the effect of the noise generated within the device itself will play an increasingly important role in the overall system sensitivity characteristics, dynamic range, and signal-to-noise ratio. Therefore, it is crucial that we understand the noise mechanisms within submicron MOSFETs, and develop an appropriate physically based noise model that can accurately predict the noise performance of transistors over a wide range of operating conditions of frequencies, currents, and device geometries. To date, some of the noise models including physical noise mechanisms are based on simplified small-signal models which cannot accurately predict the ac performance of transistors. 2 Others based on very accurate ac models neglect an important high-frequency noise source, the gate resistance thermal noise, and the impacts of velocity saturation and hot-electron effects on the thermal noise in the channel, and so cannot be used for high-frequency noise predictions. 3 Our goal is to develop a new model which can predict not only the ac characteristics but also the noise performance of transistors. This work is an extension of our earlier research on noise modeling of polysilicon emitter bipolar transistors. 4 9 II. NOISE MODEL Our noise model is based on the widely used HSPICE level 3 model 3 including the gate parasitic resistance R G, channel resistance R i, and substrate resistance R DB and includes all physically based high-frequency noise sources thermal noise, induced gate noise, and the correlations among them 10 2 shown in Fig. 1. In this model, i G 4kT/R G, i 2 S 4kT/R S, i 2 D 4kT/R D, i 2 d sat1 4kT g do, i 2 g sat1 4kT 2 C /g do, i g i d * sat1 4kT sc 0, and i DB FIG. 1. Our noise circuit model. a Electronic mail: jamal@cs.sfu.ca FIG. 2. Graph and cut set of Fig J. Vac. Sci. Technol. A 16 2, Mar/Apr /98/16 2 /850/5/$ American Vacuum Society 850

2 851 C. H. Chen and M. J. Deen: Direct calculation of MOSFET noise parameters 851 4kT/R DB where sat1, sat1, and sat1 are constants which depend on device geometries and bias conditions. Byextracting parameters from the dc and scattering parameter measurements, we can obtain all the values of the elements, g m, capacitances and resistances corresponding to different bias conditions or device geometries, and use these values to calculate the noise parameters. III. DIRECT CALCULATION OF MOSFET NOISE PARAMETERS In order to perform the direct analysis of the noisy two port model shown in Fig. 1, we transform our noisy circuit model into its graph form shown in Fig. 2 and write the node equations corresponding to each node subset, given by Y 1 0 Y Y 3 0 Y Y 1 0 Y 1 Y 2 Y 4 Y 6 Y 2 Y Y 3 g m Y 2 Y 2 Y 3 Y 5 Y 8 g m Y 5 Y g m Y 4 Y 5 g m Y 4 Y 5 Y V Y 8 0 Y 8 Y V V 2 V 3 V 4 V ig i d I 2 i G 0 i S 0 i D 0 i DB I1 0, 1 where Y 1 1/R G, Y 2 SC GD, Y 3 1/R D, Y 4 SC GS, Y 5 1/R DS, Y 6 SC GB, Y 7 1/R S SC SB, Y 8 SC DB, and Y 9 1/R DB. Once the matrix equations are formulated, the network is reduced by eliminating four nodes, nodes 6, 5, 4, and 3, one by one, leaving only the input and output nodes nodes 1 and 2. For example, we eliminate node 6 first, then each element of Y and A not in row 6 will be transformed according to the following formulas: Y ij Y ij Y 6j Y i6 1 i 6 1 j 6, 2 Y 66 A ij A ij A 6j Y i6 1 i 6 1 j 6. 3 Y 66 Row 6 and column 6 are deleted from the Y matrix at the first step; however only the 6th row of A is deleted and 6 columns remain. This procedure is followed until only the input and output nodes remain, and then the Y matrix at this time is 2 2, and the A matrix is 2 6 with complex elements. Now we define the B and D matrixes by A B D, and the correlation matrix C of our noise circuit model is 4 igid* i d i g * i d i d * i G i G * C igig* i S i S * i D i D * i DB i DB * After the Y, A, B, and C matrixes of the noise circuit are obtained, the four noise parameters can be calculated directly by Eqs R u 1 4kT Re 1 2 D * C D T, G i 1 4kT f Re B Y 11 * C B Y 11 Y cor G cor jb cor 1 4kT fr n R n R u, T, * D * C B Y 11 T, JVST A - Vacuum, Surfaces, and Films

3 852 C. H. Chen and M. J. Deen: Direct calculation of MOSFET noise parameters 852 FIG. 3. Measured symbols and simulated dashed lines of NF min and R n vs current characteristics for a 0.8 m n-type Si MOSFET (W 1 60 m) operating at 4 GHz. FIG. 5. Measured symbols and simulated dashed line phase of sop vs current characteristics for a 0.8 m n-type Si MOSFET (W 1 60 m) operating at 4 GHz. G opt G i R n B 2 cor, B opt B cor, NF min 1 2R n G cor G opt IV. COMPARISON WITH EXPERIMENTS Our device-under-test DUT is a 0.8 m n-type Si MOS- FET with 60 m channel width and is fabricated in 0.8 m BiCMOS technology by Canadian Microelectronics Corporation CMC. Before performing direct calculation of the noise parameters for intrinsic devices, we obtain the model parameters, g m, capacitances and resistances, from the dc and scattering parameter measurements by optimization. In addition, because of the difficulty of directly de-embedding noise effects from the probe pads, we model the pads of the DUT from the measurements of dummy pads and combine the pad model with the intrinsic device model Fig. 1 to form the DUT model. Based on the DUT model, we confirm our model and method by comparing the simulation data against experimental data. Our noise model takes into account the following noise sources: channel noise (i d ), noise due to the gate resistance (i G ) and the resistance between the drain and bulk (i DB ), induced gate noise (i g ) and its correlation with i d, thermal noise in the source (i S ) and drain (i D ) parasitic resistance. However, for state-of-the-art MOSFETs with high quality gate insulators, the induced gate noise and its correlation with the channel noise are negligible. Therefore, the simulated data shown in the following figures do not include the induced gate noise and its correlation with the channel noise. Figure 3 shows the characteristics of NF min, and R n versus bias current. It is shown that for a low noise circuit design it would be best to bias the device at around 3 ma for V DS 3 V because of the lowest NF min and R n. Figures 4 and 5 show characteristics of the optimized reflection coefficient of source impedance ( opt ) versus bias conditions. As for the characteristics of noise parameters versus frequency Figs. FIG. 4. Measured symbols and simulated dashed line magnitude of sop vs current characteristics for a 0.8 m n-type Si MOSFET (W 1 60 m) operating at 4 GHz. FIG. 6. Measured symbols and simulated dashed lines of NF min and R n vs frequency characteristics for a 0.8 m n-type Si MOSFET (W 1 J. Vac. Sci. Technol. A, Vol. 16, No. 2, Mar/Apr 1998

4 853 C. H. Chen and M. J. Deen: Direct calculation of MOSFET noise parameters 853 FIG. 7. Measured symbols and simulated dashed line magnitude of sop vs frequency characteristics for a 0.8 m n-type Si MOSFET (W 1 FIG. 9. Probe pad effect on NF min for a 0.8 m n-type Si MOSFET (W 1 The probe pads will contribute about 0.7 db to NF min. 6 8, it is shown that NF min is in general, proportional to frequency and R n increases with frequency as well. De-embedding the probe pad effects is very important in obtaining the ac and noise characteristics of intrinsic devices. In this work, the probe pad was modeled as C p1 parallel to (C p2 R p ) and these three parameters were extracted from the measured s-parameter data of dummy pads. Figure 9 shows that the probe pads contribute about 0.7 db to NF min. The impact of gate resistance affects not only the overall noise performance of the devices but also the maximum oscillation frequency ( f max ). 1 In order to increase f max by way of reducing R G, two approaches were investigated. 1,11 One involves metal-reinforced gates and the other employs multifinger gates. The first approach reduces R GSH so as to reduce R G and increase f max. This approach can achieve the goals of reducing the overall noise level and increasing the f max but requires changes to the fabrication process. The multifinger design in which there are six 10 m wide transistors connected in parallel to reduce R G based on the existing technology will increase not only f max but will also improve the overall noise performance. It is shown in Fig. 10 that the use of multifinger gates will reduce NF min because of reduced R G. V. CONCLUSIONS In this article, a new noise model which is based on the widely used HSPICE level 3 model and includes all the highfrequency noise sources and the correlations among them is developed for the first time. A direct calculation method allows us to easily calculate the four noise parameters of the transistors and the impact of individual noise sources. On the other hand, variations of the noise parameters with bias conditions and frequency which are important for low noise rf analog circuit design can be easily calculated as well. Finally, we obtained good agreement between the calculations and experimental data for NF min, R n and opt. FIG. 8. Measured symbols and simulated dashed line phase of sop vs frequency characteristics for a 0.8 m n-type Si MOSFET (W 1 FIG. 10. Measured NF min of multifinger gates and a single 60 m wide transistor vs current characteristics for 0.8 m n-type Si MOSFETs operating at 4 GHz. JVST A - Vacuum, Surfaces, and Films

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